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a003708a | 1 | /* |
e24798e6 | 2 | * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
a003708a AK |
3 | * |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/moduleparam.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/io.h> | |
18 | ||
19 | #include <asm/mach/irq.h> | |
20 | ||
21 | #include <mach/hardware.h> | |
e24798e6 | 22 | #include <mach/common.h> |
a003708a | 23 | |
cdc3f106 PH |
24 | #include "irq-common.h" |
25 | ||
a003708a AK |
26 | /* |
27 | ***************************************** | |
28 | * TZIC Registers * | |
29 | ***************************************** | |
30 | */ | |
31 | ||
32 | #define TZIC_INTCNTL 0x0000 /* Control register */ | |
33 | #define TZIC_INTTYPE 0x0004 /* Controller Type register */ | |
34 | #define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */ | |
35 | #define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */ | |
36 | #define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */ | |
37 | #define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */ | |
38 | #define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */ | |
39 | #define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */ | |
40 | #define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */ | |
41 | #define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */ | |
42 | #define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */ | |
43 | #define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */ | |
44 | #define TZIC_PND0 0x0D00 /* Pending Register 0 */ | |
45 | #define TZIC_HIPND0 0x0D80 /* High Priority Pending Register */ | |
46 | #define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */ | |
47 | #define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */ | |
48 | #define TZIC_ID0 0x0FD0 /* Indentification Register 0 */ | |
49 | ||
50 | void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ | |
51 | ||
fe31ad41 SH |
52 | #define TZIC_NUM_IRQS 128 |
53 | ||
cdc3f106 PH |
54 | #ifdef CONFIG_FIQ |
55 | static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) | |
56 | { | |
57 | unsigned int index, mask, value; | |
58 | ||
59 | index = irq >> 5; | |
60 | if (unlikely(index >= 4)) | |
61 | return -EINVAL; | |
62 | mask = 1U << (irq & 0x1F); | |
63 | ||
64 | value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask; | |
65 | if (type) | |
66 | value &= ~mask; | |
67 | __raw_writel(value, tzic_base + TZIC_INTSEC0(index)); | |
68 | ||
69 | return 0; | |
70 | } | |
71 | #endif | |
72 | ||
a003708a | 73 | /** |
4d93579f | 74 | * tzic_mask_irq() - Disable interrupt source "d" in the TZIC |
a003708a | 75 | * |
4d93579f | 76 | * @param d interrupt source |
a003708a | 77 | */ |
4d93579f | 78 | static void tzic_mask_irq(struct irq_data *d) |
a003708a AK |
79 | { |
80 | int index, off; | |
81 | ||
4d93579f LB |
82 | index = d->irq >> 5; |
83 | off = d->irq & 0x1F; | |
a003708a AK |
84 | __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index)); |
85 | } | |
86 | ||
87 | /** | |
4d93579f | 88 | * tzic_unmask_irq() - Enable interrupt source "d" in the TZIC |
a003708a | 89 | * |
4d93579f | 90 | * @param d interrupt source |
a003708a | 91 | */ |
4d93579f | 92 | static void tzic_unmask_irq(struct irq_data *d) |
a003708a AK |
93 | { |
94 | int index, off; | |
95 | ||
4d93579f LB |
96 | index = d->irq >> 5; |
97 | off = d->irq & 0x1F; | |
a003708a AK |
98 | __raw_writel(1 << off, tzic_base + TZIC_ENSET0(index)); |
99 | } | |
100 | ||
101 | static unsigned int wakeup_intr[4]; | |
102 | ||
103 | /** | |
4d93579f | 104 | * tzic_set_wake_irq() - Set interrupt source "d" in the TZIC as a wake-up source. |
a003708a | 105 | * |
4d93579f | 106 | * @param d interrupt source |
a003708a AK |
107 | * @param enable enable as wake-up if equal to non-zero |
108 | * disble as wake-up if equal to zero | |
109 | * | |
110 | * @return This function returns 0 on success. | |
111 | */ | |
4d93579f | 112 | static int tzic_set_wake_irq(struct irq_data *d, unsigned int enable) |
a003708a AK |
113 | { |
114 | unsigned int index, off; | |
115 | ||
4d93579f LB |
116 | index = d->irq >> 5; |
117 | off = d->irq & 0x1F; | |
a003708a AK |
118 | |
119 | if (index > 3) | |
120 | return -EINVAL; | |
121 | ||
122 | if (enable) | |
123 | wakeup_intr[index] |= (1 << off); | |
124 | else | |
125 | wakeup_intr[index] &= ~(1 << off); | |
126 | ||
127 | return 0; | |
128 | } | |
129 | ||
cdc3f106 PH |
130 | static struct mxc_irq_chip mxc_tzic_chip = { |
131 | .base = { | |
132 | .name = "MXC_TZIC", | |
4d93579f LB |
133 | .irq_ack = tzic_mask_irq, |
134 | .irq_mask = tzic_mask_irq, | |
135 | .irq_unmask = tzic_unmask_irq, | |
136 | .irq_set_wake = tzic_set_wake_irq, | |
cdc3f106 PH |
137 | }, |
138 | #ifdef CONFIG_FIQ | |
139 | .set_irq_fiq = tzic_set_irq_fiq, | |
140 | #endif | |
a003708a AK |
141 | }; |
142 | ||
143 | /* | |
144 | * This function initializes the TZIC hardware and disables all the | |
145 | * interrupts. It registers the interrupt enable and disable functions | |
146 | * to the kernel for each interrupt source. | |
147 | */ | |
148 | void __init tzic_init_irq(void __iomem *irqbase) | |
149 | { | |
150 | int i; | |
151 | ||
152 | tzic_base = irqbase; | |
153 | /* put the TZIC into the reset value with | |
154 | * all interrupts disabled | |
155 | */ | |
156 | i = __raw_readl(tzic_base + TZIC_INTCNTL); | |
157 | ||
158 | __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL); | |
159 | __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK); | |
160 | __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL); | |
161 | ||
162 | for (i = 0; i < 4; i++) | |
163 | __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i)); | |
164 | ||
165 | /* disable all interrupts */ | |
166 | for (i = 0; i < 4; i++) | |
167 | __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i)); | |
168 | ||
169 | /* all IRQ no FIQ Warning :: No selection */ | |
170 | ||
fe31ad41 | 171 | for (i = 0; i < TZIC_NUM_IRQS; i++) { |
f38c02f3 TG |
172 | irq_set_chip_and_handler(i, &mxc_tzic_chip.base, |
173 | handle_level_irq); | |
a003708a AK |
174 | set_irq_flags(i, IRQF_VALID); |
175 | } | |
cdc3f106 PH |
176 | |
177 | #ifdef CONFIG_FIQ | |
178 | /* Initialize FIQ */ | |
179 | init_FIQ(); | |
180 | #endif | |
181 | ||
a003708a AK |
182 | pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); |
183 | } | |
184 | ||
185 | /** | |
186 | * tzic_enable_wake() - enable wakeup interrupt | |
187 | * | |
188 | * @param is_idle 1 if called in idle loop (ENSET0 register); | |
189 | * 0 to be used when called from low power entry | |
190 | * @return 0 if successful; non-zero otherwise | |
191 | */ | |
192 | int tzic_enable_wake(int is_idle) | |
193 | { | |
194 | unsigned int i, v; | |
195 | ||
196 | __raw_writel(1, tzic_base + TZIC_DSMINT); | |
197 | if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0)) | |
198 | return -EAGAIN; | |
199 | ||
200 | for (i = 0; i < 4; i++) { | |
a38b372f JW |
201 | v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) : |
202 | wakeup_intr[i]; | |
203 | __raw_writel(v, tzic_base + TZIC_WAKEUP0(i)); | |
a003708a AK |
204 | } |
205 | ||
206 | return 0; | |
207 | } |