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plat-nomadik: change sleep/wakeup setting in GPIO SLPM register
[deliverable/linux.git] / arch / arm / plat-nomadik / gpio.c
CommitLineData
2ec1d359
AR		 1/*
2 * Generic GPIO driver for logic cells found in the Nomadik SoC
3 *
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/device.h>
3e3c62ca 16#include <linux/platform_device.h>
2ec1d359 17#include <linux/io.h>
af7dc228
RV		 18#include <linux/clk.h>
19#include <linux/err.h>
2ec1d359
AR		 20#include <linux/gpio.h>
21#include <linux/spinlock.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
5a0e3ad6 24#include <linux/slab.h>
2ec1d359 25
378be066 26#include <plat/pincfg.h>
2ec1d359
AR		 27#include <mach/hardware.h>
28#include <mach/gpio.h>
29
30/*
31 * The GPIO module in the Nomadik family of Systems-on-Chip is an
32 * AMBA device, managing 32 pins and alternate functions. The logic block
9c66ee6f 33 * is currently used in the Nomadik and ux500.
2ec1d359
AR		 34 *
35 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
36 */
37
9c66ee6f
JA		 38static const u32 backup_regs[] = {
39 NMK_GPIO_PDIS,
40 NMK_GPIO_DIR,
41 NMK_GPIO_AFSLA,
42 NMK_GPIO_AFSLB,
43 NMK_GPIO_SLPC,
44 NMK_GPIO_RIMSC,
45 NMK_GPIO_FIMSC,
46 NMK_GPIO_RWIMSC,
47 NMK_GPIO_FWIMSC,
48};
49
01727e61
RV		 50#define NMK_GPIO_PER_CHIP 32
51
2ec1d359
AR		 52struct nmk_gpio_chip {
53 struct gpio_chip chip;
54 void __iomem *addr;
af7dc228 55 struct clk *clk;
33b744b3 56 unsigned int bank;
2ec1d359 57 unsigned int parent_irq;
2c8bb0eb 58 int secondary_parent_irq;
33b744b3 59 u32 (*get_secondary_status)(unsigned int bank);
01727e61 60 void (*set_ioforce)(bool enable);
c0fcb8db 61 spinlock_t lock;
2ec1d359
AR		 62 /* Keep track of configured edges */
63 u32 edge_rising;
64 u32 edge_falling;
9c66ee6f
JA		 65 u32 backup[ARRAY_SIZE(backup_regs)];
66 /* Bitmap, 1 = pull up, 0 = pull down */
67 u32 pull;
2ec1d359
AR		 68};
69
01727e61
RV		 70static struct nmk_gpio_chip *
71nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
72
73static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
74
75#define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
76
6f9a974c
RV		 77static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
78 unsigned offset, int gpio_mode)
79{
80 u32 bit = 1 << offset;
81 u32 afunc, bfunc;
82
83 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
84 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
85 if (gpio_mode & NMK_GPIO_ALT_A)
86 afunc |= bit;
87 if (gpio_mode & NMK_GPIO_ALT_B)
88 bfunc |= bit;
89 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
90 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
91}
92
81a3c298
RV		 93static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
94 unsigned offset, enum nmk_gpio_slpm mode)
95{
96 u32 bit = 1 << offset;
97 u32 slpm;
98
99 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
100 if (mode == NMK_GPIO_SLPM_NOCHANGE)
101 slpm |= bit;
102 else
103 slpm &= ~bit;
104 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
105}
106
5b327edf
RV		 107static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
108 unsigned offset, enum nmk_gpio_pull pull)
109{
110 u32 bit = 1 << offset;
111 u32 pdis;
112
113 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
114 if (pull == NMK_GPIO_PULL_NONE)
115 pdis |= bit;
116 else
117 pdis &= ~bit;
118 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
119
9c66ee6f
JA		 120 if (pull == NMK_GPIO_PULL_UP) {
121 nmk_chip->pull |= bit;
5b327edf 122 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
9c66ee6f
JA		 123 } else if (pull == NMK_GPIO_PULL_DOWN) {
124 nmk_chip->pull &= ~bit;
5b327edf 125 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
9c66ee6f 126 }
5b327edf
RV		 127}
128
378be066
RV		 129static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
130 unsigned offset)
131{
132 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
133}
134
6720db7c
RV		 135static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
136 unsigned offset, int val)
137{
138 if (val)
139 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
140 else
141 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
142}
143
144static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
145 unsigned offset, int val)
146{
147 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
148 __nmk_gpio_set_output(nmk_chip, offset, val);
149}
150
01727e61
RV		 151static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
152 unsigned offset, int gpio_mode,
153 bool glitch)
154{
155 u32 rwimsc;
156 u32 fwimsc;
157
158 if (glitch && nmk_chip->set_ioforce) {
159 u32 bit = BIT(offset);
160
161 rwimsc = readl(nmk_chip->addr + NMK_GPIO_RWIMSC);
162 fwimsc = readl(nmk_chip->addr + NMK_GPIO_FWIMSC);
163
164 /* Prevent spurious wakeups */
165 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
166 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
167
168 nmk_chip->set_ioforce(true);
169 }
170
171 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
172
173 if (glitch && nmk_chip->set_ioforce) {
174 nmk_chip->set_ioforce(false);
175
176 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
177 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
178 }
179}
180
378be066 181static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
01727e61 182 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
378be066
RV		 183{
184 static const char *afnames[] = {
185 [NMK_GPIO_ALT_GPIO] = "GPIO",
186 [NMK_GPIO_ALT_A] = "A",
187 [NMK_GPIO_ALT_B] = "B",
188 [NMK_GPIO_ALT_C] = "C"
189 };
190 static const char *pullnames[] = {
191 [NMK_GPIO_PULL_NONE] = "none",
192 [NMK_GPIO_PULL_UP] = "up",
193 [NMK_GPIO_PULL_DOWN] = "down",
194 [3] /* illegal */ = "??"
195 };
196 static const char *slpmnames[] = {
7e3f7e59
RV		 197 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
198 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
378be066
RV		 199 };
200
201 int pin = PIN_NUM(cfg);
202 int pull = PIN_PULL(cfg);
203 int af = PIN_ALT(cfg);
204 int slpm = PIN_SLPM(cfg);
6720db7c
RV		 205 int output = PIN_DIR(cfg);
206 int val = PIN_VAL(cfg);
01727e61 207 bool glitch = af == NMK_GPIO_ALT_C;
378be066 208
dacdc96c
RV		 209 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
210 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
6720db7c
RV		 211 output ? "output " : "input",
212 output ? (val ? "high" : "low") : "");
213
dacdc96c
RV		 214 if (sleep) {
215 int slpm_pull = PIN_SLPM_PULL(cfg);
216 int slpm_output = PIN_SLPM_DIR(cfg);
217 int slpm_val = PIN_SLPM_VAL(cfg);
218
3546d15c
RV		 219 af = NMK_GPIO_ALT_GPIO;
220
dacdc96c
RV		 221 /*
222 * The SLPM_* values are normal values + 1 to allow zero to
223 * mean "same as normal".
224 */
225 if (slpm_pull)
226 pull = slpm_pull - 1;
227 if (slpm_output)
228 output = slpm_output - 1;
229 if (slpm_val)
230 val = slpm_val - 1;
231
232 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
233 pin,
234 slpm_pull ? pullnames[pull] : "same",
235 slpm_output ? (output ? "output" : "input") : "same",
236 slpm_val ? (val ? "high" : "low") : "same");
237 }
238
6720db7c
RV		 239 if (output)
240 __nmk_gpio_make_output(nmk_chip, offset, val);
241 else {
242 __nmk_gpio_make_input(nmk_chip, offset);
243 __nmk_gpio_set_pull(nmk_chip, offset, pull);
244 }
378be066 245
01727e61
RV		 246 /*
247 * If we've backed up the SLPM registers (glitch workaround), modify
248 * the backups since they will be restored.
249 */
250 if (slpmregs) {
251 if (slpm == NMK_GPIO_SLPM_NOCHANGE)
252 slpmregs[nmk_chip->bank] |= BIT(offset);
253 else
254 slpmregs[nmk_chip->bank] &= ~BIT(offset);
255 } else
256 __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
257
258 __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
259}
260
261/*
262 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
263 * - Save SLPM registers
264 * - Set SLPM=0 for the IOs you want to switch and others to 1
265 * - Configure the GPIO registers for the IOs that are being switched
266 * - Set IOFORCE=1
267 * - Modify the AFLSA/B registers for the IOs that are being switched
268 * - Set IOFORCE=0
269 * - Restore SLPM registers
270 * - Any spurious wake up event during switch sequence to be ignored and
271 * cleared
272 */
273static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
274{
275 int i;
276
277 for (i = 0; i < NUM_BANKS; i++) {
278 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
279 unsigned int temp = slpm[i];
280
281 if (!chip)
282 break;
283
284 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
285 writel(temp, chip->addr + NMK_GPIO_SLPC);
286 }
287}
288
289static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
290{
291 int i;
292
293 for (i = 0; i < NUM_BANKS; i++) {
294 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
295
296 if (!chip)
297 break;
298
299 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
300 }
301}
302
303static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
304{
305 static unsigned int slpm[NUM_BANKS];
306 unsigned long flags;
307 bool glitch = false;
308 int ret = 0;
309 int i;
310
311 for (i = 0; i < num; i++) {
312 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
313 glitch = true;
314 break;
315 }
316 }
317
318 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
319
320 if (glitch) {
321 memset(slpm, 0xff, sizeof(slpm));
322
323 for (i = 0; i < num; i++) {
324 int pin = PIN_NUM(cfgs[i]);
325 int offset = pin % NMK_GPIO_PER_CHIP;
326
327 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
328 slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
329 }
330
331 nmk_gpio_glitch_slpm_init(slpm);
332 }
333
334 for (i = 0; i < num; i++) {
335 struct nmk_gpio_chip *nmk_chip;
336 int pin = PIN_NUM(cfgs[i]);
337
338 nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(pin));
339 if (!nmk_chip) {
340 ret = -EINVAL;
341 break;
342 }
343
344 spin_lock(&nmk_chip->lock);
345 __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base,
346 cfgs[i], sleep, glitch ? slpm : NULL);
347 spin_unlock(&nmk_chip->lock);
348 }
349
350 if (glitch)
351 nmk_gpio_glitch_slpm_restore(slpm);
352
353 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
354
355 return ret;
378be066
RV		 356}
357
358/**
359 * nmk_config_pin - configure a pin's mux attributes
360 * @cfg: pin confguration
361 *
362 * Configures a pin's mode (alternate function or GPIO), its pull up status,
363 * and its sleep mode based on the specified configuration. The @cfg is
364 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
365 * are constructed using, and can be further enhanced with, the macros in
366 * plat/pincfg.h.
367 *
368 * If a pin's mode is set to GPIO, it is configured as an input to avoid
369 * side-effects. The gpio can be manipulated later using standard GPIO API
370 * calls.
371 */
dacdc96c 372int nmk_config_pin(pin_cfg_t cfg, bool sleep)
378be066 373{
01727e61 374 return __nmk_config_pins(&cfg, 1, sleep);
378be066
RV		 375}
376EXPORT_SYMBOL(nmk_config_pin);
377
378/**
379 * nmk_config_pins - configure several pins at once
380 * @cfgs: array of pin configurations
381 * @num: number of elments in the array
382 *
383 * Configures several pins using nmk_config_pin(). Refer to that function for
384 * further information.
385 */
386int nmk_config_pins(pin_cfg_t *cfgs, int num)
387{
01727e61 388 return __nmk_config_pins(cfgs, num, false);
378be066
RV		 389}
390EXPORT_SYMBOL(nmk_config_pins);
391
dacdc96c
RV		 392int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
393{
01727e61 394 return __nmk_config_pins(cfgs, num, true);
dacdc96c
RV		 395}
396EXPORT_SYMBOL(nmk_config_pins_sleep);
397
81a3c298
RV		 398/**
399 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
400 * @gpio: pin number
401 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
402 *
403 * Sets the sleep mode of a pin. If @mode is NMK_GPIO_SLPM_INPUT, the pin is
404 * changed to an input (with pullup/down enabled) in sleep and deep sleep. If
405 * @mode is NMK_GPIO_SLPM_NOCHANGE, the pin remains in the state it was
406 * configured even when in sleep and deep sleep.
7e3f7e59
RV		 407 *
408 * On DB8500v2 onwards, this setting loses the previous meaning and instead
409 * indicates if wakeup detection is enabled on the pin. Note that
410 * enable_irq_wake() will automatically enable wakeup detection.
81a3c298
RV		 411 */
412int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
413{
414 struct nmk_gpio_chip *nmk_chip;
415 unsigned long flags;
416
417 nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
418 if (!nmk_chip)
419 return -EINVAL;
420
01727e61
RV		 421 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
422 spin_lock(&nmk_chip->lock);
423
81a3c298 424 __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode);
01727e61
RV		 425
426 spin_unlock(&nmk_chip->lock);
427 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
81a3c298
RV		 428
429 return 0;
430}
431
5b327edf
RV		 432/**
433 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
434 * @gpio: pin number
435 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
436 *
437 * Enables/disables pull up/down on a specified pin. This only takes effect if
438 * the pin is configured as an input (either explicitly or by the alternate
439 * function).
440 *
441 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
442 * configured as an input. Otherwise, due to the way the controller registers
443 * work, this function will change the value output on the pin.
444 */
445int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
446{
447 struct nmk_gpio_chip *nmk_chip;
448 unsigned long flags;
449
450 nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
451 if (!nmk_chip)
452 return -EINVAL;
453
454 spin_lock_irqsave(&nmk_chip->lock, flags);
455 __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull);
456 spin_unlock_irqrestore(&nmk_chip->lock, flags);
457
458 return 0;
459}
460
2ec1d359 461/* Mode functions */
9c66ee6f
JA		 462/**
463 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
464 * @gpio: pin number
465 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
466 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
467 *
468 * Sets the mode of the specified pin to one of the alternate functions or
469 * plain GPIO.
470 */
2ec1d359
AR		 471int nmk_gpio_set_mode(int gpio, int gpio_mode)
472{
473 struct nmk_gpio_chip *nmk_chip;
474 unsigned long flags;
2ec1d359
AR		 475
476 nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
477 if (!nmk_chip)
478 return -EINVAL;
479
2ec1d359 480 spin_lock_irqsave(&nmk_chip->lock, flags);
6f9a974c 481 __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode);
2ec1d359
AR		 482 spin_unlock_irqrestore(&nmk_chip->lock, flags);
483
484 return 0;
485}
486EXPORT_SYMBOL(nmk_gpio_set_mode);
487
488int nmk_gpio_get_mode(int gpio)
489{
490 struct nmk_gpio_chip *nmk_chip;
491 u32 afunc, bfunc, bit;
492
493 nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
494 if (!nmk_chip)
495 return -EINVAL;
496
497 bit = 1 << (gpio - nmk_chip->chip.base);
498
499 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
500 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
501
502 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
503}
504EXPORT_SYMBOL(nmk_gpio_get_mode);
505
506
507/* IRQ functions */
508static inline int nmk_gpio_get_bitmask(int gpio)
509{
510 return 1 << (gpio % 32);
511}
512
f272c00e 513static void nmk_gpio_irq_ack(struct irq_data *d)
2ec1d359
AR		 514{
515 int gpio;
516 struct nmk_gpio_chip *nmk_chip;
517
f272c00e
LB		 518 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
519 nmk_chip = irq_data_get_irq_chip_data(d);
2ec1d359
AR		 520 if (!nmk_chip)
521 return;
522 writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC);
523}
524
4d4e20f7
RV		 525enum nmk_gpio_irq_type {
526 NORMAL,
527 WAKE,
528};
529
040e5ecd 530static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
4d4e20f7
RV		 531 int gpio, enum nmk_gpio_irq_type which,
532 bool enable)
2ec1d359 533{
4d4e20f7
RV		 534 u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC;
535 u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC;
040e5ecd
RV		 536 u32 bitmask = nmk_gpio_get_bitmask(gpio);
537 u32 reg;
2ec1d359 538
040e5ecd 539 /* we must individually set/clear the two edges */
2ec1d359 540 if (nmk_chip->edge_rising & bitmask) {
4d4e20f7 541 reg = readl(nmk_chip->addr + rimsc);
040e5ecd
RV		 542 if (enable)
543 reg |= bitmask;
544 else
545 reg &= ~bitmask;
4d4e20f7 546 writel(reg, nmk_chip->addr + rimsc);
2ec1d359
AR		 547 }
548 if (nmk_chip->edge_falling & bitmask) {
4d4e20f7 549 reg = readl(nmk_chip->addr + fimsc);
040e5ecd
RV		 550 if (enable)
551 reg |= bitmask;
552 else
553 reg &= ~bitmask;
4d4e20f7 554 writel(reg, nmk_chip->addr + fimsc);
2ec1d359 555 }
040e5ecd 556}
2ec1d359 557
f272c00e 558static int nmk_gpio_irq_modify(struct irq_data *d, enum nmk_gpio_irq_type which,
4d4e20f7 559 bool enable)
2ec1d359
AR		 560{
561 int gpio;
562 struct nmk_gpio_chip *nmk_chip;
563 unsigned long flags;
040e5ecd 564 u32 bitmask;
2ec1d359 565
f272c00e
LB		 566 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
567 nmk_chip = irq_data_get_irq_chip_data(d);
2ec1d359
AR		 568 bitmask = nmk_gpio_get_bitmask(gpio);
569 if (!nmk_chip)
4d4e20f7 570 return -EINVAL;
2ec1d359 571
2ec1d359 572 spin_lock_irqsave(&nmk_chip->lock, flags);
4d4e20f7 573 __nmk_gpio_irq_modify(nmk_chip, gpio, which, enable);
2ec1d359 574 spin_unlock_irqrestore(&nmk_chip->lock, flags);
4d4e20f7
RV		 575
576 return 0;
2ec1d359
AR		 577}
578
f272c00e 579static void nmk_gpio_irq_mask(struct irq_data *d)
040e5ecd 580{
f272c00e 581 nmk_gpio_irq_modify(d, NORMAL, false);
4d4e20f7 582}
040e5ecd 583
f272c00e 584static void nmk_gpio_irq_unmask(struct irq_data *d)
040e5ecd 585{
f272c00e 586 nmk_gpio_irq_modify(d, NORMAL, true);
4d4e20f7
RV		 587}
588
f272c00e 589static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
4d4e20f7 590{
7e3f7e59
RV		 591 struct nmk_gpio_chip *nmk_chip;
592 unsigned long flags;
593 int gpio;
594
f272c00e
LB		 595 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
596 nmk_chip = irq_data_get_irq_chip_data(d);
7e3f7e59
RV		 597 if (!nmk_chip)
598 return -EINVAL;
599
01727e61
RV		 600 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
601 spin_lock(&nmk_chip->lock);
602
7e3f7e59
RV		 603#ifdef CONFIG_ARCH_U8500
604 if (cpu_is_u8500v2()) {
8b40eeea 605 __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base,
7e3f7e59
RV		 606 on ? NMK_GPIO_SLPM_WAKEUP_ENABLE
607 : NMK_GPIO_SLPM_WAKEUP_DISABLE);
608 }
609#endif
610 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
01727e61
RV		 611
612 spin_unlock(&nmk_chip->lock);
613 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
7e3f7e59
RV		 614
615 return 0;
040e5ecd
RV		 616}
617
f272c00e 618static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
2ec1d359 619{
f272c00e 620 struct irq_desc *desc = irq_to_desc(d->irq);
4d4e20f7
RV		 621 bool enabled = !(desc->status & IRQ_DISABLED);
622 bool wake = desc->wake_depth;
2ec1d359
AR		 623 int gpio;
624 struct nmk_gpio_chip *nmk_chip;
625 unsigned long flags;
626 u32 bitmask;
627
f272c00e
LB		 628 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
629 nmk_chip = irq_data_get_irq_chip_data(d);
2ec1d359
AR		 630 bitmask = nmk_gpio_get_bitmask(gpio);
631 if (!nmk_chip)
632 return -EINVAL;
633
634 if (type & IRQ_TYPE_LEVEL_HIGH)
635 return -EINVAL;
636 if (type & IRQ_TYPE_LEVEL_LOW)
637 return -EINVAL;
638
639 spin_lock_irqsave(&nmk_chip->lock, flags);
640
7a852d80 641 if (enabled)
4d4e20f7
RV		 642 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false);
643
644 if (wake)
645 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false);
7a852d80 646
2ec1d359
AR		 647 nmk_chip->edge_rising &= ~bitmask;
648 if (type & IRQ_TYPE_EDGE_RISING)
649 nmk_chip->edge_rising |= bitmask;
2ec1d359
AR		 650
651 nmk_chip->edge_falling &= ~bitmask;
652 if (type & IRQ_TYPE_EDGE_FALLING)
653 nmk_chip->edge_falling |= bitmask;
2ec1d359 654
7a852d80 655 if (enabled)
4d4e20f7
RV		 656 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true);
657
658 if (wake)
659 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true);
2ec1d359 660
7a852d80 661 spin_unlock_irqrestore(&nmk_chip->lock, flags);
2ec1d359
AR		 662
663 return 0;
664}
665
666static struct irq_chip nmk_gpio_irq_chip = {
667 .name = "Nomadik-GPIO",
f272c00e
LB		 668 .irq_ack = nmk_gpio_irq_ack,
669 .irq_mask = nmk_gpio_irq_mask,
670 .irq_unmask = nmk_gpio_irq_unmask,
671 .irq_set_type = nmk_gpio_irq_set_type,
672 .irq_set_wake = nmk_gpio_irq_set_wake,
2ec1d359
AR		 673};
674
33b744b3
RV		 675static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
676 u32 status)
2ec1d359
AR		 677{
678 struct nmk_gpio_chip *nmk_chip;
aaedaa2b 679 struct irq_chip *host_chip = get_irq_chip(irq);
2ec1d359
AR		 680 unsigned int first_irq;
681
f272c00e
LB		 682 if (host_chip->irq_mask_ack)
683 host_chip->irq_mask_ack(&desc->irq_data);
aaedaa2b 684 else {
f272c00e
LB		 685 host_chip->irq_mask(&desc->irq_data);
686 if (host_chip->irq_ack)
687 host_chip->irq_ack(&desc->irq_data);
aaedaa2b
RV		 688 }
689
2ec1d359
AR		 690 nmk_chip = get_irq_data(irq);
691 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
33b744b3
RV		 692 while (status) {
693 int bit = __ffs(status);
694
695 generic_handle_irq(first_irq + bit);
696 status &= ~BIT(bit);
2ec1d359 697 }
aaedaa2b 698
f272c00e 699 host_chip->irq_unmask(&desc->irq_data);
2ec1d359
AR		 700}
701
33b744b3
RV		 702static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
703{
704 struct nmk_gpio_chip *nmk_chip = get_irq_data(irq);
705 u32 status = readl(nmk_chip->addr + NMK_GPIO_IS);
706
707 __nmk_gpio_irq_handler(irq, desc, status);
708}
709
710static void nmk_gpio_secondary_irq_handler(unsigned int irq,
711 struct irq_desc *desc)
712{
713 struct nmk_gpio_chip *nmk_chip = get_irq_data(irq);
714 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
715
716 __nmk_gpio_irq_handler(irq, desc, status);
717}
718
2ec1d359
AR		 719static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
720{
721 unsigned int first_irq;
722 int i;
723
724 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
e493e06f 725 for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) {
2ec1d359
AR		 726 set_irq_chip(i, &nmk_gpio_irq_chip);
727 set_irq_handler(i, handle_edge_irq);
728 set_irq_flags(i, IRQF_VALID);
729 set_irq_chip_data(i, nmk_chip);
2210d645 730 set_irq_type(i, IRQ_TYPE_EDGE_FALLING);
2ec1d359 731 }
33b744b3 732
2ec1d359
AR		 733 set_irq_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
734 set_irq_data(nmk_chip->parent_irq, nmk_chip);
33b744b3
RV		 735
736 if (nmk_chip->secondary_parent_irq >= 0) {
737 set_irq_chained_handler(nmk_chip->secondary_parent_irq,
738 nmk_gpio_secondary_irq_handler);
739 set_irq_data(nmk_chip->secondary_parent_irq, nmk_chip);
740 }
741
2ec1d359
AR		 742 return 0;
743}
744
745/* I/O Functions */
746static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
747{
748 struct nmk_gpio_chip *nmk_chip =
749 container_of(chip, struct nmk_gpio_chip, chip);
750
751 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
752 return 0;
753}
754
2ec1d359
AR		 755static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
756{
757 struct nmk_gpio_chip *nmk_chip =
758 container_of(chip, struct nmk_gpio_chip, chip);
759 u32 bit = 1 << offset;
760
761 return (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
762}
763
764static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
765 int val)
766{
767 struct nmk_gpio_chip *nmk_chip =
768 container_of(chip, struct nmk_gpio_chip, chip);
2ec1d359 769
6720db7c 770 __nmk_gpio_set_output(nmk_chip, offset, val);
2ec1d359
AR		 771}
772
6647c6c0
RV		 773static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
774 int val)
775{
776 struct nmk_gpio_chip *nmk_chip =
777 container_of(chip, struct nmk_gpio_chip, chip);
778
6720db7c 779 __nmk_gpio_make_output(nmk_chip, offset, val);
6647c6c0
RV		 780
781 return 0;
782}
783
0d2aec9c
RV		 784static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
785{
786 struct nmk_gpio_chip *nmk_chip =
787 container_of(chip, struct nmk_gpio_chip, chip);
788
789 return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset;
790}
791
d0b543c7
RV		 792#ifdef CONFIG_DEBUG_FS
793
794#include <linux/seq_file.h>
795
796static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
797{
798 int mode;
799 unsigned i;
800 unsigned gpio = chip->base;
801 int is_out;
802 struct nmk_gpio_chip *nmk_chip =
803 container_of(chip, struct nmk_gpio_chip, chip);
804 const char *modes[] = {
805 [NMK_GPIO_ALT_GPIO] = "gpio",
806 [NMK_GPIO_ALT_A] = "altA",
807 [NMK_GPIO_ALT_B] = "altB",
808 [NMK_GPIO_ALT_C] = "altC",
809 };
810
811 for (i = 0; i < chip->ngpio; i++, gpio++) {
812 const char *label = gpiochip_is_requested(chip, i);
813 bool pull;
814 u32 bit = 1 << i;
815
816 if (!label)
817 continue;
818
819 is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit;
820 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
821 mode = nmk_gpio_get_mode(gpio);
822 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
823 gpio, label,
824 is_out ? "out" : "in ",
825 chip->get
826 ? (chip->get(chip, i) ? "hi" : "lo")
827 : "? ",
828 (mode < 0) ? "unknown" : modes[mode],
829 pull ? "pull" : "none");
830
831 if (!is_out) {
832 int irq = gpio_to_irq(gpio);
833 struct irq_desc *desc = irq_to_desc(irq);
834
835 /* This races with request_irq(), set_irq_type(),
836 * and set_irq_wake() ... but those are "rare".
837 *
838 * More significantly, trigger type flags aren't
839 * currently maintained by genirq.
840 */
841 if (irq >= 0 && desc->action) {
842 char *trigger;
843
844 switch (desc->status & IRQ_TYPE_SENSE_MASK) {
845 case IRQ_TYPE_NONE:
846 trigger = "(default)";
847 break;
848 case IRQ_TYPE_EDGE_FALLING:
849 trigger = "edge-falling";
850 break;
851 case IRQ_TYPE_EDGE_RISING:
852 trigger = "edge-rising";
853 break;
854 case IRQ_TYPE_EDGE_BOTH:
855 trigger = "edge-both";
856 break;
857 case IRQ_TYPE_LEVEL_HIGH:
858 trigger = "level-high";
859 break;
860 case IRQ_TYPE_LEVEL_LOW:
861 trigger = "level-low";
862 break;
863 default:
864 trigger = "?trigger?";
865 break;
866 }
867
868 seq_printf(s, " irq-%d %s%s",
869 irq, trigger,
870 (desc->status & IRQ_WAKEUP)
871 ? " wakeup" : "");
872 }
873 }
874
875 seq_printf(s, "\n");
876 }
877}
878
879#else
880#define nmk_gpio_dbg_show NULL
881#endif
882
2ec1d359
AR		 883/* This structure is replicated for each GPIO block allocated at probe time */
884static struct gpio_chip nmk_gpio_template = {
885 .direction_input = nmk_gpio_make_input,
886 .get = nmk_gpio_get_input,
887 .direction_output = nmk_gpio_make_output,
888 .set = nmk_gpio_set_output,
0d2aec9c 889 .to_irq = nmk_gpio_to_irq,
d0b543c7 890 .dbg_show = nmk_gpio_dbg_show,
2ec1d359
AR		 891 .can_sleep = 0,
892};
893
fd0d67d6 894static int __devinit nmk_gpio_probe(struct platform_device *dev)
2ec1d359 895{
3e3c62ca 896 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
2ec1d359
AR		 897 struct nmk_gpio_chip *nmk_chip;
898 struct gpio_chip *chip;
3e3c62ca 899 struct resource *res;
af7dc228 900 struct clk *clk;
33b744b3 901 int secondary_irq;
3e3c62ca 902 int irq;
2ec1d359
AR		 903 int ret;
904
3e3c62ca
RV		 905 if (!pdata)
906 return -ENODEV;
907
908 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
909 if (!res) {
910 ret = -ENOENT;
911 goto out;
912 }
913
914 irq = platform_get_irq(dev, 0);
915 if (irq < 0) {
916 ret = irq;
917 goto out;
918 }
919
33b744b3
RV		 920 secondary_irq = platform_get_irq(dev, 1);
921 if (secondary_irq >= 0 && !pdata->get_secondary_status) {
922 ret = -EINVAL;
923 goto out;
924 }
925
3e3c62ca
RV		 926 if (request_mem_region(res->start, resource_size(res),
927 dev_name(&dev->dev)) == NULL) {
928 ret = -EBUSY;
929 goto out;
930 }
2ec1d359 931
af7dc228
RV		 932 clk = clk_get(&dev->dev, NULL);
933 if (IS_ERR(clk)) {
934 ret = PTR_ERR(clk);
935 goto out_release;
936 }
937
938 clk_enable(clk);
939
2ec1d359
AR		 940 nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL);
941 if (!nmk_chip) {
942 ret = -ENOMEM;
af7dc228 943 goto out_clk;
2ec1d359
AR		 944 }
945 /*
946 * The virt address in nmk_chip->addr is in the nomadik register space,
947 * so we can simply convert the resource address, without remapping
948 */
33b744b3 949 nmk_chip->bank = dev->id;
af7dc228 950 nmk_chip->clk = clk;
3e3c62ca 951 nmk_chip->addr = io_p2v(res->start);
2ec1d359 952 nmk_chip->chip = nmk_gpio_template;
3e3c62ca 953 nmk_chip->parent_irq = irq;
33b744b3
RV		 954 nmk_chip->secondary_parent_irq = secondary_irq;
955 nmk_chip->get_secondary_status = pdata->get_secondary_status;
01727e61 956 nmk_chip->set_ioforce = pdata->set_ioforce;
c0fcb8db 957 spin_lock_init(&nmk_chip->lock);
2ec1d359
AR		 958
959 chip = &nmk_chip->chip;
960 chip->base = pdata->first_gpio;
e493e06f 961 chip->ngpio = pdata->num_gpio;
8d568ae5 962 chip->label = pdata->name ?: dev_name(&dev->dev);
2ec1d359
AR		 963 chip->dev = &dev->dev;
964 chip->owner = THIS_MODULE;
965
966 ret = gpiochip_add(&nmk_chip->chip);
967 if (ret)
968 goto out_free;
969
01727e61
RV		 970 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
971
972 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
3e3c62ca 973 platform_set_drvdata(dev, nmk_chip);
2ec1d359
AR		 974
975 nmk_gpio_init_irq(nmk_chip);
976
977 dev_info(&dev->dev, "Bits %i-%i at address %p\n",
978 nmk_chip->chip.base, nmk_chip->chip.base+31, nmk_chip->addr);
979 return 0;
980
3e3c62ca 981out_free:
2ec1d359 982 kfree(nmk_chip);
af7dc228
RV		 983out_clk:
984 clk_disable(clk);
985 clk_put(clk);
3e3c62ca
RV		 986out_release:
987 release_mem_region(res->start, resource_size(res));
988out:
2ec1d359
AR		 989 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
990 pdata->first_gpio, pdata->first_gpio+31);
991 return ret;
992}
993
9c66ee6f 994#ifdef CONFIG_NOMADIK_GPIO_PM
c84c7c08
RV		 995static int nmk_gpio_pm(struct platform_device *dev, bool suspend)
996{
997 struct nmk_gpio_chip *nmk_chip = platform_get_drvdata(dev);
998 int i;
9c66ee6f
JA		 999 u32 dir;
1000 u32 dat;
c84c7c08 1001
9c66ee6f 1002 for (i = 0; i < ARRAY_SIZE(backup_regs); i++) {
c84c7c08 1003 if (suspend)
9c66ee6f
JA		 1004 nmk_chip->backup[i] = readl(nmk_chip->addr +
1005 backup_regs[i]);
c84c7c08 1006 else
9c66ee6f
JA		 1007 writel(nmk_chip->backup[i],
1008 nmk_chip->addr + backup_regs[i]);
c84c7c08
RV		 1009 }
1010
9c66ee6f
JA		 1011 if (!suspend) {
1012 /*
1013 * Restore pull-up and pull-down on inputs and
1014 * outputs.
1015 */
1016 dir = readl(nmk_chip->addr + NMK_GPIO_DIR);
1017 dat = readl(nmk_chip->addr + NMK_GPIO_DAT);
1018
1019 writel((nmk_chip->pull & ~dir) |
1020 (dat & dir),
1021 nmk_chip->addr + NMK_GPIO_DATS);
1022
1023 writel((~nmk_chip->pull & ~dir) |
1024 (~dat & dir),
1025 nmk_chip->addr + NMK_GPIO_DATC);
1026 }
c84c7c08
RV		 1027 return 0;
1028}
1029
1030static int nmk_gpio_suspend(struct platform_device *dev, pm_message_t state)
1031{
1032 return nmk_gpio_pm(dev, true);
1033}
1034
1035static int nmk_gpio_resume(struct platform_device *dev)
1036{
1037 return nmk_gpio_pm(dev, false);
1038}
1039#else
1040#define nmk_gpio_suspend NULL
1041#define nmk_gpio_resume NULL
1042#endif
1043
3e3c62ca
RV		 1044static struct platform_driver nmk_gpio_driver = {
1045 .driver = {
2ec1d359
AR		 1046 .owner = THIS_MODULE,
1047 .name = "gpio",
1048 },
1049 .probe = nmk_gpio_probe,
c84c7c08
RV		 1050 .suspend = nmk_gpio_suspend,
1051 .resume = nmk_gpio_resume,
2ec1d359
AR		 1052};
1053
1054static int __init nmk_gpio_init(void)
1055{
3e3c62ca 1056 return platform_driver_register(&nmk_gpio_driver);
2ec1d359
AR		 1057}
1058
33f45ea9 1059core_initcall(nmk_gpio_init);
2ec1d359
AR		 1060
1061MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1062MODULE_DESCRIPTION("Nomadik GPIO Driver");
1063MODULE_LICENSE("GPL");
1064
1065
Linux kernel - Deliverables
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