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28ad94ec AR |
1 | /* |
2 | * linux/arch/arm/mach-nomadik/timer.c | |
3 | * | |
4 | * Copyright (C) 2008 STMicroelectronics | |
b102c01f | 5 | * Copyright (C) 2010 Alessandro Rubini |
28ad94ec AR |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2, as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/irq.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/clockchips.h> | |
16 | #include <linux/jiffies.h> | |
17 | #include <asm/mach/time.h> | |
28ad94ec | 18 | |
59b559d7 | 19 | #include <plat/mtu.h> |
28ad94ec | 20 | |
b102c01f | 21 | void __iomem *mtu_base; /* ssigned by machine code */ |
59b559d7 | 22 | |
b102c01f | 23 | /* clocksource: MTU decrements, so we negate the value being read. */ |
28ad94ec AR |
24 | static cycle_t nmdk_read_timer(struct clocksource *cs) |
25 | { | |
b102c01f | 26 | return -readl(mtu_base + MTU_VAL(0)); |
28ad94ec AR |
27 | } |
28 | ||
29 | static struct clocksource nmdk_clksrc = { | |
30 | .name = "mtu_0", | |
b102c01f | 31 | .rating = 200, |
28ad94ec | 32 | .read = nmdk_read_timer, |
b102c01f | 33 | .mask = CLOCKSOURCE_MASK(32), |
28ad94ec AR |
34 | .shift = 20, |
35 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
36 | }; | |
37 | ||
b102c01f | 38 | /* Clockevent device: use one-shot mode */ |
28ad94ec AR |
39 | static void nmdk_clkevt_mode(enum clock_event_mode mode, |
40 | struct clock_event_device *dev) | |
41 | { | |
b102c01f AR |
42 | u32 cr; |
43 | ||
28ad94ec AR |
44 | switch (mode) { |
45 | case CLOCK_EVT_MODE_PERIODIC: | |
b102c01f | 46 | pr_err("%s: periodic mode not supported\n", __func__); |
28ad94ec AR |
47 | break; |
48 | case CLOCK_EVT_MODE_ONESHOT: | |
b102c01f AR |
49 | /* Load highest value, enable device, enable interrupts */ |
50 | cr = readl(mtu_base + MTU_CR(1)); | |
51 | writel(0, mtu_base + MTU_LR(1)); | |
52 | writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(1)); | |
53 | writel(0x2, mtu_base + MTU_IMSC); | |
54 | break; | |
28ad94ec AR |
55 | case CLOCK_EVT_MODE_SHUTDOWN: |
56 | case CLOCK_EVT_MODE_UNUSED: | |
b102c01f AR |
57 | /* disable irq */ |
58 | writel(0, mtu_base + MTU_IMSC); | |
28ad94ec AR |
59 | break; |
60 | case CLOCK_EVT_MODE_RESUME: | |
61 | break; | |
62 | } | |
63 | } | |
64 | ||
b102c01f AR |
65 | static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev) |
66 | { | |
67 | /* writing the value has immediate effect */ | |
68 | writel(evt, mtu_base + MTU_LR(1)); | |
69 | return 0; | |
70 | } | |
71 | ||
28ad94ec | 72 | static struct clock_event_device nmdk_clkevt = { |
b102c01f AR |
73 | .name = "mtu_1", |
74 | .features = CLOCK_EVT_FEAT_ONESHOT, | |
28ad94ec | 75 | .shift = 32, |
b102c01f | 76 | .rating = 200, |
28ad94ec | 77 | .set_mode = nmdk_clkevt_mode, |
b102c01f | 78 | .set_next_event = nmdk_clkevt_next, |
28ad94ec AR |
79 | }; |
80 | ||
81 | /* | |
b102c01f | 82 | * IRQ Handler for timer 1 of the MTU block. |
28ad94ec AR |
83 | */ |
84 | static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id) | |
85 | { | |
b102c01f | 86 | struct clock_event_device *evdev = dev_id; |
28ad94ec | 87 | |
b102c01f AR |
88 | writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */ |
89 | evdev->event_handler(evdev); | |
28ad94ec AR |
90 | return IRQ_HANDLED; |
91 | } | |
92 | ||
28ad94ec AR |
93 | static struct irqaction nmdk_timer_irq = { |
94 | .name = "Nomadik Timer Tick", | |
95 | .flags = IRQF_DISABLED | IRQF_TIMER, | |
96 | .handler = nmdk_timer_interrupt, | |
b102c01f | 97 | .dev_id = &nmdk_clkevt, |
28ad94ec AR |
98 | }; |
99 | ||
59b559d7 | 100 | void __init nmdk_timer_init(void) |
28ad94ec | 101 | { |
28ad94ec | 102 | unsigned long rate; |
b102c01f AR |
103 | u32 cr = MTU_CRn_32BITS;; |
104 | ||
105 | /* | |
106 | * Tick rate is 2.4MHz for Nomadik and 110MHz for ux500: | |
107 | * use a divide-by-16 counter if it's more than 16MHz | |
108 | */ | |
109 | rate = CLOCK_TICK_RATE; | |
110 | if (rate > 16 << 20) { | |
111 | rate /= 16; | |
112 | cr |= MTU_CRn_PRESCALE_16; | |
113 | } else { | |
114 | cr |= MTU_CRn_PRESCALE_1; | |
115 | } | |
28ad94ec | 116 | |
b102c01f AR |
117 | /* Timer 0 is the free running clocksource */ |
118 | writel(cr, mtu_base + MTU_CR(0)); | |
119 | writel(0, mtu_base + MTU_LR(0)); | |
120 | writel(0, mtu_base + MTU_BGLR(0)); | |
121 | writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0)); | |
28ad94ec AR |
122 | |
123 | nmdk_clksrc.mult = clocksource_hz2mult(rate, nmdk_clksrc.shift); | |
28ad94ec | 124 | |
59b559d7 | 125 | if (clocksource_register(&nmdk_clksrc)) |
b102c01f AR |
126 | pr_err("timer: failed to initialize clock source %s\n", |
127 | nmdk_clksrc.name); | |
128 | ||
129 | /* Timer 1 is used for events, fix according to rate */ | |
130 | writel(cr | MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */ | |
131 | nmdk_clkevt.mult = div_sc(rate, NSEC_PER_SEC, nmdk_clkevt.shift); | |
132 | nmdk_clkevt.max_delta_ns = | |
133 | clockevent_delta2ns(0xffffffff, &nmdk_clkevt); | |
134 | nmdk_clkevt.min_delta_ns = | |
135 | clockevent_delta2ns(0x00000002, &nmdk_clkevt); | |
136 | nmdk_clkevt.cpumask = cpumask_of(0); | |
28ad94ec AR |
137 | |
138 | /* Register irq and clockevents */ | |
139 | setup_irq(IRQ_MTU0, &nmdk_timer_irq); | |
28ad94ec AR |
140 | clockevents_register_device(&nmdk_clkevt); |
141 | } |