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OMAP: Remove OMAP_IO_ADDRESS, use OMAP1_IO_ADDRESS and OMAP2_IO_ADDRESS instead
[deliverable/linux.git] / arch / arm / plat-omap / dma.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/dma.c
3 *
97b7f715 4 * Copyright (C) 2003 - 2008 Nokia Corporation
96de0e25 5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4
TL		 6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
f8151e5c 9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
1a8bfa1e 10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
5e1c5ff4
TL		 11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 *
44169075
SS		 13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 *
5e1c5ff4
TL		 16 * Support functions for the OMAP internal DMA channels.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/sched.h>
27#include <linux/spinlock.h>
28#include <linux/errno.h>
29#include <linux/interrupt.h>
418ca1f0 30#include <linux/irq.h>
97b7f715 31#include <linux/io.h>
5e1c5ff4
TL		 32
33#include <asm/system.h>
a09e64fb 34#include <mach/hardware.h>
dcea83ad 35#include <mach/dma.h>
5e1c5ff4 36
a09e64fb 37#include <mach/tc.h>
5e1c5ff4 38
f8151e5c
AG		 39#undef DEBUG
40
41#ifndef CONFIG_ARCH_OMAP1
42enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
43 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
44};
45
46enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
1a8bfa1e 47#endif
5e1c5ff4 48
97b7f715
TL		 49#define OMAP_DMA_ACTIVE 0x01
50#define OMAP_DMA_CCR_EN (1 << 7)
7ff879db 51#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
5e1c5ff4 52
97b7f715 53#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
5e1c5ff4 54
97b7f715 55static int enable_1510_mode;
5e1c5ff4
TL		 56
57struct omap_dma_lch {
58 int next_lch;
59 int dev_id;
60 u16 saved_csr;
61 u16 enabled_irqs;
62 const char *dev_name;
97b7f715 63 void (*callback)(int lch, u16 ch_status, void *data);
5e1c5ff4 64 void *data;
f8151e5c
AG		 65
66#ifndef CONFIG_ARCH_OMAP1
67 /* required for Dynamic chaining */
68 int prev_linked_ch;
69 int next_linked_ch;
70 int state;
71 int chain_id;
72
73 int status;
74#endif
5e1c5ff4
TL		 75 long flags;
76};
77
f8151e5c
AG		 78struct dma_link_info {
79 int *linked_dmach_q;
80 int no_of_lchs_linked;
81
82 int q_count;
83 int q_tail;
84 int q_head;
85
86 int chain_state;
87 int chain_mode;
88
89};
90
4d96372e
TL		 91static struct dma_link_info *dma_linked_lch;
92
93#ifndef CONFIG_ARCH_OMAP1
f8151e5c
AG		 94
95/* Chain handling macros */
96#define OMAP_DMA_CHAIN_QINIT(chain_id) \
97 do { \
98 dma_linked_lch[chain_id].q_head = \
99 dma_linked_lch[chain_id].q_tail = \
100 dma_linked_lch[chain_id].q_count = 0; \
101 } while (0)
102#define OMAP_DMA_CHAIN_QFULL(chain_id) \
103 (dma_linked_lch[chain_id].no_of_lchs_linked == \
104 dma_linked_lch[chain_id].q_count)
105#define OMAP_DMA_CHAIN_QLAST(chain_id) \
106 do { \
107 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
108 dma_linked_lch[chain_id].q_count) \
109 } while (0)
110#define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
111 (0 == dma_linked_lch[chain_id].q_count)
112#define __OMAP_DMA_CHAIN_INCQ(end) \
113 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
114#define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
115 do { \
116 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
117 dma_linked_lch[chain_id].q_count--; \
118 } while (0)
119
120#define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
121 do { \
122 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
123 dma_linked_lch[chain_id].q_count++; \
124 } while (0)
125#endif
4d96372e
TL		 126
127static int dma_lch_count;
5e1c5ff4 128static int dma_chan_count;
2263f022 129static int omap_dma_reserve_channels;
5e1c5ff4
TL		 130
131static spinlock_t dma_chan_lock;
4d96372e 132static struct omap_dma_lch *dma_chan;
0499bdeb 133static void __iomem *omap_dma_base;
5e1c5ff4 134
4d96372e 135static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
5e1c5ff4
TL		 136 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
137 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
138 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
139 INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
140 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
141};
142
f8151e5c
AG		 143static inline void disable_lnk(int lch);
144static void omap_disable_channel_irq(int lch);
145static inline void omap_enable_channel_irq(int lch);
146
1a8bfa1e 147#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
8e86f427 148 __func__);
1a8bfa1e 149
0499bdeb
TL		 150#define dma_read(reg) \
151({ \
152 u32 __val; \
153 if (cpu_class_is_omap1()) \
154 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg); \
155 else \
156 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg); \
157 __val; \
158})
159
160#define dma_write(val, reg) \
161({ \
162 if (cpu_class_is_omap1()) \
163 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
164 else \
165 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \
166})
167
1a8bfa1e
TL		 168#ifdef CONFIG_ARCH_OMAP15XX
169/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
170int omap_dma_in_1510_mode(void)
171{
172 return enable_1510_mode;
173}
174#else
175#define omap_dma_in_1510_mode() 0
176#endif
177
178#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 179static inline int get_gdma_dev(int req)
180{
181 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
182 int shift = ((req - 1) % 5) * 6;
183
184 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
185}
186
187static inline void set_gdma_dev(int req, int dev)
188{
189 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
190 int shift = ((req - 1) % 5) * 6;
191 u32 l;
192
193 l = omap_readl(reg);
194 l &= ~(0x3f << shift);
195 l |= (dev - 1) << shift;
196 omap_writel(l, reg);
197}
1a8bfa1e
TL		 198#else
199#define set_gdma_dev(req, dev) do {} while (0)
200#endif
5e1c5ff4 201
0499bdeb 202/* Omap1 only */
5e1c5ff4
TL		 203static void clear_lch_regs(int lch)
204{
205 int i;
0499bdeb 206 void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
5e1c5ff4
TL		 207
208 for (i = 0; i < 0x2c; i += 2)
0499bdeb 209 __raw_writew(0, lch_base + i);
5e1c5ff4
TL		 210}
211
709eb3e5 212void omap_set_dma_priority(int lch, int dst_port, int priority)
5e1c5ff4
TL		 213{
214 unsigned long reg;
215 u32 l;
216
709eb3e5
TL		 217 if (cpu_class_is_omap1()) {
218 switch (dst_port) {
219 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
220 reg = OMAP_TC_OCPT1_PRIOR;
221 break;
222 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
223 reg = OMAP_TC_OCPT2_PRIOR;
224 break;
225 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
226 reg = OMAP_TC_EMIFF_PRIOR;
227 break;
228 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
229 reg = OMAP_TC_EMIFS_PRIOR;
230 break;
231 default:
232 BUG();
233 return;
234 }
235 l = omap_readl(reg);
236 l &= ~(0xf << 8);
237 l |= (priority & 0xf) << 8;
238 omap_writel(l, reg);
239 }
240
f8151e5c 241 if (cpu_class_is_omap2()) {
0499bdeb
TL		 242 u32 ccr;
243
244 ccr = dma_read(CCR(lch));
709eb3e5 245 if (priority)
0499bdeb 246 ccr |= (1 << 6);
709eb3e5 247 else
0499bdeb
TL		 248 ccr &= ~(1 << 6);
249 dma_write(ccr, CCR(lch));
5e1c5ff4 250 }
5e1c5ff4 251}
97b7f715 252EXPORT_SYMBOL(omap_set_dma_priority);
5e1c5ff4
TL		 253
254void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
1a8bfa1e
TL		 255 int frame_count, int sync_mode,
256 int dma_trigger, int src_or_dst_synch)
5e1c5ff4 257{
0499bdeb
TL		 258 u32 l;
259
260 l = dma_read(CSDP(lch));
261 l &= ~0x03;
262 l |= data_type;
263 dma_write(l, CSDP(lch));
5e1c5ff4 264
1a8bfa1e 265 if (cpu_class_is_omap1()) {
0499bdeb
TL		 266 u16 ccr;
267
268 ccr = dma_read(CCR(lch));
269 ccr &= ~(1 << 5);
1a8bfa1e 270 if (sync_mode == OMAP_DMA_SYNC_FRAME)
0499bdeb
TL		 271 ccr |= 1 << 5;
272 dma_write(ccr, CCR(lch));
1a8bfa1e 273
0499bdeb
TL		 274 ccr = dma_read(CCR2(lch));
275 ccr &= ~(1 << 2);
1a8bfa1e 276 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
0499bdeb
TL		 277 ccr |= 1 << 2;
278 dma_write(ccr, CCR2(lch));
1a8bfa1e
TL		 279 }
280
f8151e5c 281 if (cpu_class_is_omap2() && dma_trigger) {
0499bdeb 282 u32 val;
1a8bfa1e 283
0499bdeb 284 val = dma_read(CCR(lch));
4b3cf448
AG		 285
286 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
287 val &= ~((3 << 19) | 0x1f);
288 val |= (dma_trigger & ~0x1f) << 14;
289 val |= dma_trigger & 0x1f;
5e1c5ff4 290
1a8bfa1e
TL		 291 if (sync_mode & OMAP_DMA_SYNC_FRAME)
292 val |= 1 << 5;
eca9e56e
PU		 293 else
294 val &= ~(1 << 5);
5e1c5ff4 295
1a8bfa1e
TL		 296 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
297 val |= 1 << 18;
eca9e56e
PU		 298 else
299 val &= ~(1 << 18);
5e1c5ff4 300
1a8bfa1e
TL		 301 if (src_or_dst_synch)
302 val |= 1 << 24; /* source synch */
303 else
304 val &= ~(1 << 24); /* dest synch */
305
0499bdeb 306 dma_write(val, CCR(lch));
1a8bfa1e
TL		 307 }
308
0499bdeb
TL		 309 dma_write(elem_count, CEN(lch));
310 dma_write(frame_count, CFN(lch));
5e1c5ff4 311}
97b7f715 312EXPORT_SYMBOL(omap_set_dma_transfer_params);
1a8bfa1e 313
5e1c5ff4
TL		 314void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
315{
5e1c5ff4
TL		 316 BUG_ON(omap_dma_in_1510_mode());
317
0815f8ea
TV		 318 if (cpu_class_is_omap1()) {
319 u16 w;
1a8bfa1e 320
0815f8ea
TV		 321 w = dma_read(CCR2(lch));
322 w &= ~0x03;
323
324 switch (mode) {
325 case OMAP_DMA_CONSTANT_FILL:
326 w |= 0x01;
327 break;
328 case OMAP_DMA_TRANSPARENT_COPY:
329 w |= 0x02;
330 break;
331 case OMAP_DMA_COLOR_DIS:
332 break;
333 default:
334 BUG();
335 }
336 dma_write(w, CCR2(lch));
337
338 w = dma_read(LCH_CTRL(lch));
339 w &= ~0x0f;
340 /* Default is channel type 2D */
341 if (mode) {
342 dma_write((u16)color, COLOR_L(lch));
343 dma_write((u16)(color >> 16), COLOR_U(lch));
344 w |= 1; /* Channel type G */
345 }
346 dma_write(w, LCH_CTRL(lch));
5e1c5ff4 347 }
0815f8ea
TV		 348
349 if (cpu_class_is_omap2()) {
350 u32 val;
351
352 val = dma_read(CCR(lch));
353 val &= ~((1 << 17) | (1 << 16));
354
355 switch (mode) {
356 case OMAP_DMA_CONSTANT_FILL:
357 val |= 1 << 16;
358 break;
359 case OMAP_DMA_TRANSPARENT_COPY:
360 val |= 1 << 17;
361 break;
362 case OMAP_DMA_COLOR_DIS:
363 break;
364 default:
365 BUG();
366 }
367 dma_write(val, CCR(lch));
368
369 color &= 0xffffff;
370 dma_write(color, COLOR(lch));
5e1c5ff4 371 }
5e1c5ff4 372}
97b7f715 373EXPORT_SYMBOL(omap_set_dma_color_mode);
5e1c5ff4 374
709eb3e5
TL		 375void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
376{
f8151e5c 377 if (cpu_class_is_omap2()) {
0499bdeb
TL		 378 u32 csdp;
379
380 csdp = dma_read(CSDP(lch));
381 csdp &= ~(0x3 << 16);
382 csdp |= (mode << 16);
383 dma_write(csdp, CSDP(lch));
709eb3e5
TL		 384 }
385}
97b7f715 386EXPORT_SYMBOL(omap_set_dma_write_mode);
709eb3e5 387
0499bdeb
TL		 388void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
389{
390 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
391 u32 l;
392
393 l = dma_read(LCH_CTRL(lch));
394 l &= ~0x7;
395 l |= mode;
396 dma_write(l, LCH_CTRL(lch));
397 }
398}
399EXPORT_SYMBOL(omap_set_dma_channel_mode);
400
1a8bfa1e 401/* Note that src_port is only for omap1 */
5e1c5ff4 402void omap_set_dma_src_params(int lch, int src_port, int src_amode,
1a8bfa1e
TL		 403 unsigned long src_start,
404 int src_ei, int src_fi)
5e1c5ff4 405{
97b7f715
TL		 406 u32 l;
407
1a8bfa1e 408 if (cpu_class_is_omap1()) {
0499bdeb 409 u16 w;
1a8bfa1e 410
0499bdeb
TL		 411 w = dma_read(CSDP(lch));
412 w &= ~(0x1f << 2);
413 w |= src_port << 2;
414 dma_write(w, CSDP(lch));
97b7f715 415 }
1a8bfa1e 416
97b7f715
TL		 417 l = dma_read(CCR(lch));
418 l &= ~(0x03 << 12);
419 l |= src_amode << 12;
420 dma_write(l, CCR(lch));
0499bdeb 421
97b7f715 422 if (cpu_class_is_omap1()) {
0499bdeb
TL		 423 dma_write(src_start >> 16, CSSA_U(lch));
424 dma_write((u16)src_start, CSSA_L(lch));
1a8bfa1e 425 }
5e1c5ff4 426
97b7f715 427 if (cpu_class_is_omap2())
0499bdeb 428 dma_write(src_start, CSSA(lch));
97b7f715
TL		 429
430 dma_write(src_ei, CSEI(lch));
431 dma_write(src_fi, CSFI(lch));
1a8bfa1e 432}
97b7f715 433EXPORT_SYMBOL(omap_set_dma_src_params);
5e1c5ff4 434
97b7f715 435void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
1a8bfa1e
TL		 436{
437 omap_set_dma_transfer_params(lch, params->data_type,
438 params->elem_count, params->frame_count,
439 params->sync_mode, params->trigger,
440 params->src_or_dst_synch);
441 omap_set_dma_src_params(lch, params->src_port,
442 params->src_amode, params->src_start,
443 params->src_ei, params->src_fi);
444
445 omap_set_dma_dest_params(lch, params->dst_port,
446 params->dst_amode, params->dst_start,
447 params->dst_ei, params->dst_fi);
f8151e5c
AG		 448 if (params->read_prio || params->write_prio)
449 omap_dma_set_prio_lch(lch, params->read_prio,
450 params->write_prio);
5e1c5ff4 451}
97b7f715 452EXPORT_SYMBOL(omap_set_dma_params);
5e1c5ff4
TL		 453
454void omap_set_dma_src_index(int lch, int eidx, int fidx)
455{
97b7f715 456 if (cpu_class_is_omap2())
1a8bfa1e 457 return;
97b7f715 458
0499bdeb
TL		 459 dma_write(eidx, CSEI(lch));
460 dma_write(fidx, CSFI(lch));
5e1c5ff4 461}
97b7f715 462EXPORT_SYMBOL(omap_set_dma_src_index);
5e1c5ff4
TL		 463
464void omap_set_dma_src_data_pack(int lch, int enable)
465{
0499bdeb
TL		 466 u32 l;
467
468 l = dma_read(CSDP(lch));
469 l &= ~(1 << 6);
1a8bfa1e 470 if (enable)
0499bdeb
TL		 471 l |= (1 << 6);
472 dma_write(l, CSDP(lch));
5e1c5ff4 473}
97b7f715 474EXPORT_SYMBOL(omap_set_dma_src_data_pack);
5e1c5ff4
TL		 475
476void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
477{
6dc3c8f2 478 unsigned int burst = 0;
0499bdeb
TL		 479 u32 l;
480
481 l = dma_read(CSDP(lch));
482 l &= ~(0x03 << 7);
5e1c5ff4 483
5e1c5ff4
TL		 484 switch (burst_mode) {
485 case OMAP_DMA_DATA_BURST_DIS:
486 break;
487 case OMAP_DMA_DATA_BURST_4:
f8151e5c 488 if (cpu_class_is_omap2())
6dc3c8f2
KP		 489 burst = 0x1;
490 else
491 burst = 0x2;
5e1c5ff4
TL		 492 break;
493 case OMAP_DMA_DATA_BURST_8:
f8151e5c 494 if (cpu_class_is_omap2()) {
6dc3c8f2
KP		 495 burst = 0x2;
496 break;
497 }
498 /* not supported by current hardware on OMAP1
5e1c5ff4
TL		 499 * w |= (0x03 << 7);
500 * fall through
501 */
6dc3c8f2 502 case OMAP_DMA_DATA_BURST_16:
f8151e5c 503 if (cpu_class_is_omap2()) {
6dc3c8f2
KP		 504 burst = 0x3;
505 break;
506 }
507 /* OMAP1 don't support burst 16
508 * fall through
509 */
5e1c5ff4
TL		 510 default:
511 BUG();
512 }
0499bdeb
TL		 513
514 l |= (burst << 7);
515 dma_write(l, CSDP(lch));
5e1c5ff4 516}
97b7f715 517EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
5e1c5ff4 518
1a8bfa1e 519/* Note that dest_port is only for OMAP1 */
5e1c5ff4 520void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
1a8bfa1e
TL		 521 unsigned long dest_start,
522 int dst_ei, int dst_fi)
5e1c5ff4 523{
0499bdeb
TL		 524 u32 l;
525
1a8bfa1e 526 if (cpu_class_is_omap1()) {
0499bdeb
TL		 527 l = dma_read(CSDP(lch));
528 l &= ~(0x1f << 9);
529 l |= dest_port << 9;
530 dma_write(l, CSDP(lch));
1a8bfa1e 531 }
5e1c5ff4 532
0499bdeb
TL		 533 l = dma_read(CCR(lch));
534 l &= ~(0x03 << 14);
535 l |= dest_amode << 14;
536 dma_write(l, CCR(lch));
1a8bfa1e
TL		 537
538 if (cpu_class_is_omap1()) {
0499bdeb
TL		 539 dma_write(dest_start >> 16, CDSA_U(lch));
540 dma_write(dest_start, CDSA_L(lch));
1a8bfa1e 541 }
5e1c5ff4 542
f8151e5c 543 if (cpu_class_is_omap2())
0499bdeb 544 dma_write(dest_start, CDSA(lch));
5e1c5ff4 545
0499bdeb
TL		 546 dma_write(dst_ei, CDEI(lch));
547 dma_write(dst_fi, CDFI(lch));
5e1c5ff4 548}
97b7f715 549EXPORT_SYMBOL(omap_set_dma_dest_params);
5e1c5ff4
TL		 550
551void omap_set_dma_dest_index(int lch, int eidx, int fidx)
552{
97b7f715 553 if (cpu_class_is_omap2())
1a8bfa1e 554 return;
97b7f715 555
0499bdeb
TL		 556 dma_write(eidx, CDEI(lch));
557 dma_write(fidx, CDFI(lch));
5e1c5ff4 558}
97b7f715 559EXPORT_SYMBOL(omap_set_dma_dest_index);
5e1c5ff4
TL		 560
561void omap_set_dma_dest_data_pack(int lch, int enable)
562{
0499bdeb
TL		 563 u32 l;
564
565 l = dma_read(CSDP(lch));
566 l &= ~(1 << 13);
1a8bfa1e 567 if (enable)
0499bdeb
TL		 568 l |= 1 << 13;
569 dma_write(l, CSDP(lch));
5e1c5ff4 570}
97b7f715 571EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
5e1c5ff4
TL		 572
573void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
574{
6dc3c8f2 575 unsigned int burst = 0;
0499bdeb
TL		 576 u32 l;
577
578 l = dma_read(CSDP(lch));
579 l &= ~(0x03 << 14);
5e1c5ff4 580
5e1c5ff4
TL		 581 switch (burst_mode) {
582 case OMAP_DMA_DATA_BURST_DIS:
583 break;
584 case OMAP_DMA_DATA_BURST_4:
f8151e5c 585 if (cpu_class_is_omap2())
6dc3c8f2
KP		 586 burst = 0x1;
587 else
588 burst = 0x2;
5e1c5ff4
TL		 589 break;
590 case OMAP_DMA_DATA_BURST_8:
f8151e5c 591 if (cpu_class_is_omap2())
6dc3c8f2
KP		 592 burst = 0x2;
593 else
594 burst = 0x3;
5e1c5ff4 595 break;
6dc3c8f2 596 case OMAP_DMA_DATA_BURST_16:
f8151e5c 597 if (cpu_class_is_omap2()) {
6dc3c8f2
KP		 598 burst = 0x3;
599 break;
600 }
601 /* OMAP1 don't support burst 16
602 * fall through
603 */
5e1c5ff4
TL		 604 default:
605 printk(KERN_ERR "Invalid DMA burst mode\n");
606 BUG();
607 return;
608 }
0499bdeb
TL		 609 l |= (burst << 14);
610 dma_write(l, CSDP(lch));
5e1c5ff4 611}
97b7f715 612EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
5e1c5ff4 613
1a8bfa1e 614static inline void omap_enable_channel_irq(int lch)
5e1c5ff4 615{
1a8bfa1e 616 u32 status;
5e1c5ff4 617
7ff879db
TL		 618 /* Clear CSR */
619 if (cpu_class_is_omap1())
0499bdeb 620 status = dma_read(CSR(lch));
f8151e5c 621 else if (cpu_class_is_omap2())
0499bdeb 622 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
1a8bfa1e 623
5e1c5ff4 624 /* Enable some nice interrupts. */
0499bdeb 625 dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
5e1c5ff4
TL		 626}
627
1a8bfa1e 628static void omap_disable_channel_irq(int lch)
5e1c5ff4 629{
f8151e5c 630 if (cpu_class_is_omap2())
0499bdeb 631 dma_write(0, CICR(lch));
1a8bfa1e
TL		 632}
633
634void omap_enable_dma_irq(int lch, u16 bits)
635{
636 dma_chan[lch].enabled_irqs |= bits;
637}
97b7f715 638EXPORT_SYMBOL(omap_enable_dma_irq);
5e1c5ff4 639
1a8bfa1e
TL		 640void omap_disable_dma_irq(int lch, u16 bits)
641{
642 dma_chan[lch].enabled_irqs &= ~bits;
643}
97b7f715 644EXPORT_SYMBOL(omap_disable_dma_irq);
1a8bfa1e
TL		 645
646static inline void enable_lnk(int lch)
647{
0499bdeb
TL		 648 u32 l;
649
650 l = dma_read(CLNK_CTRL(lch));
651
1a8bfa1e 652 if (cpu_class_is_omap1())
0499bdeb 653 l &= ~(1 << 14);
5e1c5ff4 654
1a8bfa1e 655 /* Set the ENABLE_LNK bits */
5e1c5ff4 656 if (dma_chan[lch].next_lch != -1)
0499bdeb 657 l = dma_chan[lch].next_lch | (1 << 15);
f8151e5c
AG		 658
659#ifndef CONFIG_ARCH_OMAP1
97b7f715
TL		 660 if (cpu_class_is_omap2())
661 if (dma_chan[lch].next_linked_ch != -1)
662 l = dma_chan[lch].next_linked_ch | (1 << 15);
f8151e5c 663#endif
0499bdeb
TL		 664
665 dma_write(l, CLNK_CTRL(lch));
5e1c5ff4
TL		 666}
667
668static inline void disable_lnk(int lch)
669{
0499bdeb
TL		 670 u32 l;
671
672 l = dma_read(CLNK_CTRL(lch));
673
5e1c5ff4 674 /* Disable interrupts */
1a8bfa1e 675 if (cpu_class_is_omap1()) {
0499bdeb 676 dma_write(0, CICR(lch));
1a8bfa1e 677 /* Set the STOP_LNK bit */
0499bdeb 678 l |= 1 << 14;
1a8bfa1e 679 }
5e1c5ff4 680
f8151e5c 681 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 682 omap_disable_channel_irq(lch);
683 /* Clear the ENABLE_LNK bit */
0499bdeb 684 l &= ~(1 << 15);
1a8bfa1e 685 }
5e1c5ff4 686
0499bdeb 687 dma_write(l, CLNK_CTRL(lch));
5e1c5ff4
TL		 688 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
689}
690
1a8bfa1e 691static inline void omap2_enable_irq_lch(int lch)
5e1c5ff4 692{
1a8bfa1e
TL		 693 u32 val;
694
f8151e5c 695 if (!cpu_class_is_omap2())
1a8bfa1e
TL		 696 return;
697
0499bdeb 698 val = dma_read(IRQENABLE_L0);
1a8bfa1e 699 val |= 1 << lch;
0499bdeb 700 dma_write(val, IRQENABLE_L0);
1a8bfa1e
TL		 701}
702
703int omap_request_dma(int dev_id, const char *dev_name,
97b7f715 704 void (*callback)(int lch, u16 ch_status, void *data),
1a8bfa1e
TL		 705 void *data, int *dma_ch_out)
706{
707 int ch, free_ch = -1;
708 unsigned long flags;
709 struct omap_dma_lch *chan;
710
711 spin_lock_irqsave(&dma_chan_lock, flags);
712 for (ch = 0; ch < dma_chan_count; ch++) {
713 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
714 free_ch = ch;
715 if (dev_id == 0)
716 break;
717 }
718 }
719 if (free_ch == -1) {
720 spin_unlock_irqrestore(&dma_chan_lock, flags);
721 return -EBUSY;
722 }
723 chan = dma_chan + free_ch;
724 chan->dev_id = dev_id;
725
726 if (cpu_class_is_omap1())
727 clear_lch_regs(free_ch);
5e1c5ff4 728
f8151e5c 729 if (cpu_class_is_omap2())
1a8bfa1e
TL		 730 omap_clear_dma(free_ch);
731
732 spin_unlock_irqrestore(&dma_chan_lock, flags);
733
734 chan->dev_name = dev_name;
735 chan->callback = callback;
736 chan->data = data;
a92fda19 737 chan->flags = 0;
97b7f715 738
f8151e5c 739#ifndef CONFIG_ARCH_OMAP1
97b7f715
TL		 740 if (cpu_class_is_omap2()) {
741 chan->chain_id = -1;
742 chan->next_linked_ch = -1;
743 }
f8151e5c 744#endif
97b7f715 745
7ff879db 746 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
1a8bfa1e 747
7ff879db
TL		 748 if (cpu_class_is_omap1())
749 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
f8151e5c 750 else if (cpu_class_is_omap2())
7ff879db
TL		 751 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
752 OMAP2_DMA_TRANS_ERR_IRQ;
1a8bfa1e
TL		 753
754 if (cpu_is_omap16xx()) {
755 /* If the sync device is set, configure it dynamically. */
756 if (dev_id != 0) {
757 set_gdma_dev(free_ch + 1, dev_id);
758 dev_id = free_ch + 1;
759 }
97b7f715
TL		 760 /*
761 * Disable the 1510 compatibility mode and set the sync device
762 * id.
763 */
0499bdeb 764 dma_write(dev_id | (1 << 10), CCR(free_ch));
557096fe 765 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
0499bdeb 766 dma_write(dev_id, CCR(free_ch));
1a8bfa1e
TL		 767 }
768
f8151e5c 769 if (cpu_class_is_omap2()) {
1a8bfa1e 770 omap2_enable_irq_lch(free_ch);
1a8bfa1e
TL		 771 omap_enable_channel_irq(free_ch);
772 /* Clear the CSR register and IRQ status register */
0499bdeb
TL		 773 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
774 dma_write(1 << free_ch, IRQSTATUS_L0);
1a8bfa1e
TL		 775 }
776
777 *dma_ch_out = free_ch;
778
779 return 0;
780}
97b7f715 781EXPORT_SYMBOL(omap_request_dma);
1a8bfa1e
TL		 782
783void omap_free_dma(int lch)
784{
785 unsigned long flags;
786
1a8bfa1e 787 if (dma_chan[lch].dev_id == -1) {
97b7f715 788 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
1a8bfa1e 789 lch);
1a8bfa1e
TL		 790 return;
791 }
97b7f715 792
1a8bfa1e
TL		 793 if (cpu_class_is_omap1()) {
794 /* Disable all DMA interrupts for the channel. */
0499bdeb 795 dma_write(0, CICR(lch));
1a8bfa1e 796 /* Make sure the DMA transfer is stopped. */
0499bdeb 797 dma_write(0, CCR(lch));
1a8bfa1e
TL		 798 }
799
f8151e5c 800 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 801 u32 val;
802 /* Disable interrupts */
0499bdeb 803 val = dma_read(IRQENABLE_L0);
1a8bfa1e 804 val &= ~(1 << lch);
0499bdeb 805 dma_write(val, IRQENABLE_L0);
1a8bfa1e
TL		 806
807 /* Clear the CSR register and IRQ status register */
0499bdeb
TL		 808 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
809 dma_write(1 << lch, IRQSTATUS_L0);
1a8bfa1e
TL		 810
811 /* Disable all DMA interrupts for the channel. */
0499bdeb 812 dma_write(0, CICR(lch));
1a8bfa1e
TL		 813
814 /* Make sure the DMA transfer is stopped. */
0499bdeb 815 dma_write(0, CCR(lch));
1a8bfa1e
TL		 816 omap_clear_dma(lch);
817 }
da1b94e6
SS		 818
819 spin_lock_irqsave(&dma_chan_lock, flags);
820 dma_chan[lch].dev_id = -1;
821 dma_chan[lch].next_lch = -1;
822 dma_chan[lch].callback = NULL;
823 spin_unlock_irqrestore(&dma_chan_lock, flags);
1a8bfa1e 824}
97b7f715 825EXPORT_SYMBOL(omap_free_dma);
1a8bfa1e 826
f8151e5c
AG		 827/**
828 * @brief omap_dma_set_global_params : Set global priority settings for dma
829 *
830 * @param arb_rate
831 * @param max_fifo_depth
832 * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
833 * DMA_THREAD_RESERVE_ONET
834 * DMA_THREAD_RESERVE_TWOT
835 * DMA_THREAD_RESERVE_THREET
836 */
837void
838omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
839{
840 u32 reg;
841
842 if (!cpu_class_is_omap2()) {
8e86f427 843 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
f8151e5c
AG		 844 return;
845 }
846
847 if (arb_rate == 0)
848 arb_rate = 1;
849
850 reg = (arb_rate & 0xff) << 16;
851 reg |= (0xff & max_fifo_depth);
852
0499bdeb 853 dma_write(reg, GCR);
f8151e5c
AG		 854}
855EXPORT_SYMBOL(omap_dma_set_global_params);
856
857/**
858 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
859 *
860 * @param lch
861 * @param read_prio - Read priority
862 * @param write_prio - Write priority
863 * Both of the above can be set with one of the following values :
864 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
865 */
866int
867omap_dma_set_prio_lch(int lch, unsigned char read_prio,
868 unsigned char write_prio)
869{
0499bdeb 870 u32 l;
f8151e5c 871
4d96372e 872 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
f8151e5c
AG		 873 printk(KERN_ERR "Invalid channel id\n");
874 return -EINVAL;
875 }
0499bdeb
TL		 876 l = dma_read(CCR(lch));
877 l &= ~((1 << 6) | (1 << 26));
44169075 878 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
0499bdeb 879 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
f8151e5c 880 else
0499bdeb
TL		 881 l |= ((read_prio & 0x1) << 6);
882
883 dma_write(l, CCR(lch));
f8151e5c 884
f8151e5c
AG		 885 return 0;
886}
887EXPORT_SYMBOL(omap_dma_set_prio_lch);
888
1a8bfa1e
TL		 889/*
890 * Clears any DMA state so the DMA engine is ready to restart with new buffers
891 * through omap_start_dma(). Any buffers in flight are discarded.
892 */
893void omap_clear_dma(int lch)
894{
895 unsigned long flags;
896
897 local_irq_save(flags);
898
899 if (cpu_class_is_omap1()) {
0499bdeb
TL		 900 u32 l;
901
902 l = dma_read(CCR(lch));
903 l &= ~OMAP_DMA_CCR_EN;
904 dma_write(l, CCR(lch));
1a8bfa1e
TL		 905
906 /* Clear pending interrupts */
0499bdeb 907 l = dma_read(CSR(lch));
1a8bfa1e
TL		 908 }
909
f8151e5c 910 if (cpu_class_is_omap2()) {
1a8bfa1e 911 int i;
0499bdeb 912 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
1a8bfa1e 913 for (i = 0; i < 0x44; i += 4)
0499bdeb 914 __raw_writel(0, lch_base + i);
1a8bfa1e
TL		 915 }
916
917 local_irq_restore(flags);
918}
97b7f715 919EXPORT_SYMBOL(omap_clear_dma);
1a8bfa1e
TL		 920
921void omap_start_dma(int lch)
922{
0499bdeb
TL		 923 u32 l;
924
5e1c5ff4
TL		 925 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
926 int next_lch, cur_lch;
4d96372e 927 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
5e1c5ff4
TL		 928
929 dma_chan_link_map[lch] = 1;
930 /* Set the link register of the first channel */
931 enable_lnk(lch);
932
933 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
934 cur_lch = dma_chan[lch].next_lch;
935 do {
936 next_lch = dma_chan[cur_lch].next_lch;
937
1a8bfa1e 938 /* The loop case: we've been here already */
5e1c5ff4
TL		 939 if (dma_chan_link_map[cur_lch])
940 break;
941 /* Mark the current channel */
942 dma_chan_link_map[cur_lch] = 1;
943
944 enable_lnk(cur_lch);
1a8bfa1e 945 omap_enable_channel_irq(cur_lch);
5e1c5ff4
TL		 946
947 cur_lch = next_lch;
948 } while (next_lch != -1);
284119c4
VP		 949 } else if (cpu_is_omap242x() ||
950 (cpu_is_omap243x() && omap_type() <= OMAP2430_REV_ES1_0)) {
951
1a8bfa1e 952 /* Errata: Need to write lch even if not using chaining */
0499bdeb 953 dma_write(lch, CLNK_CTRL(lch));
5e1c5ff4
TL		 954 }
955
1a8bfa1e
TL		 956 omap_enable_channel_irq(lch);
957
0499bdeb
TL		 958 l = dma_read(CCR(lch));
959
97b7f715
TL		 960 /*
961 * Errata: On ES2.0 BUFFERING disable must be set.
962 * This will always fail on ES1.0
963 */
0499bdeb
TL		 964 if (cpu_is_omap24xx())
965 l |= OMAP_DMA_CCR_EN;
1a8bfa1e 966
0499bdeb
TL		 967 l |= OMAP_DMA_CCR_EN;
968 dma_write(l, CCR(lch));
5e1c5ff4 969
5e1c5ff4
TL		 970 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
971}
97b7f715 972EXPORT_SYMBOL(omap_start_dma);
5e1c5ff4
TL		 973
974void omap_stop_dma(int lch)
975{
0499bdeb
TL		 976 u32 l;
977
5e1c5ff4
TL		 978 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
979 int next_lch, cur_lch = lch;
4d96372e 980 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
5e1c5ff4
TL		 981
982 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
983 do {
984 /* The loop case: we've been here already */
985 if (dma_chan_link_map[cur_lch])
986 break;
987 /* Mark the current channel */
988 dma_chan_link_map[cur_lch] = 1;
989
990 disable_lnk(cur_lch);
991
992 next_lch = dma_chan[cur_lch].next_lch;
993 cur_lch = next_lch;
994 } while (next_lch != -1);
995
996 return;
997 }
1a8bfa1e 998
5e1c5ff4 999 /* Disable all interrupts on the channel */
1a8bfa1e 1000 if (cpu_class_is_omap1())
0499bdeb
TL		 1001 dma_write(0, CICR(lch));
1002
1003 l = dma_read(CCR(lch));
1004 l &= ~OMAP_DMA_CCR_EN;
1005 dma_write(l, CCR(lch));
5e1c5ff4 1006
5e1c5ff4
TL		 1007 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1008}
97b7f715 1009EXPORT_SYMBOL(omap_stop_dma);
5e1c5ff4 1010
709eb3e5
TL		 1011/*
1012 * Allows changing the DMA callback function or data. This may be needed if
1013 * the driver shares a single DMA channel for multiple dma triggers.
1014 */
1015int omap_set_dma_callback(int lch,
97b7f715 1016 void (*callback)(int lch, u16 ch_status, void *data),
709eb3e5
TL		 1017 void *data)
1018{
1019 unsigned long flags;
1020
1021 if (lch < 0)
1022 return -ENODEV;
1023
1024 spin_lock_irqsave(&dma_chan_lock, flags);
1025 if (dma_chan[lch].dev_id == -1) {
1026 printk(KERN_ERR "DMA callback for not set for free channel\n");
1027 spin_unlock_irqrestore(&dma_chan_lock, flags);
1028 return -EINVAL;
1029 }
1030 dma_chan[lch].callback = callback;
1031 dma_chan[lch].data = data;
1032 spin_unlock_irqrestore(&dma_chan_lock, flags);
1033
1034 return 0;
1035}
97b7f715 1036EXPORT_SYMBOL(omap_set_dma_callback);
709eb3e5 1037
1a8bfa1e
TL		 1038/*
1039 * Returns current physical source address for the given DMA channel.
1040 * If the channel is running the caller must disable interrupts prior calling
1041 * this function and process the returned value before re-enabling interrupt to
1042 * prevent races with the interrupt handler. Note that in continuous mode there
1043 * is a chance for CSSA_L register overflow inbetween the two reads resulting
1044 * in incorrect return value.
1045 */
1046dma_addr_t omap_get_dma_src_pos(int lch)
5e1c5ff4 1047{
0695de32 1048 dma_addr_t offset = 0;
5e1c5ff4 1049
0499bdeb
TL		 1050 if (cpu_is_omap15xx())
1051 offset = dma_read(CPC(lch));
1052 else
1053 offset = dma_read(CSAC(lch));
5e1c5ff4 1054
0499bdeb
TL		 1055 /*
1056 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1057 * read before the DMA controller finished disabling the channel.
1058 */
1059 if (!cpu_is_omap15xx() && offset == 0)
1060 offset = dma_read(CSAC(lch));
1061
1062 if (cpu_class_is_omap1())
1063 offset |= (dma_read(CSSA_U(lch)) << 16);
5e1c5ff4 1064
1a8bfa1e 1065 return offset;
5e1c5ff4 1066}
97b7f715 1067EXPORT_SYMBOL(omap_get_dma_src_pos);
5e1c5ff4 1068
1a8bfa1e
TL		 1069/*
1070 * Returns current physical destination address for the given DMA channel.
1071 * If the channel is running the caller must disable interrupts prior calling
1072 * this function and process the returned value before re-enabling interrupt to
1073 * prevent races with the interrupt handler. Note that in continuous mode there
1074 * is a chance for CDSA_L register overflow inbetween the two reads resulting
1075 * in incorrect return value.
1076 */
1077dma_addr_t omap_get_dma_dst_pos(int lch)
5e1c5ff4 1078{
0695de32 1079 dma_addr_t offset = 0;
5e1c5ff4 1080
0499bdeb
TL		 1081 if (cpu_is_omap15xx())
1082 offset = dma_read(CPC(lch));
1083 else
1084 offset = dma_read(CDAC(lch));
5e1c5ff4 1085
0499bdeb
TL		 1086 /*
1087 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1088 * read before the DMA controller finished disabling the channel.
1089 */
1090 if (!cpu_is_omap15xx() && offset == 0)
1091 offset = dma_read(CDAC(lch));
1092
1093 if (cpu_class_is_omap1())
1094 offset |= (dma_read(CDSA_U(lch)) << 16);
5e1c5ff4 1095
1a8bfa1e 1096 return offset;
5e1c5ff4 1097}
97b7f715 1098EXPORT_SYMBOL(omap_get_dma_dst_pos);
0499bdeb
TL		 1099
1100int omap_get_dma_active_status(int lch)
1101{
1102 return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
5e1c5ff4 1103}
0499bdeb 1104EXPORT_SYMBOL(omap_get_dma_active_status);
5e1c5ff4 1105
1a8bfa1e 1106int omap_dma_running(void)
5e1c5ff4 1107{
1a8bfa1e 1108 int lch;
5e1c5ff4 1109
1a8bfa1e
TL		 1110 /* Check if LCD DMA is running */
1111 if (cpu_is_omap16xx())
1112 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1113 return 1;
5e1c5ff4 1114
1a8bfa1e 1115 for (lch = 0; lch < dma_chan_count; lch++)
0499bdeb 1116 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1a8bfa1e 1117 return 1;
5e1c5ff4 1118
1a8bfa1e 1119 return 0;
5e1c5ff4
TL		 1120}
1121
1122/*
1123 * lch_queue DMA will start right after lch_head one is finished.
1124 * For this DMA link to start, you still need to start (see omap_start_dma)
1125 * the first one. That will fire up the entire queue.
1126 */
97b7f715 1127void omap_dma_link_lch(int lch_head, int lch_queue)
5e1c5ff4
TL		 1128{
1129 if (omap_dma_in_1510_mode()) {
1130 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1131 BUG();
1132 return;
1133 }
1134
1135 if ((dma_chan[lch_head].dev_id == -1) ||
1136 (dma_chan[lch_queue].dev_id == -1)) {
1a8bfa1e
TL		 1137 printk(KERN_ERR "omap_dma: trying to link "
1138 "non requested channels\n");
5e1c5ff4
TL		 1139 dump_stack();
1140 }
1141
1142 dma_chan[lch_head].next_lch = lch_queue;
1143}
97b7f715 1144EXPORT_SYMBOL(omap_dma_link_lch);
5e1c5ff4
TL		 1145
1146/*
1147 * Once the DMA queue is stopped, we can destroy it.
1148 */
97b7f715 1149void omap_dma_unlink_lch(int lch_head, int lch_queue)
5e1c5ff4
TL		 1150{
1151 if (omap_dma_in_1510_mode()) {
1152 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1153 BUG();
1154 return;
1155 }
1156
1157 if (dma_chan[lch_head].next_lch != lch_queue ||
1158 dma_chan[lch_head].next_lch == -1) {
1a8bfa1e
TL		 1159 printk(KERN_ERR "omap_dma: trying to unlink "
1160 "non linked channels\n");
5e1c5ff4
TL		 1161 dump_stack();
1162 }
1163
5e1c5ff4
TL		 1164 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1165 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1a8bfa1e
TL		 1166 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1167 "before unlinking\n");
5e1c5ff4
TL		 1168 dump_stack();
1169 }
1170
1171 dma_chan[lch_head].next_lch = -1;
1172}
97b7f715
TL		 1173EXPORT_SYMBOL(omap_dma_unlink_lch);
1174
1175/*----------------------------------------------------------------------------*/
5e1c5ff4 1176
f8151e5c
AG		 1177#ifndef CONFIG_ARCH_OMAP1
1178/* Create chain of DMA channesls */
1179static void create_dma_lch_chain(int lch_head, int lch_queue)
1180{
0499bdeb 1181 u32 l;
f8151e5c
AG		 1182
1183 /* Check if this is the first link in chain */
1184 if (dma_chan[lch_head].next_linked_ch == -1) {
1185 dma_chan[lch_head].next_linked_ch = lch_queue;
1186 dma_chan[lch_head].prev_linked_ch = lch_queue;
1187 dma_chan[lch_queue].next_linked_ch = lch_head;
1188 dma_chan[lch_queue].prev_linked_ch = lch_head;
1189 }
1190
1191 /* a link exists, link the new channel in circular chain */
1192 else {
1193 dma_chan[lch_queue].next_linked_ch =
1194 dma_chan[lch_head].next_linked_ch;
1195 dma_chan[lch_queue].prev_linked_ch = lch_head;
1196 dma_chan[lch_head].next_linked_ch = lch_queue;
1197 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1198 lch_queue;
1199 }
1200
0499bdeb
TL		 1201 l = dma_read(CLNK_CTRL(lch_head));
1202 l &= ~(0x1f);
1203 l |= lch_queue;
1204 dma_write(l, CLNK_CTRL(lch_head));
f8151e5c 1205
0499bdeb
TL		 1206 l = dma_read(CLNK_CTRL(lch_queue));
1207 l &= ~(0x1f);
1208 l |= (dma_chan[lch_queue].next_linked_ch);
1209 dma_write(l, CLNK_CTRL(lch_queue));
f8151e5c
AG		 1210}
1211
1212/**
1213 * @brief omap_request_dma_chain : Request a chain of DMA channels
1214 *
1215 * @param dev_id - Device id using the dma channel
1216 * @param dev_name - Device name
1217 * @param callback - Call back function
1218 * @chain_id -
1219 * @no_of_chans - Number of channels requested
1220 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1221 * OMAP_DMA_DYNAMIC_CHAIN
1222 * @params - Channel parameters
1223 *
1224 * @return - Succes : 0
1225 * Failure: -EINVAL/-ENOMEM
1226 */
1227int omap_request_dma_chain(int dev_id, const char *dev_name,
279b918d 1228 void (*callback) (int lch, u16 ch_status,
f8151e5c
AG		 1229 void *data),
1230 int *chain_id, int no_of_chans, int chain_mode,
1231 struct omap_dma_channel_params params)
1232{
1233 int *channels;
1234 int i, err;
1235
1236 /* Is the chain mode valid ? */
1237 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1238 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1239 printk(KERN_ERR "Invalid chain mode requested\n");
1240 return -EINVAL;
1241 }
1242
1243 if (unlikely((no_of_chans < 1
4d96372e 1244 || no_of_chans > dma_lch_count))) {
f8151e5c
AG		 1245 printk(KERN_ERR "Invalid Number of channels requested\n");
1246 return -EINVAL;
1247 }
1248
1249 /* Allocate a queue to maintain the status of the channels
1250 * in the chain */
1251 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1252 if (channels == NULL) {
1253 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1254 return -ENOMEM;
1255 }
1256
1257 /* request and reserve DMA channels for the chain */
1258 for (i = 0; i < no_of_chans; i++) {
1259 err = omap_request_dma(dev_id, dev_name,
c0fc18c5 1260 callback, NULL, &channels[i]);
f8151e5c
AG		 1261 if (err < 0) {
1262 int j;
1263 for (j = 0; j < i; j++)
1264 omap_free_dma(channels[j]);
1265 kfree(channels);
1266 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1267 return err;
1268 }
f8151e5c
AG		 1269 dma_chan[channels[i]].prev_linked_ch = -1;
1270 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1271
1272 /*
1273 * Allowing client drivers to set common parameters now,
1274 * so that later only relevant (src_start, dest_start
1275 * and element count) can be set
1276 */
1277 omap_set_dma_params(channels[i], &params);
1278 }
1279
1280 *chain_id = channels[0];
1281 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1282 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1283 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1284 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1285
1286 for (i = 0; i < no_of_chans; i++)
1287 dma_chan[channels[i]].chain_id = *chain_id;
1288
1289 /* Reset the Queue pointers */
1290 OMAP_DMA_CHAIN_QINIT(*chain_id);
1291
1292 /* Set up the chain */
1293 if (no_of_chans == 1)
1294 create_dma_lch_chain(channels[0], channels[0]);
1295 else {
1296 for (i = 0; i < (no_of_chans - 1); i++)
1297 create_dma_lch_chain(channels[i], channels[i + 1]);
1298 }
97b7f715 1299
f8151e5c
AG		 1300 return 0;
1301}
1302EXPORT_SYMBOL(omap_request_dma_chain);
1303
1304/**
1305 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1306 * params after setting it. Dont do this while dma is running!!
1307 *
1308 * @param chain_id - Chained logical channel id.
1309 * @param params
1310 *
1311 * @return - Success : 0
1312 * Failure : -EINVAL
1313 */
1314int omap_modify_dma_chain_params(int chain_id,
1315 struct omap_dma_channel_params params)
1316{
1317 int *channels;
1318 u32 i;
1319
1320 /* Check for input params */
1321 if (unlikely((chain_id < 0
4d96372e 1322 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1323 printk(KERN_ERR "Invalid chain id\n");
1324 return -EINVAL;
1325 }
1326
1327 /* Check if the chain exists */
1328 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1329 printk(KERN_ERR "Chain doesn't exists\n");
1330 return -EINVAL;
1331 }
1332 channels = dma_linked_lch[chain_id].linked_dmach_q;
1333
1334 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1335 /*
1336 * Allowing client drivers to set common parameters now,
1337 * so that later only relevant (src_start, dest_start
1338 * and element count) can be set
1339 */
1340 omap_set_dma_params(channels[i], &params);
1341 }
97b7f715 1342
f8151e5c
AG		 1343 return 0;
1344}
1345EXPORT_SYMBOL(omap_modify_dma_chain_params);
1346
1347/**
1348 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1349 *
1350 * @param chain_id
1351 *
1352 * @return - Success : 0
1353 * Failure : -EINVAL
1354 */
1355int omap_free_dma_chain(int chain_id)
1356{
1357 int *channels;
1358 u32 i;
1359
1360 /* Check for input params */
4d96372e 1361 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1362 printk(KERN_ERR "Invalid chain id\n");
1363 return -EINVAL;
1364 }
1365
1366 /* Check if the chain exists */
1367 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1368 printk(KERN_ERR "Chain doesn't exists\n");
1369 return -EINVAL;
1370 }
1371
1372 channels = dma_linked_lch[chain_id].linked_dmach_q;
1373 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1374 dma_chan[channels[i]].next_linked_ch = -1;
1375 dma_chan[channels[i]].prev_linked_ch = -1;
1376 dma_chan[channels[i]].chain_id = -1;
1377 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1378 omap_free_dma(channels[i]);
1379 }
1380
1381 kfree(channels);
1382
1383 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1384 dma_linked_lch[chain_id].chain_mode = -1;
1385 dma_linked_lch[chain_id].chain_state = -1;
97b7f715 1386
f8151e5c
AG		 1387 return (0);
1388}
1389EXPORT_SYMBOL(omap_free_dma_chain);
1390
1391/**
1392 * @brief omap_dma_chain_status - Check if the chain is in
1393 * active / inactive state.
1394 * @param chain_id
1395 *
1396 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1397 * Failure : -EINVAL
1398 */
1399int omap_dma_chain_status(int chain_id)
1400{
1401 /* Check for input params */
4d96372e 1402 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1403 printk(KERN_ERR "Invalid chain id\n");
1404 return -EINVAL;
1405 }
1406
1407 /* Check if the chain exists */
1408 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1409 printk(KERN_ERR "Chain doesn't exists\n");
1410 return -EINVAL;
1411 }
1412 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1413 dma_linked_lch[chain_id].q_count);
1414
1415 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1416 return OMAP_DMA_CHAIN_INACTIVE;
97b7f715 1417
f8151e5c
AG		 1418 return OMAP_DMA_CHAIN_ACTIVE;
1419}
1420EXPORT_SYMBOL(omap_dma_chain_status);
1421
1422/**
1423 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1424 * set the params and start the transfer.
1425 *
1426 * @param chain_id
1427 * @param src_start - buffer start address
1428 * @param dest_start - Dest address
1429 * @param elem_count
1430 * @param frame_count
1431 * @param callbk_data - channel callback parameter data.
1432 *
f4b6a7ef 1433 * @return - Success : 0
f8151e5c
AG		 1434 * Failure: -EINVAL/-EBUSY
1435 */
1436int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1437 int elem_count, int frame_count, void *callbk_data)
1438{
1439 int *channels;
0499bdeb 1440 u32 l, lch;
f8151e5c
AG		 1441 int start_dma = 0;
1442
97b7f715
TL		 1443 /*
1444 * if buffer size is less than 1 then there is
1445 * no use of starting the chain
1446 */
f8151e5c
AG		 1447 if (elem_count < 1) {
1448 printk(KERN_ERR "Invalid buffer size\n");
1449 return -EINVAL;
1450 }
1451
1452 /* Check for input params */
1453 if (unlikely((chain_id < 0
4d96372e 1454 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1455 printk(KERN_ERR "Invalid chain id\n");
1456 return -EINVAL;
1457 }
1458
1459 /* Check if the chain exists */
1460 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1461 printk(KERN_ERR "Chain doesn't exist\n");
1462 return -EINVAL;
1463 }
1464
1465 /* Check if all the channels in chain are in use */
1466 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1467 return -EBUSY;
1468
1469 /* Frame count may be negative in case of indexed transfers */
1470 channels = dma_linked_lch[chain_id].linked_dmach_q;
1471
1472 /* Get a free channel */
1473 lch = channels[dma_linked_lch[chain_id].q_tail];
1474
1475 /* Store the callback data */
1476 dma_chan[lch].data = callbk_data;
1477
1478 /* Increment the q_tail */
1479 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1480
1481 /* Set the params to the free channel */
1482 if (src_start != 0)
0499bdeb 1483 dma_write(src_start, CSSA(lch));
f8151e5c 1484 if (dest_start != 0)
0499bdeb 1485 dma_write(dest_start, CDSA(lch));
f8151e5c
AG		 1486
1487 /* Write the buffer size */
0499bdeb
TL		 1488 dma_write(elem_count, CEN(lch));
1489 dma_write(frame_count, CFN(lch));
f8151e5c 1490
97b7f715
TL		 1491 /*
1492 * If the chain is dynamically linked,
1493 * then we may have to start the chain if its not active
1494 */
f8151e5c
AG		 1495 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1496
97b7f715
TL		 1497 /*
1498 * In Dynamic chain, if the chain is not started,
1499 * queue the channel
1500 */
f8151e5c
AG		 1501 if (dma_linked_lch[chain_id].chain_state ==
1502 DMA_CHAIN_NOTSTARTED) {
1503 /* Enable the link in previous channel */
1504 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1505 DMA_CH_QUEUED)
1506 enable_lnk(dma_chan[lch].prev_linked_ch);
1507 dma_chan[lch].state = DMA_CH_QUEUED;
1508 }
1509
97b7f715
TL		 1510 /*
1511 * Chain is already started, make sure its active,
1512 * if not then start the chain
1513 */
f8151e5c
AG		 1514 else {
1515 start_dma = 1;
1516
1517 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1518 DMA_CH_STARTED) {
1519 enable_lnk(dma_chan[lch].prev_linked_ch);
1520 dma_chan[lch].state = DMA_CH_QUEUED;
1521 start_dma = 0;
0499bdeb
TL		 1522 if (0 == ((1 << 7) & dma_read(
1523 CCR(dma_chan[lch].prev_linked_ch)))) {
f8151e5c
AG		 1524 disable_lnk(dma_chan[lch].
1525 prev_linked_ch);
1526 pr_debug("\n prev ch is stopped\n");
1527 start_dma = 1;
1528 }
1529 }
1530
1531 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1532 == DMA_CH_QUEUED) {
1533 enable_lnk(dma_chan[lch].prev_linked_ch);
1534 dma_chan[lch].state = DMA_CH_QUEUED;
1535 start_dma = 0;
1536 }
1537 omap_enable_channel_irq(lch);
1538
0499bdeb 1539 l = dma_read(CCR(lch));
f8151e5c 1540
0499bdeb
TL		 1541 if ((0 == (l & (1 << 24))))
1542 l &= ~(1 << 25);
f8151e5c 1543 else
0499bdeb 1544 l |= (1 << 25);
f8151e5c 1545 if (start_dma == 1) {
0499bdeb
TL		 1546 if (0 == (l & (1 << 7))) {
1547 l |= (1 << 7);
f8151e5c
AG		 1548 dma_chan[lch].state = DMA_CH_STARTED;
1549 pr_debug("starting %d\n", lch);
0499bdeb 1550 dma_write(l, CCR(lch));
f8151e5c
AG		 1551 } else
1552 start_dma = 0;
1553 } else {
0499bdeb
TL		 1554 if (0 == (l & (1 << 7)))
1555 dma_write(l, CCR(lch));
f8151e5c
AG		 1556 }
1557 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1558 }
1559 }
97b7f715 1560
f4b6a7ef 1561 return 0;
f8151e5c
AG		 1562}
1563EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1564
1565/**
1566 * @brief omap_start_dma_chain_transfers - Start the chain
1567 *
1568 * @param chain_id
1569 *
1570 * @return - Success : 0
1571 * Failure : -EINVAL/-EBUSY
1572 */
1573int omap_start_dma_chain_transfers(int chain_id)
1574{
1575 int *channels;
0499bdeb 1576 u32 l, i;
f8151e5c 1577
4d96372e 1578 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1579 printk(KERN_ERR "Invalid chain id\n");
1580 return -EINVAL;
1581 }
1582
1583 channels = dma_linked_lch[chain_id].linked_dmach_q;
1584
1585 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1586 printk(KERN_ERR "Chain is already started\n");
1587 return -EBUSY;
1588 }
1589
1590 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1591 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1592 i++) {
1593 enable_lnk(channels[i]);
1594 omap_enable_channel_irq(channels[i]);
1595 }
1596 } else {
1597 omap_enable_channel_irq(channels[0]);
1598 }
1599
0499bdeb
TL		 1600 l = dma_read(CCR(channels[0]));
1601 l |= (1 << 7);
f8151e5c
AG		 1602 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1603 dma_chan[channels[0]].state = DMA_CH_STARTED;
1604
0499bdeb
TL		 1605 if ((0 == (l & (1 << 24))))
1606 l &= ~(1 << 25);
f8151e5c 1607 else
0499bdeb
TL		 1608 l |= (1 << 25);
1609 dma_write(l, CCR(channels[0]));
f8151e5c
AG		 1610
1611 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
97b7f715 1612
f8151e5c
AG		 1613 return 0;
1614}
1615EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1616
1617/**
1618 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1619 *
1620 * @param chain_id
1621 *
1622 * @return - Success : 0
1623 * Failure : EINVAL
1624 */
1625int omap_stop_dma_chain_transfers(int chain_id)
1626{
1627 int *channels;
0499bdeb 1628 u32 l, i;
f8151e5c
AG		 1629 u32 sys_cf;
1630
1631 /* Check for input params */
4d96372e 1632 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1633 printk(KERN_ERR "Invalid chain id\n");
1634 return -EINVAL;
1635 }
1636
1637 /* Check if the chain exists */
1638 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1639 printk(KERN_ERR "Chain doesn't exists\n");
1640 return -EINVAL;
1641 }
1642 channels = dma_linked_lch[chain_id].linked_dmach_q;
1643
97b7f715
TL		 1644 /*
1645 * DMA Errata:
f8151e5c
AG		 1646 * Special programming model needed to disable DMA before end of block
1647 */
0499bdeb
TL		 1648 sys_cf = dma_read(OCP_SYSCONFIG);
1649 l = sys_cf;
f8151e5c 1650 /* Middle mode reg set no Standby */
0499bdeb
TL		 1651 l &= ~((1 << 12)|(1 << 13));
1652 dma_write(l, OCP_SYSCONFIG);
f8151e5c
AG		 1653
1654 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1655
1656 /* Stop the Channel transmission */
0499bdeb
TL		 1657 l = dma_read(CCR(channels[i]));
1658 l &= ~(1 << 7);
1659 dma_write(l, CCR(channels[i]));
f8151e5c
AG		 1660
1661 /* Disable the link in all the channels */
1662 disable_lnk(channels[i]);
1663 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1664
1665 }
1666 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1667
1668 /* Reset the Queue pointers */
1669 OMAP_DMA_CHAIN_QINIT(chain_id);
1670
1671 /* Errata - put in the old value */
0499bdeb 1672 dma_write(sys_cf, OCP_SYSCONFIG);
97b7f715 1673
f8151e5c
AG		 1674 return 0;
1675}
1676EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1677
1678/* Get the index of the ongoing DMA in chain */
1679/**
1680 * @brief omap_get_dma_chain_index - Get the element and frame index
1681 * of the ongoing DMA in chain
1682 *
1683 * @param chain_id
1684 * @param ei - Element index
1685 * @param fi - Frame index
1686 *
1687 * @return - Success : 0
1688 * Failure : -EINVAL
1689 */
1690int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1691{
1692 int lch;
1693 int *channels;
1694
1695 /* Check for input params */
4d96372e 1696 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1697 printk(KERN_ERR "Invalid chain id\n");
1698 return -EINVAL;
1699 }
1700
1701 /* Check if the chain exists */
1702 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1703 printk(KERN_ERR "Chain doesn't exists\n");
1704 return -EINVAL;
1705 }
1706 if ((!ei) || (!fi))
1707 return -EINVAL;
1708
1709 channels = dma_linked_lch[chain_id].linked_dmach_q;
1710
1711 /* Get the current channel */
1712 lch = channels[dma_linked_lch[chain_id].q_head];
1713
0499bdeb
TL		 1714 *ei = dma_read(CCEN(lch));
1715 *fi = dma_read(CCFN(lch));
f8151e5c
AG		 1716
1717 return 0;
1718}
1719EXPORT_SYMBOL(omap_get_dma_chain_index);
1720
1721/**
1722 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1723 * ongoing DMA in chain
1724 *
1725 * @param chain_id
1726 *
1727 * @return - Success : Destination position
1728 * Failure : -EINVAL
1729 */
1730int omap_get_dma_chain_dst_pos(int chain_id)
1731{
1732 int lch;
1733 int *channels;
1734
1735 /* Check for input params */
4d96372e 1736 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1737 printk(KERN_ERR "Invalid chain id\n");
1738 return -EINVAL;
1739 }
1740
1741 /* Check if the chain exists */
1742 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1743 printk(KERN_ERR "Chain doesn't exists\n");
1744 return -EINVAL;
1745 }
1746
1747 channels = dma_linked_lch[chain_id].linked_dmach_q;
1748
1749 /* Get the current channel */
1750 lch = channels[dma_linked_lch[chain_id].q_head];
1751
0499bdeb 1752 return dma_read(CDAC(lch));
f8151e5c
AG		 1753}
1754EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1755
1756/**
1757 * @brief omap_get_dma_chain_src_pos - Get the source position
1758 * of the ongoing DMA in chain
1759 * @param chain_id
1760 *
1761 * @return - Success : Destination position
1762 * Failure : -EINVAL
1763 */
1764int omap_get_dma_chain_src_pos(int chain_id)
1765{
1766 int lch;
1767 int *channels;
1768
1769 /* Check for input params */
4d96372e 1770 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1771 printk(KERN_ERR "Invalid chain id\n");
1772 return -EINVAL;
1773 }
1774
1775 /* Check if the chain exists */
1776 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1777 printk(KERN_ERR "Chain doesn't exists\n");
1778 return -EINVAL;
1779 }
1780
1781 channels = dma_linked_lch[chain_id].linked_dmach_q;
1782
1783 /* Get the current channel */
1784 lch = channels[dma_linked_lch[chain_id].q_head];
1785
0499bdeb 1786 return dma_read(CSAC(lch));
f8151e5c
AG		 1787}
1788EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
97b7f715 1789#endif /* ifndef CONFIG_ARCH_OMAP1 */
f8151e5c 1790
1a8bfa1e
TL		 1791/*----------------------------------------------------------------------------*/
1792
1793#ifdef CONFIG_ARCH_OMAP1
1794
1795static int omap1_dma_handle_ch(int ch)
1796{
0499bdeb 1797 u32 csr;
1a8bfa1e
TL		 1798
1799 if (enable_1510_mode && ch >= 6) {
1800 csr = dma_chan[ch].saved_csr;
1801 dma_chan[ch].saved_csr = 0;
1802 } else
0499bdeb 1803 csr = dma_read(CSR(ch));
1a8bfa1e
TL		 1804 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1805 dma_chan[ch + 6].saved_csr = csr >> 7;
1806 csr &= 0x7f;
1807 }
1808 if ((csr & 0x3f) == 0)
1809 return 0;
1810 if (unlikely(dma_chan[ch].dev_id == -1)) {
1811 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1812 "%d (CSR %04x)\n", ch, csr);
1813 return 0;
1814 }
7ff879db 1815 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1a8bfa1e
TL		 1816 printk(KERN_WARNING "DMA timeout with device %d\n",
1817 dma_chan[ch].dev_id);
1818 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1819 printk(KERN_WARNING "DMA synchronization event drop occurred "
1820 "with device %d\n", dma_chan[ch].dev_id);
1821 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1822 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1823 if (likely(dma_chan[ch].callback != NULL))
1824 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
97b7f715 1825
1a8bfa1e
TL		 1826 return 1;
1827}
1828
0cd61b68 1829static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1a8bfa1e
TL		 1830{
1831 int ch = ((int) dev_id) - 1;
1832 int handled = 0;
1833
1834 for (;;) {
1835 int handled_now = 0;
1836
1837 handled_now += omap1_dma_handle_ch(ch);
1838 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1839 handled_now += omap1_dma_handle_ch(ch + 6);
1840 if (!handled_now)
1841 break;
1842 handled += handled_now;
1843 }
1844
1845 return handled ? IRQ_HANDLED : IRQ_NONE;
1846}
1847
1848#else
1849#define omap1_dma_irq_handler NULL
1850#endif
1851
44169075
SS		 1852#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
1853 defined(CONFIG_ARCH_OMAP4)
1a8bfa1e
TL		 1854
1855static int omap2_dma_handle_ch(int ch)
1856{
0499bdeb 1857 u32 status = dma_read(CSR(ch));
1a8bfa1e 1858
3151369d
JY		 1859 if (!status) {
1860 if (printk_ratelimit())
97b7f715
TL		 1861 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1862 ch);
0499bdeb 1863 dma_write(1 << ch, IRQSTATUS_L0);
1a8bfa1e 1864 return 0;
3151369d
JY		 1865 }
1866 if (unlikely(dma_chan[ch].dev_id == -1)) {
1867 if (printk_ratelimit())
1868 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1869 "channel %d\n", status, ch);
1a8bfa1e 1870 return 0;
3151369d 1871 }
1a8bfa1e
TL		 1872 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1873 printk(KERN_INFO
1874 "DMA synchronization event drop occurred with device "
1875 "%d\n", dma_chan[ch].dev_id);
a50f18c7 1876 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1a8bfa1e
TL		 1877 printk(KERN_INFO "DMA transaction error with device %d\n",
1878 dma_chan[ch].dev_id);
a50f18c7
SS		 1879 if (cpu_class_is_omap2()) {
1880 /* Errata: sDMA Channel is not disabled
1881 * after a transaction error. So we explicitely
1882 * disable the channel
1883 */
1884 u32 ccr;
1885
1886 ccr = dma_read(CCR(ch));
1887 ccr &= ~OMAP_DMA_CCR_EN;
1888 dma_write(ccr, CCR(ch));
1889 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1890 }
1891 }
7ff879db
TL		 1892 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1893 printk(KERN_INFO "DMA secure error with device %d\n",
1894 dma_chan[ch].dev_id);
1895 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1896 printk(KERN_INFO "DMA misaligned error with device %d\n",
1897 dma_chan[ch].dev_id);
1a8bfa1e 1898
0499bdeb
TL		 1899 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1900 dma_write(1 << ch, IRQSTATUS_L0);
1a8bfa1e 1901
f8151e5c
AG		 1902 /* If the ch is not chained then chain_id will be -1 */
1903 if (dma_chan[ch].chain_id != -1) {
1904 int chain_id = dma_chan[ch].chain_id;
1905 dma_chan[ch].state = DMA_CH_NOTSTARTED;
0499bdeb 1906 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
f8151e5c
AG		 1907 dma_chan[dma_chan[ch].next_linked_ch].state =
1908 DMA_CH_STARTED;
1909 if (dma_linked_lch[chain_id].chain_mode ==
1910 OMAP_DMA_DYNAMIC_CHAIN)
1911 disable_lnk(ch);
1912
1913 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1914 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1915
0499bdeb 1916 status = dma_read(CSR(ch));
f8151e5c
AG		 1917 }
1918
320ce6f6
JY		 1919 dma_write(status, CSR(ch));
1920
538528de
JN		 1921 if (likely(dma_chan[ch].callback != NULL))
1922 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
f8151e5c 1923
1a8bfa1e
TL		 1924 return 0;
1925}
1926
1927/* STATUS register count is from 1-32 while our is 0-31 */
0cd61b68 1928static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1a8bfa1e 1929{
52176e70 1930 u32 val, enable_reg;
1a8bfa1e
TL		 1931 int i;
1932
0499bdeb 1933 val = dma_read(IRQSTATUS_L0);
3151369d
JY		 1934 if (val == 0) {
1935 if (printk_ratelimit())
1936 printk(KERN_WARNING "Spurious DMA IRQ\n");
1937 return IRQ_HANDLED;
1938 }
52176e70
SS		 1939 enable_reg = dma_read(IRQENABLE_L0);
1940 val &= enable_reg; /* Dispatch only relevant interrupts */
4d96372e 1941 for (i = 0; i < dma_lch_count && val != 0; i++) {
3151369d
JY		 1942 if (val & 1)
1943 omap2_dma_handle_ch(i);
1944 val >>= 1;
1a8bfa1e
TL		 1945 }
1946
1947 return IRQ_HANDLED;
1948}
1949
1950static struct irqaction omap24xx_dma_irq = {
1951 .name = "DMA",
1952 .handler = omap2_dma_irq_handler,
52e405ea 1953 .flags = IRQF_DISABLED
1a8bfa1e
TL		 1954};
1955
1956#else
1957static struct irqaction omap24xx_dma_irq;
1958#endif
1959
1960/*----------------------------------------------------------------------------*/
5e1c5ff4
TL		 1961
1962static struct lcd_dma_info {
1963 spinlock_t lock;
1964 int reserved;
97b7f715 1965 void (*callback)(u16 status, void *data);
5e1c5ff4
TL		 1966 void *cb_data;
1967
1968 int active;
1969 unsigned long addr, size;
1970 int rotate, data_type, xres, yres;
1971 int vxres;
1972 int mirror;
1973 int xscale, yscale;
1974 int ext_ctrl;
1975 int src_port;
1976 int single_transfer;
1977} lcd_dma;
1978
1979void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1980 int data_type)
1981{
1982 lcd_dma.addr = addr;
1983 lcd_dma.data_type = data_type;
1984 lcd_dma.xres = fb_xres;
1985 lcd_dma.yres = fb_yres;
1986}
97b7f715 1987EXPORT_SYMBOL(omap_set_lcd_dma_b1);
5e1c5ff4
TL		 1988
1989void omap_set_lcd_dma_src_port(int port)
1990{
1991 lcd_dma.src_port = port;
1992}
1993
1994void omap_set_lcd_dma_ext_controller(int external)
1995{
1996 lcd_dma.ext_ctrl = external;
1997}
97b7f715 1998EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
5e1c5ff4
TL		 1999
2000void omap_set_lcd_dma_single_transfer(int single)
2001{
2002 lcd_dma.single_transfer = single;
2003}
97b7f715 2004EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
5e1c5ff4
TL		 2005
2006void omap_set_lcd_dma_b1_rotation(int rotate)
2007{
2008 if (omap_dma_in_1510_mode()) {
2009 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
2010 BUG();
2011 return;
2012 }
2013 lcd_dma.rotate = rotate;
2014}
97b7f715 2015EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
5e1c5ff4
TL		 2016
2017void omap_set_lcd_dma_b1_mirror(int mirror)
2018{
2019 if (omap_dma_in_1510_mode()) {
2020 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
2021 BUG();
2022 }
2023 lcd_dma.mirror = mirror;
2024}
97b7f715 2025EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
5e1c5ff4
TL		 2026
2027void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
2028{
2029 if (omap_dma_in_1510_mode()) {
2030 printk(KERN_ERR "DMA virtual resulotion is not supported "
2031 "in 1510 mode\n");
2032 BUG();
2033 }
2034 lcd_dma.vxres = vxres;
2035}
97b7f715 2036EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
5e1c5ff4
TL		 2037
2038void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
2039{
2040 if (omap_dma_in_1510_mode()) {
2041 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
2042 BUG();
2043 }
2044 lcd_dma.xscale = xscale;
2045 lcd_dma.yscale = yscale;
2046}
97b7f715 2047EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
5e1c5ff4
TL		 2048
2049static void set_b1_regs(void)
2050{
2051 unsigned long top, bottom;
2052 int es;
2053 u16 w;
2054 unsigned long en, fn;
2055 long ei, fi;
2056 unsigned long vxres;
2057 unsigned int xscale, yscale;
2058
2059 switch (lcd_dma.data_type) {
2060 case OMAP_DMA_DATA_TYPE_S8:
2061 es = 1;
2062 break;
2063 case OMAP_DMA_DATA_TYPE_S16:
2064 es = 2;
2065 break;
2066 case OMAP_DMA_DATA_TYPE_S32:
2067 es = 4;
2068 break;
2069 default:
2070 BUG();
2071 return;
2072 }
2073
2074 vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2075 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2076 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2077 BUG_ON(vxres < lcd_dma.xres);
97b7f715
TL		 2078
2079#define PIXADDR(x, y) (lcd_dma.addr + \
2080 ((y) * vxres * yscale + (x) * xscale) * es)
5e1c5ff4 2081#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
97b7f715 2082
5e1c5ff4
TL		 2083 switch (lcd_dma.rotate) {
2084 case 0:
2085 if (!lcd_dma.mirror) {
2086 top = PIXADDR(0, 0);
2087 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2088 /* 1510 DMA requires the bottom address to be 2 more
2089 * than the actual last memory access location. */
2090 if (omap_dma_in_1510_mode() &&
97b7f715
TL		 2091 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2092 bottom += 2;
5e1c5ff4
TL		 2093 ei = PIXSTEP(0, 0, 1, 0);
2094 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2095 } else {
2096 top = PIXADDR(lcd_dma.xres - 1, 0);
2097 bottom = PIXADDR(0, lcd_dma.yres - 1);
2098 ei = PIXSTEP(1, 0, 0, 0);
2099 fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2100 }
2101 en = lcd_dma.xres;
2102 fn = lcd_dma.yres;
2103 break;
2104 case 90:
2105 if (!lcd_dma.mirror) {
2106 top = PIXADDR(0, lcd_dma.yres - 1);
2107 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2108 ei = PIXSTEP(0, 1, 0, 0);
2109 fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2110 } else {
2111 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2112 bottom = PIXADDR(0, 0);
2113 ei = PIXSTEP(0, 1, 0, 0);
2114 fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2115 }
2116 en = lcd_dma.yres;
2117 fn = lcd_dma.xres;
2118 break;
2119 case 180:
2120 if (!lcd_dma.mirror) {
2121 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2122 bottom = PIXADDR(0, 0);
2123 ei = PIXSTEP(1, 0, 0, 0);
2124 fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2125 } else {
2126 top = PIXADDR(0, lcd_dma.yres - 1);
2127 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2128 ei = PIXSTEP(0, 0, 1, 0);
2129 fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2130 }
2131 en = lcd_dma.xres;
2132 fn = lcd_dma.yres;
2133 break;
2134 case 270:
2135 if (!lcd_dma.mirror) {
2136 top = PIXADDR(lcd_dma.xres - 1, 0);
2137 bottom = PIXADDR(0, lcd_dma.yres - 1);
2138 ei = PIXSTEP(0, 0, 0, 1);
2139 fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2140 } else {
2141 top = PIXADDR(0, 0);
2142 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2143 ei = PIXSTEP(0, 0, 0, 1);
2144 fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2145 }
2146 en = lcd_dma.yres;
2147 fn = lcd_dma.xres;
2148 break;
2149 default:
2150 BUG();
6cbdc8c5 2151 return; /* Suppress warning about uninitialized vars */
5e1c5ff4
TL		 2152 }
2153
2154 if (omap_dma_in_1510_mode()) {
2155 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2156 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2157 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2158 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2159
2160 return;
2161 }
2162
2163 /* 1610 regs */
2164 omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2165 omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2166 omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2167 omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2168
2169 omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2170 omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2171
2172 w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2173 w &= ~0x03;
2174 w |= lcd_dma.data_type;
2175 omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2176
2177 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2178 /* Always set the source port as SDRAM for now*/
2179 w &= ~(0x03 << 6);
5e1c5ff4 2180 if (lcd_dma.callback != NULL)
1a8bfa1e 2181 w |= 1 << 1; /* Block interrupt enable */
5e1c5ff4
TL		 2182 else
2183 w &= ~(1 << 1);
2184 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2185
2186 if (!(lcd_dma.rotate || lcd_dma.mirror ||
2187 lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2188 return;
2189
2190 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2191 /* Set the double-indexed addressing mode */
2192 w |= (0x03 << 12);
2193 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2194
2195 omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2196 omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2197 omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2198}
2199
0cd61b68 2200static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
5e1c5ff4
TL		 2201{
2202 u16 w;
2203
2204 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2205 if (unlikely(!(w & (1 << 3)))) {
2206 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2207 return IRQ_NONE;
2208 }
2209 /* Ack the IRQ */
2210 w |= (1 << 3);
2211 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2212 lcd_dma.active = 0;
2213 if (lcd_dma.callback != NULL)
2214 lcd_dma.callback(w, lcd_dma.cb_data);
2215
2216 return IRQ_HANDLED;
2217}
2218
97b7f715 2219int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
5e1c5ff4
TL		 2220 void *data)
2221{
2222 spin_lock_irq(&lcd_dma.lock);
2223 if (lcd_dma.reserved) {
2224 spin_unlock_irq(&lcd_dma.lock);
2225 printk(KERN_ERR "LCD DMA channel already reserved\n");
2226 BUG();
2227 return -EBUSY;
2228 }
2229 lcd_dma.reserved = 1;
2230 spin_unlock_irq(&lcd_dma.lock);
2231 lcd_dma.callback = callback;
2232 lcd_dma.cb_data = data;
2233 lcd_dma.active = 0;
2234 lcd_dma.single_transfer = 0;
2235 lcd_dma.rotate = 0;
2236 lcd_dma.vxres = 0;
2237 lcd_dma.mirror = 0;
2238 lcd_dma.xscale = 0;
2239 lcd_dma.yscale = 0;
2240 lcd_dma.ext_ctrl = 0;
2241 lcd_dma.src_port = 0;
2242
2243 return 0;
2244}
97b7f715 2245EXPORT_SYMBOL(omap_request_lcd_dma);
5e1c5ff4
TL		 2246
2247void omap_free_lcd_dma(void)
2248{
2249 spin_lock(&lcd_dma.lock);
2250 if (!lcd_dma.reserved) {
2251 spin_unlock(&lcd_dma.lock);
2252 printk(KERN_ERR "LCD DMA is not reserved\n");
2253 BUG();
2254 return;
2255 }
2256 if (!enable_1510_mode)
1a8bfa1e
TL		 2257 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2258 OMAP1610_DMA_LCD_CCR);
5e1c5ff4
TL		 2259 lcd_dma.reserved = 0;
2260 spin_unlock(&lcd_dma.lock);
2261}
97b7f715 2262EXPORT_SYMBOL(omap_free_lcd_dma);
5e1c5ff4
TL		 2263
2264void omap_enable_lcd_dma(void)
2265{
2266 u16 w;
2267
97b7f715
TL		 2268 /*
2269 * Set the Enable bit only if an external controller is
5e1c5ff4
TL		 2270 * connected. Otherwise the OMAP internal controller will
2271 * start the transfer when it gets enabled.
2272 */
2273 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2274 return;
bb13b5fd
TL		 2275
2276 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2277 w |= 1 << 8;
2278 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2279
92105bb7
TL		 2280 lcd_dma.active = 1;
2281
5e1c5ff4
TL		 2282 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2283 w |= 1 << 7;
2284 omap_writew(w, OMAP1610_DMA_LCD_CCR);
5e1c5ff4 2285}
97b7f715 2286EXPORT_SYMBOL(omap_enable_lcd_dma);
5e1c5ff4
TL		 2287
2288void omap_setup_lcd_dma(void)
2289{
2290 BUG_ON(lcd_dma.active);
2291 if (!enable_1510_mode) {
2292 /* Set some reasonable defaults */
2293 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2294 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2295 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2296 }
2297 set_b1_regs();
2298 if (!enable_1510_mode) {
2299 u16 w;
2300
2301 w = omap_readw(OMAP1610_DMA_LCD_CCR);
97b7f715
TL		 2302 /*
2303 * If DMA was already active set the end_prog bit to have
5e1c5ff4
TL		 2304 * the programmed register set loaded into the active
2305 * register set.
2306 */
2307 w |= 1 << 11; /* End_prog */
2308 if (!lcd_dma.single_transfer)
97b7f715 2309 w |= (3 << 8); /* Auto_init, repeat */
5e1c5ff4
TL		 2310 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2311 }
2312}
97b7f715 2313EXPORT_SYMBOL(omap_setup_lcd_dma);
5e1c5ff4
TL		 2314
2315void omap_stop_lcd_dma(void)
2316{
bb13b5fd
TL		 2317 u16 w;
2318
5e1c5ff4 2319 lcd_dma.active = 0;
bb13b5fd
TL		 2320 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2321 return;
2322
2323 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2324 w &= ~(1 << 7);
2325 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2326
2327 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2328 w &= ~(1 << 8);
2329 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
5e1c5ff4 2330}
97b7f715 2331EXPORT_SYMBOL(omap_stop_lcd_dma);
5e1c5ff4 2332
1a8bfa1e 2333/*----------------------------------------------------------------------------*/
bb13b5fd 2334
5e1c5ff4
TL		 2335static int __init omap_init_dma(void)
2336{
2337 int ch, r;
2338
0499bdeb 2339 if (cpu_class_is_omap1()) {
94113260 2340 omap_dma_base = OMAP1_IO_ADDRESS(OMAP1_DMA_BASE);
4d96372e 2341 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
0499bdeb 2342 } else if (cpu_is_omap24xx()) {
94113260 2343 omap_dma_base = OMAP2_IO_ADDRESS(OMAP24XX_DMA4_BASE);
4d96372e 2344 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
0499bdeb 2345 } else if (cpu_is_omap34xx()) {
94113260 2346 omap_dma_base = OMAP2_IO_ADDRESS(OMAP34XX_DMA4_BASE);
0499bdeb 2347 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
44169075 2348 } else if (cpu_is_omap44xx()) {
94113260 2349 omap_dma_base = OMAP2_IO_ADDRESS(OMAP44XX_DMA4_BASE);
44169075 2350 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
0499bdeb
TL		 2351 } else {
2352 pr_err("DMA init failed for unsupported omap\n");
2353 return -ENODEV;
2354 }
4d96372e 2355
2263f022
SS		 2356 if (cpu_class_is_omap2() && omap_dma_reserve_channels
2357 && (omap_dma_reserve_channels <= dma_lch_count))
2358 dma_lch_count = omap_dma_reserve_channels;
2359
4d96372e
TL		 2360 dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2361 GFP_KERNEL);
2362 if (!dma_chan)
2363 return -ENOMEM;
2364
2365 if (cpu_class_is_omap2()) {
2366 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2367 dma_lch_count, GFP_KERNEL);
2368 if (!dma_linked_lch) {
2369 kfree(dma_chan);
2370 return -ENOMEM;
2371 }
2372 }
2373
1a8bfa1e
TL		 2374 if (cpu_is_omap15xx()) {
2375 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
5e1c5ff4
TL		 2376 dma_chan_count = 9;
2377 enable_1510_mode = 1;
557096fe 2378 } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
5e1c5ff4 2379 printk(KERN_INFO "OMAP DMA hardware version %d\n",
0499bdeb 2380 dma_read(HW_ID));
5e1c5ff4 2381 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
0499bdeb
TL		 2382 (dma_read(CAPS_0_U) << 16) |
2383 dma_read(CAPS_0_L),
2384 (dma_read(CAPS_1_U) << 16) |
2385 dma_read(CAPS_1_L),
2386 dma_read(CAPS_2), dma_read(CAPS_3),
2387 dma_read(CAPS_4));
5e1c5ff4
TL		 2388 if (!enable_1510_mode) {
2389 u16 w;
2390
2391 /* Disable OMAP 3.0/3.1 compatibility mode. */
0499bdeb 2392 w = dma_read(GSCR);
5e1c5ff4 2393 w |= 1 << 3;
0499bdeb 2394 dma_write(w, GSCR);
5e1c5ff4
TL		 2395 dma_chan_count = 16;
2396 } else
2397 dma_chan_count = 9;
b5beef5d
ID		 2398 if (cpu_is_omap16xx()) {
2399 u16 w;
2400
2401 /* this would prevent OMAP sleep */
2402 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2403 w &= ~(1 << 8);
2404 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2405 }
f8151e5c 2406 } else if (cpu_class_is_omap2()) {
0499bdeb 2407 u8 revision = dma_read(REVISION) & 0xff;
1a8bfa1e
TL		 2408 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2409 revision >> 4, revision & 0xf);
2263f022 2410 dma_chan_count = dma_lch_count;
5e1c5ff4
TL		 2411 } else {
2412 dma_chan_count = 0;
2413 return 0;
2414 }
2415
5e1c5ff4
TL		 2416 spin_lock_init(&lcd_dma.lock);
2417 spin_lock_init(&dma_chan_lock);
5e1c5ff4
TL		 2418
2419 for (ch = 0; ch < dma_chan_count; ch++) {
1a8bfa1e 2420 omap_clear_dma(ch);
5e1c5ff4
TL		 2421 dma_chan[ch].dev_id = -1;
2422 dma_chan[ch].next_lch = -1;
2423
2424 if (ch >= 6 && enable_1510_mode)
2425 continue;
2426
1a8bfa1e 2427 if (cpu_class_is_omap1()) {
97b7f715
TL		 2428 /*
2429 * request_irq() doesn't like dev_id (ie. ch) being
2430 * zero, so we have to kludge around this.
2431 */
1a8bfa1e
TL		 2432 r = request_irq(omap1_dma_irq[ch],
2433 omap1_dma_irq_handler, 0, "DMA",
2434 (void *) (ch + 1));
2435 if (r != 0) {
2436 int i;
2437
2438 printk(KERN_ERR "unable to request IRQ %d "
2439 "for DMA (error %d)\n",
2440 omap1_dma_irq[ch], r);
2441 for (i = 0; i < ch; i++)
2442 free_irq(omap1_dma_irq[i],
2443 (void *) (i + 1));
2444 return r;
2445 }
2446 }
2447 }
2448
44169075 2449 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
f8151e5c
AG		 2450 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2451 DMA_DEFAULT_FIFO_DEPTH, 0);
2452
44169075
SS		 2453 if (cpu_class_is_omap2()) {
2454 int irq;
2455 if (cpu_is_omap44xx())
2456 irq = INT_44XX_SDMA_IRQ0;
2457 else
2458 irq = INT_24XX_SDMA_IRQ0;
2459 setup_irq(irq, &omap24xx_dma_irq);
2460 }
1a8bfa1e 2461
aecedb94
KJ		 2462 /* Enable smartidle idlemodes and autoidle */
2463 if (cpu_is_omap34xx()) {
2464 u32 v = dma_read(OCP_SYSCONFIG);
2465 v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
2466 DMA_SYSCONFIG_SIDLEMODE_MASK |
2467 DMA_SYSCONFIG_AUTOIDLE);
2468 v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2469 DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2470 DMA_SYSCONFIG_AUTOIDLE);
2471 dma_write(v , OCP_SYSCONFIG);
2472 }
2473
2474
1a8bfa1e
TL		 2475 /* FIXME: Update LCD DMA to work on 24xx */
2476 if (cpu_class_is_omap1()) {
2477 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2478 "LCD DMA", NULL);
5e1c5ff4
TL		 2479 if (r != 0) {
2480 int i;
2481
1a8bfa1e
TL		 2482 printk(KERN_ERR "unable to request IRQ for LCD DMA "
2483 "(error %d)\n", r);
2484 for (i = 0; i < dma_chan_count; i++)
2485 free_irq(omap1_dma_irq[i], (void *) (i + 1));
5e1c5ff4
TL		 2486 return r;
2487 }
2488 }
5e1c5ff4 2489
5e1c5ff4
TL		 2490 return 0;
2491}
2492
2493arch_initcall(omap_init_dma);
2494
2263f022
SS		 2495/*
2496 * Reserve the omap SDMA channels using cmdline bootarg
2497 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2498 */
2499static int __init omap_dma_cmdline_reserve_ch(char *str)
2500{
2501 if (get_option(&str, &omap_dma_reserve_channels) != 1)
2502 omap_dma_reserve_channels = 0;
2503 return 1;
2504}
2505
2506__setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2507
5e1c5ff4 2508
Linux kernel - Deliverables
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