Commit | Line | Data |
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5e1c5ff4 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/dma.c | |
3 | * | |
97b7f715 | 4 | * Copyright (C) 2003 - 2008 Nokia Corporation |
96de0e25 | 5 | * Author: Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 TL |
6 | * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> |
7 | * Graphics DMA and LCD DMA graphics tranformations | |
8 | * by Imre Deak <imre.deak@nokia.com> | |
f8151e5c | 9 | * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc. |
1a8bfa1e | 10 | * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com> |
5e1c5ff4 TL |
11 | * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. |
12 | * | |
44169075 SS |
13 | * Copyright (C) 2009 Texas Instruments |
14 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
15 | * | |
5e1c5ff4 TL |
16 | * Support functions for the OMAP internal DMA channels. |
17 | * | |
f31cc962 MK |
18 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ |
19 | * Converted DMA library into DMA platform driver. | |
20 | * - G, Manjunath Kondaiah <manjugk@ti.com> | |
21 | * | |
5e1c5ff4 TL |
22 | * This program is free software; you can redistribute it and/or modify |
23 | * it under the terms of the GNU General Public License version 2 as | |
24 | * published by the Free Software Foundation. | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/module.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/sched.h> | |
31 | #include <linux/spinlock.h> | |
32 | #include <linux/errno.h> | |
33 | #include <linux/interrupt.h> | |
418ca1f0 | 34 | #include <linux/irq.h> |
97b7f715 | 35 | #include <linux/io.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
0e4905c0 | 37 | #include <linux/delay.h> |
5e1c5ff4 | 38 | |
2b6c4e73 | 39 | #include <plat-omap/dma-omap.h> |
5e1c5ff4 | 40 | |
e4c060db TL |
41 | #include "../mach-omap1/soc.h" |
42 | #include "../mach-omap2/soc.h" | |
43 | ||
bc4d8b5f PW |
44 | /* |
45 | * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA | |
46 | * channels that an instance of the SDMA IP block can support. Used | |
47 | * to size arrays. (The actual maximum on a particular SoC may be less | |
48 | * than this -- for example, OMAP1 SDMA instances only support 17 logical | |
49 | * DMA channels.) | |
50 | */ | |
51 | #define MAX_LOGICAL_DMA_CH_COUNT 32 | |
52 | ||
f8151e5c AG |
53 | #undef DEBUG |
54 | ||
55 | #ifndef CONFIG_ARCH_OMAP1 | |
56 | enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED, | |
57 | DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED | |
58 | }; | |
59 | ||
60 | enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; | |
1a8bfa1e | 61 | #endif |
5e1c5ff4 | 62 | |
97b7f715 | 63 | #define OMAP_DMA_ACTIVE 0x01 |
4fb699b4 | 64 | #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff |
5e1c5ff4 | 65 | |
97b7f715 | 66 | #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) |
5e1c5ff4 | 67 | |
f31cc962 MK |
68 | static struct omap_system_dma_plat_info *p; |
69 | static struct omap_dma_dev_attr *d; | |
70 | ||
97b7f715 | 71 | static int enable_1510_mode; |
d3c9be2f | 72 | static u32 errata; |
5e1c5ff4 | 73 | |
f2d11858 TK |
74 | static struct omap_dma_global_context_registers { |
75 | u32 dma_irqenable_l0; | |
76 | u32 dma_ocp_sysconfig; | |
77 | u32 dma_gcr; | |
78 | } omap_dma_global_context; | |
79 | ||
f8151e5c AG |
80 | struct dma_link_info { |
81 | int *linked_dmach_q; | |
82 | int no_of_lchs_linked; | |
83 | ||
84 | int q_count; | |
85 | int q_tail; | |
86 | int q_head; | |
87 | ||
88 | int chain_state; | |
89 | int chain_mode; | |
90 | ||
91 | }; | |
92 | ||
4d96372e TL |
93 | static struct dma_link_info *dma_linked_lch; |
94 | ||
95 | #ifndef CONFIG_ARCH_OMAP1 | |
f8151e5c AG |
96 | |
97 | /* Chain handling macros */ | |
98 | #define OMAP_DMA_CHAIN_QINIT(chain_id) \ | |
99 | do { \ | |
100 | dma_linked_lch[chain_id].q_head = \ | |
101 | dma_linked_lch[chain_id].q_tail = \ | |
102 | dma_linked_lch[chain_id].q_count = 0; \ | |
103 | } while (0) | |
104 | #define OMAP_DMA_CHAIN_QFULL(chain_id) \ | |
105 | (dma_linked_lch[chain_id].no_of_lchs_linked == \ | |
106 | dma_linked_lch[chain_id].q_count) | |
107 | #define OMAP_DMA_CHAIN_QLAST(chain_id) \ | |
108 | do { \ | |
109 | ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \ | |
110 | dma_linked_lch[chain_id].q_count) \ | |
111 | } while (0) | |
112 | #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \ | |
113 | (0 == dma_linked_lch[chain_id].q_count) | |
114 | #define __OMAP_DMA_CHAIN_INCQ(end) \ | |
115 | ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked) | |
116 | #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \ | |
117 | do { \ | |
118 | __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \ | |
119 | dma_linked_lch[chain_id].q_count--; \ | |
120 | } while (0) | |
121 | ||
122 | #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \ | |
123 | do { \ | |
124 | __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \ | |
125 | dma_linked_lch[chain_id].q_count++; \ | |
126 | } while (0) | |
127 | #endif | |
4d96372e TL |
128 | |
129 | static int dma_lch_count; | |
5e1c5ff4 | 130 | static int dma_chan_count; |
2263f022 | 131 | static int omap_dma_reserve_channels; |
5e1c5ff4 TL |
132 | |
133 | static spinlock_t dma_chan_lock; | |
4d96372e | 134 | static struct omap_dma_lch *dma_chan; |
5e1c5ff4 | 135 | |
f8151e5c AG |
136 | static inline void disable_lnk(int lch); |
137 | static void omap_disable_channel_irq(int lch); | |
138 | static inline void omap_enable_channel_irq(int lch); | |
139 | ||
1a8bfa1e | 140 | #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \ |
8e86f427 | 141 | __func__); |
1a8bfa1e TL |
142 | |
143 | #ifdef CONFIG_ARCH_OMAP15XX | |
144 | /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ | |
c7767582 | 145 | static int omap_dma_in_1510_mode(void) |
1a8bfa1e TL |
146 | { |
147 | return enable_1510_mode; | |
148 | } | |
149 | #else | |
150 | #define omap_dma_in_1510_mode() 0 | |
151 | #endif | |
152 | ||
153 | #ifdef CONFIG_ARCH_OMAP1 | |
5e1c5ff4 TL |
154 | static inline int get_gdma_dev(int req) |
155 | { | |
156 | u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; | |
157 | int shift = ((req - 1) % 5) * 6; | |
158 | ||
159 | return ((omap_readl(reg) >> shift) & 0x3f) + 1; | |
160 | } | |
161 | ||
162 | static inline void set_gdma_dev(int req, int dev) | |
163 | { | |
164 | u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4; | |
165 | int shift = ((req - 1) % 5) * 6; | |
166 | u32 l; | |
167 | ||
168 | l = omap_readl(reg); | |
169 | l &= ~(0x3f << shift); | |
170 | l |= (dev - 1) << shift; | |
171 | omap_writel(l, reg); | |
172 | } | |
1a8bfa1e TL |
173 | #else |
174 | #define set_gdma_dev(req, dev) do {} while (0) | |
2c799cef TL |
175 | #define omap_readl(reg) 0 |
176 | #define omap_writel(val, reg) do {} while (0) | |
1a8bfa1e | 177 | #endif |
5e1c5ff4 | 178 | |
54b693d4 | 179 | #ifdef CONFIG_ARCH_OMAP1 |
709eb3e5 | 180 | void omap_set_dma_priority(int lch, int dst_port, int priority) |
5e1c5ff4 TL |
181 | { |
182 | unsigned long reg; | |
183 | u32 l; | |
184 | ||
709eb3e5 TL |
185 | if (cpu_class_is_omap1()) { |
186 | switch (dst_port) { | |
187 | case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */ | |
188 | reg = OMAP_TC_OCPT1_PRIOR; | |
189 | break; | |
190 | case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */ | |
191 | reg = OMAP_TC_OCPT2_PRIOR; | |
192 | break; | |
193 | case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */ | |
194 | reg = OMAP_TC_EMIFF_PRIOR; | |
195 | break; | |
196 | case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */ | |
197 | reg = OMAP_TC_EMIFS_PRIOR; | |
198 | break; | |
199 | default: | |
200 | BUG(); | |
201 | return; | |
202 | } | |
203 | l = omap_readl(reg); | |
204 | l &= ~(0xf << 8); | |
205 | l |= (priority & 0xf) << 8; | |
206 | omap_writel(l, reg); | |
207 | } | |
54b693d4 TL |
208 | } |
209 | #endif | |
709eb3e5 | 210 | |
54b693d4 TL |
211 | #ifdef CONFIG_ARCH_OMAP2PLUS |
212 | void omap_set_dma_priority(int lch, int dst_port, int priority) | |
213 | { | |
214 | u32 ccr; | |
215 | ||
216 | ccr = p->dma_read(CCR, lch); | |
217 | if (priority) | |
218 | ccr |= (1 << 6); | |
219 | else | |
220 | ccr &= ~(1 << 6); | |
221 | p->dma_write(ccr, CCR, lch); | |
5e1c5ff4 | 222 | } |
54b693d4 | 223 | #endif |
97b7f715 | 224 | EXPORT_SYMBOL(omap_set_dma_priority); |
5e1c5ff4 TL |
225 | |
226 | void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, | |
1a8bfa1e TL |
227 | int frame_count, int sync_mode, |
228 | int dma_trigger, int src_or_dst_synch) | |
5e1c5ff4 | 229 | { |
0499bdeb TL |
230 | u32 l; |
231 | ||
f31cc962 | 232 | l = p->dma_read(CSDP, lch); |
0499bdeb TL |
233 | l &= ~0x03; |
234 | l |= data_type; | |
f31cc962 | 235 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 236 | |
1a8bfa1e | 237 | if (cpu_class_is_omap1()) { |
0499bdeb TL |
238 | u16 ccr; |
239 | ||
f31cc962 | 240 | ccr = p->dma_read(CCR, lch); |
0499bdeb | 241 | ccr &= ~(1 << 5); |
1a8bfa1e | 242 | if (sync_mode == OMAP_DMA_SYNC_FRAME) |
0499bdeb | 243 | ccr |= 1 << 5; |
f31cc962 | 244 | p->dma_write(ccr, CCR, lch); |
1a8bfa1e | 245 | |
f31cc962 | 246 | ccr = p->dma_read(CCR2, lch); |
0499bdeb | 247 | ccr &= ~(1 << 2); |
1a8bfa1e | 248 | if (sync_mode == OMAP_DMA_SYNC_BLOCK) |
0499bdeb | 249 | ccr |= 1 << 2; |
f31cc962 | 250 | p->dma_write(ccr, CCR2, lch); |
1a8bfa1e TL |
251 | } |
252 | ||
f8151e5c | 253 | if (cpu_class_is_omap2() && dma_trigger) { |
0499bdeb | 254 | u32 val; |
1a8bfa1e | 255 | |
f31cc962 | 256 | val = p->dma_read(CCR, lch); |
4b3cf448 AG |
257 | |
258 | /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */ | |
72a1179e | 259 | val &= ~((1 << 23) | (3 << 19) | 0x1f); |
4b3cf448 AG |
260 | val |= (dma_trigger & ~0x1f) << 14; |
261 | val |= dma_trigger & 0x1f; | |
5e1c5ff4 | 262 | |
1a8bfa1e TL |
263 | if (sync_mode & OMAP_DMA_SYNC_FRAME) |
264 | val |= 1 << 5; | |
eca9e56e PU |
265 | else |
266 | val &= ~(1 << 5); | |
5e1c5ff4 | 267 | |
1a8bfa1e TL |
268 | if (sync_mode & OMAP_DMA_SYNC_BLOCK) |
269 | val |= 1 << 18; | |
eca9e56e PU |
270 | else |
271 | val &= ~(1 << 18); | |
5e1c5ff4 | 272 | |
72a1179e SO |
273 | if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) { |
274 | val &= ~(1 << 24); /* dest synch */ | |
275 | val |= (1 << 23); /* Prefetch */ | |
276 | } else if (src_or_dst_synch) { | |
1a8bfa1e | 277 | val |= 1 << 24; /* source synch */ |
72a1179e | 278 | } else { |
1a8bfa1e | 279 | val &= ~(1 << 24); /* dest synch */ |
72a1179e | 280 | } |
f31cc962 | 281 | p->dma_write(val, CCR, lch); |
1a8bfa1e TL |
282 | } |
283 | ||
f31cc962 MK |
284 | p->dma_write(elem_count, CEN, lch); |
285 | p->dma_write(frame_count, CFN, lch); | |
5e1c5ff4 | 286 | } |
97b7f715 | 287 | EXPORT_SYMBOL(omap_set_dma_transfer_params); |
1a8bfa1e | 288 | |
5e1c5ff4 TL |
289 | void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) |
290 | { | |
5e1c5ff4 TL |
291 | BUG_ON(omap_dma_in_1510_mode()); |
292 | ||
0815f8ea TV |
293 | if (cpu_class_is_omap1()) { |
294 | u16 w; | |
1a8bfa1e | 295 | |
f31cc962 | 296 | w = p->dma_read(CCR2, lch); |
0815f8ea TV |
297 | w &= ~0x03; |
298 | ||
299 | switch (mode) { | |
300 | case OMAP_DMA_CONSTANT_FILL: | |
301 | w |= 0x01; | |
302 | break; | |
303 | case OMAP_DMA_TRANSPARENT_COPY: | |
304 | w |= 0x02; | |
305 | break; | |
306 | case OMAP_DMA_COLOR_DIS: | |
307 | break; | |
308 | default: | |
309 | BUG(); | |
310 | } | |
f31cc962 | 311 | p->dma_write(w, CCR2, lch); |
0815f8ea | 312 | |
f31cc962 | 313 | w = p->dma_read(LCH_CTRL, lch); |
0815f8ea TV |
314 | w &= ~0x0f; |
315 | /* Default is channel type 2D */ | |
316 | if (mode) { | |
f31cc962 | 317 | p->dma_write(color, COLOR, lch); |
0815f8ea TV |
318 | w |= 1; /* Channel type G */ |
319 | } | |
f31cc962 | 320 | p->dma_write(w, LCH_CTRL, lch); |
5e1c5ff4 | 321 | } |
0815f8ea TV |
322 | |
323 | if (cpu_class_is_omap2()) { | |
324 | u32 val; | |
325 | ||
f31cc962 | 326 | val = p->dma_read(CCR, lch); |
0815f8ea TV |
327 | val &= ~((1 << 17) | (1 << 16)); |
328 | ||
329 | switch (mode) { | |
330 | case OMAP_DMA_CONSTANT_FILL: | |
331 | val |= 1 << 16; | |
332 | break; | |
333 | case OMAP_DMA_TRANSPARENT_COPY: | |
334 | val |= 1 << 17; | |
335 | break; | |
336 | case OMAP_DMA_COLOR_DIS: | |
337 | break; | |
338 | default: | |
339 | BUG(); | |
340 | } | |
f31cc962 | 341 | p->dma_write(val, CCR, lch); |
0815f8ea TV |
342 | |
343 | color &= 0xffffff; | |
f31cc962 | 344 | p->dma_write(color, COLOR, lch); |
5e1c5ff4 | 345 | } |
5e1c5ff4 | 346 | } |
97b7f715 | 347 | EXPORT_SYMBOL(omap_set_dma_color_mode); |
5e1c5ff4 | 348 | |
709eb3e5 TL |
349 | void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) |
350 | { | |
f8151e5c | 351 | if (cpu_class_is_omap2()) { |
0499bdeb TL |
352 | u32 csdp; |
353 | ||
f31cc962 | 354 | csdp = p->dma_read(CSDP, lch); |
0499bdeb TL |
355 | csdp &= ~(0x3 << 16); |
356 | csdp |= (mode << 16); | |
f31cc962 | 357 | p->dma_write(csdp, CSDP, lch); |
709eb3e5 TL |
358 | } |
359 | } | |
97b7f715 | 360 | EXPORT_SYMBOL(omap_set_dma_write_mode); |
709eb3e5 | 361 | |
0499bdeb TL |
362 | void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode) |
363 | { | |
364 | if (cpu_class_is_omap1() && !cpu_is_omap15xx()) { | |
365 | u32 l; | |
366 | ||
f31cc962 | 367 | l = p->dma_read(LCH_CTRL, lch); |
0499bdeb TL |
368 | l &= ~0x7; |
369 | l |= mode; | |
f31cc962 | 370 | p->dma_write(l, LCH_CTRL, lch); |
0499bdeb TL |
371 | } |
372 | } | |
373 | EXPORT_SYMBOL(omap_set_dma_channel_mode); | |
374 | ||
1a8bfa1e | 375 | /* Note that src_port is only for omap1 */ |
5e1c5ff4 | 376 | void omap_set_dma_src_params(int lch, int src_port, int src_amode, |
1a8bfa1e TL |
377 | unsigned long src_start, |
378 | int src_ei, int src_fi) | |
5e1c5ff4 | 379 | { |
97b7f715 TL |
380 | u32 l; |
381 | ||
1a8bfa1e | 382 | if (cpu_class_is_omap1()) { |
0499bdeb | 383 | u16 w; |
1a8bfa1e | 384 | |
f31cc962 | 385 | w = p->dma_read(CSDP, lch); |
0499bdeb TL |
386 | w &= ~(0x1f << 2); |
387 | w |= src_port << 2; | |
f31cc962 | 388 | p->dma_write(w, CSDP, lch); |
97b7f715 | 389 | } |
1a8bfa1e | 390 | |
f31cc962 | 391 | l = p->dma_read(CCR, lch); |
97b7f715 TL |
392 | l &= ~(0x03 << 12); |
393 | l |= src_amode << 12; | |
f31cc962 | 394 | p->dma_write(l, CCR, lch); |
0499bdeb | 395 | |
f31cc962 | 396 | p->dma_write(src_start, CSSA, lch); |
5e1c5ff4 | 397 | |
f31cc962 MK |
398 | p->dma_write(src_ei, CSEI, lch); |
399 | p->dma_write(src_fi, CSFI, lch); | |
1a8bfa1e | 400 | } |
97b7f715 | 401 | EXPORT_SYMBOL(omap_set_dma_src_params); |
5e1c5ff4 | 402 | |
97b7f715 | 403 | void omap_set_dma_params(int lch, struct omap_dma_channel_params *params) |
1a8bfa1e TL |
404 | { |
405 | omap_set_dma_transfer_params(lch, params->data_type, | |
406 | params->elem_count, params->frame_count, | |
407 | params->sync_mode, params->trigger, | |
408 | params->src_or_dst_synch); | |
409 | omap_set_dma_src_params(lch, params->src_port, | |
410 | params->src_amode, params->src_start, | |
411 | params->src_ei, params->src_fi); | |
412 | ||
413 | omap_set_dma_dest_params(lch, params->dst_port, | |
414 | params->dst_amode, params->dst_start, | |
415 | params->dst_ei, params->dst_fi); | |
f8151e5c AG |
416 | if (params->read_prio || params->write_prio) |
417 | omap_dma_set_prio_lch(lch, params->read_prio, | |
418 | params->write_prio); | |
5e1c5ff4 | 419 | } |
97b7f715 | 420 | EXPORT_SYMBOL(omap_set_dma_params); |
5e1c5ff4 TL |
421 | |
422 | void omap_set_dma_src_index(int lch, int eidx, int fidx) | |
423 | { | |
97b7f715 | 424 | if (cpu_class_is_omap2()) |
1a8bfa1e | 425 | return; |
97b7f715 | 426 | |
f31cc962 MK |
427 | p->dma_write(eidx, CSEI, lch); |
428 | p->dma_write(fidx, CSFI, lch); | |
5e1c5ff4 | 429 | } |
97b7f715 | 430 | EXPORT_SYMBOL(omap_set_dma_src_index); |
5e1c5ff4 TL |
431 | |
432 | void omap_set_dma_src_data_pack(int lch, int enable) | |
433 | { | |
0499bdeb TL |
434 | u32 l; |
435 | ||
f31cc962 | 436 | l = p->dma_read(CSDP, lch); |
0499bdeb | 437 | l &= ~(1 << 6); |
1a8bfa1e | 438 | if (enable) |
0499bdeb | 439 | l |= (1 << 6); |
f31cc962 | 440 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 441 | } |
97b7f715 | 442 | EXPORT_SYMBOL(omap_set_dma_src_data_pack); |
5e1c5ff4 TL |
443 | |
444 | void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) | |
445 | { | |
6dc3c8f2 | 446 | unsigned int burst = 0; |
0499bdeb TL |
447 | u32 l; |
448 | ||
f31cc962 | 449 | l = p->dma_read(CSDP, lch); |
0499bdeb | 450 | l &= ~(0x03 << 7); |
5e1c5ff4 | 451 | |
5e1c5ff4 TL |
452 | switch (burst_mode) { |
453 | case OMAP_DMA_DATA_BURST_DIS: | |
454 | break; | |
455 | case OMAP_DMA_DATA_BURST_4: | |
f8151e5c | 456 | if (cpu_class_is_omap2()) |
6dc3c8f2 KP |
457 | burst = 0x1; |
458 | else | |
459 | burst = 0x2; | |
5e1c5ff4 TL |
460 | break; |
461 | case OMAP_DMA_DATA_BURST_8: | |
f8151e5c | 462 | if (cpu_class_is_omap2()) { |
6dc3c8f2 KP |
463 | burst = 0x2; |
464 | break; | |
465 | } | |
ea221a6a | 466 | /* |
467 | * not supported by current hardware on OMAP1 | |
5e1c5ff4 TL |
468 | * w |= (0x03 << 7); |
469 | * fall through | |
470 | */ | |
6dc3c8f2 | 471 | case OMAP_DMA_DATA_BURST_16: |
f8151e5c | 472 | if (cpu_class_is_omap2()) { |
6dc3c8f2 KP |
473 | burst = 0x3; |
474 | break; | |
475 | } | |
ea221a6a | 476 | /* |
477 | * OMAP1 don't support burst 16 | |
6dc3c8f2 KP |
478 | * fall through |
479 | */ | |
5e1c5ff4 TL |
480 | default: |
481 | BUG(); | |
482 | } | |
0499bdeb TL |
483 | |
484 | l |= (burst << 7); | |
f31cc962 | 485 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 486 | } |
97b7f715 | 487 | EXPORT_SYMBOL(omap_set_dma_src_burst_mode); |
5e1c5ff4 | 488 | |
1a8bfa1e | 489 | /* Note that dest_port is only for OMAP1 */ |
5e1c5ff4 | 490 | void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, |
1a8bfa1e TL |
491 | unsigned long dest_start, |
492 | int dst_ei, int dst_fi) | |
5e1c5ff4 | 493 | { |
0499bdeb TL |
494 | u32 l; |
495 | ||
1a8bfa1e | 496 | if (cpu_class_is_omap1()) { |
f31cc962 | 497 | l = p->dma_read(CSDP, lch); |
0499bdeb TL |
498 | l &= ~(0x1f << 9); |
499 | l |= dest_port << 9; | |
f31cc962 | 500 | p->dma_write(l, CSDP, lch); |
1a8bfa1e | 501 | } |
5e1c5ff4 | 502 | |
f31cc962 | 503 | l = p->dma_read(CCR, lch); |
0499bdeb TL |
504 | l &= ~(0x03 << 14); |
505 | l |= dest_amode << 14; | |
f31cc962 | 506 | p->dma_write(l, CCR, lch); |
5e1c5ff4 | 507 | |
f31cc962 | 508 | p->dma_write(dest_start, CDSA, lch); |
5e1c5ff4 | 509 | |
f31cc962 MK |
510 | p->dma_write(dst_ei, CDEI, lch); |
511 | p->dma_write(dst_fi, CDFI, lch); | |
5e1c5ff4 | 512 | } |
97b7f715 | 513 | EXPORT_SYMBOL(omap_set_dma_dest_params); |
5e1c5ff4 TL |
514 | |
515 | void omap_set_dma_dest_index(int lch, int eidx, int fidx) | |
516 | { | |
97b7f715 | 517 | if (cpu_class_is_omap2()) |
1a8bfa1e | 518 | return; |
97b7f715 | 519 | |
f31cc962 MK |
520 | p->dma_write(eidx, CDEI, lch); |
521 | p->dma_write(fidx, CDFI, lch); | |
5e1c5ff4 | 522 | } |
97b7f715 | 523 | EXPORT_SYMBOL(omap_set_dma_dest_index); |
5e1c5ff4 TL |
524 | |
525 | void omap_set_dma_dest_data_pack(int lch, int enable) | |
526 | { | |
0499bdeb TL |
527 | u32 l; |
528 | ||
f31cc962 | 529 | l = p->dma_read(CSDP, lch); |
0499bdeb | 530 | l &= ~(1 << 13); |
1a8bfa1e | 531 | if (enable) |
0499bdeb | 532 | l |= 1 << 13; |
f31cc962 | 533 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 534 | } |
97b7f715 | 535 | EXPORT_SYMBOL(omap_set_dma_dest_data_pack); |
5e1c5ff4 TL |
536 | |
537 | void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) | |
538 | { | |
6dc3c8f2 | 539 | unsigned int burst = 0; |
0499bdeb TL |
540 | u32 l; |
541 | ||
f31cc962 | 542 | l = p->dma_read(CSDP, lch); |
0499bdeb | 543 | l &= ~(0x03 << 14); |
5e1c5ff4 | 544 | |
5e1c5ff4 TL |
545 | switch (burst_mode) { |
546 | case OMAP_DMA_DATA_BURST_DIS: | |
547 | break; | |
548 | case OMAP_DMA_DATA_BURST_4: | |
f8151e5c | 549 | if (cpu_class_is_omap2()) |
6dc3c8f2 KP |
550 | burst = 0x1; |
551 | else | |
552 | burst = 0x2; | |
5e1c5ff4 TL |
553 | break; |
554 | case OMAP_DMA_DATA_BURST_8: | |
f8151e5c | 555 | if (cpu_class_is_omap2()) |
6dc3c8f2 KP |
556 | burst = 0x2; |
557 | else | |
558 | burst = 0x3; | |
5e1c5ff4 | 559 | break; |
6dc3c8f2 | 560 | case OMAP_DMA_DATA_BURST_16: |
f8151e5c | 561 | if (cpu_class_is_omap2()) { |
6dc3c8f2 KP |
562 | burst = 0x3; |
563 | break; | |
564 | } | |
ea221a6a | 565 | /* |
566 | * OMAP1 don't support burst 16 | |
6dc3c8f2 KP |
567 | * fall through |
568 | */ | |
5e1c5ff4 TL |
569 | default: |
570 | printk(KERN_ERR "Invalid DMA burst mode\n"); | |
571 | BUG(); | |
572 | return; | |
573 | } | |
0499bdeb | 574 | l |= (burst << 14); |
f31cc962 | 575 | p->dma_write(l, CSDP, lch); |
5e1c5ff4 | 576 | } |
97b7f715 | 577 | EXPORT_SYMBOL(omap_set_dma_dest_burst_mode); |
5e1c5ff4 | 578 | |
1a8bfa1e | 579 | static inline void omap_enable_channel_irq(int lch) |
5e1c5ff4 | 580 | { |
7ff879db TL |
581 | /* Clear CSR */ |
582 | if (cpu_class_is_omap1()) | |
bedfb7ad OM |
583 | p->dma_read(CSR, lch); |
584 | else | |
f31cc962 | 585 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); |
1a8bfa1e | 586 | |
5e1c5ff4 | 587 | /* Enable some nice interrupts. */ |
f31cc962 | 588 | p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch); |
5e1c5ff4 TL |
589 | } |
590 | ||
bedfb7ad | 591 | static inline void omap_disable_channel_irq(int lch) |
5e1c5ff4 | 592 | { |
bedfb7ad OM |
593 | /* disable channel interrupts */ |
594 | p->dma_write(0, CICR, lch); | |
595 | /* Clear CSR */ | |
596 | if (cpu_class_is_omap1()) | |
597 | p->dma_read(CSR, lch); | |
598 | else | |
599 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); | |
1a8bfa1e TL |
600 | } |
601 | ||
602 | void omap_enable_dma_irq(int lch, u16 bits) | |
603 | { | |
604 | dma_chan[lch].enabled_irqs |= bits; | |
605 | } | |
97b7f715 | 606 | EXPORT_SYMBOL(omap_enable_dma_irq); |
5e1c5ff4 | 607 | |
1a8bfa1e TL |
608 | void omap_disable_dma_irq(int lch, u16 bits) |
609 | { | |
610 | dma_chan[lch].enabled_irqs &= ~bits; | |
611 | } | |
97b7f715 | 612 | EXPORT_SYMBOL(omap_disable_dma_irq); |
1a8bfa1e TL |
613 | |
614 | static inline void enable_lnk(int lch) | |
615 | { | |
0499bdeb TL |
616 | u32 l; |
617 | ||
f31cc962 | 618 | l = p->dma_read(CLNK_CTRL, lch); |
0499bdeb | 619 | |
1a8bfa1e | 620 | if (cpu_class_is_omap1()) |
0499bdeb | 621 | l &= ~(1 << 14); |
5e1c5ff4 | 622 | |
1a8bfa1e | 623 | /* Set the ENABLE_LNK bits */ |
5e1c5ff4 | 624 | if (dma_chan[lch].next_lch != -1) |
0499bdeb | 625 | l = dma_chan[lch].next_lch | (1 << 15); |
f8151e5c AG |
626 | |
627 | #ifndef CONFIG_ARCH_OMAP1 | |
97b7f715 TL |
628 | if (cpu_class_is_omap2()) |
629 | if (dma_chan[lch].next_linked_ch != -1) | |
630 | l = dma_chan[lch].next_linked_ch | (1 << 15); | |
f8151e5c | 631 | #endif |
0499bdeb | 632 | |
f31cc962 | 633 | p->dma_write(l, CLNK_CTRL, lch); |
5e1c5ff4 TL |
634 | } |
635 | ||
636 | static inline void disable_lnk(int lch) | |
637 | { | |
0499bdeb TL |
638 | u32 l; |
639 | ||
f31cc962 | 640 | l = p->dma_read(CLNK_CTRL, lch); |
0499bdeb | 641 | |
5e1c5ff4 | 642 | /* Disable interrupts */ |
bedfb7ad OM |
643 | omap_disable_channel_irq(lch); |
644 | ||
1a8bfa1e | 645 | if (cpu_class_is_omap1()) { |
1a8bfa1e | 646 | /* Set the STOP_LNK bit */ |
0499bdeb | 647 | l |= 1 << 14; |
1a8bfa1e | 648 | } |
5e1c5ff4 | 649 | |
f8151e5c | 650 | if (cpu_class_is_omap2()) { |
1a8bfa1e | 651 | /* Clear the ENABLE_LNK bit */ |
0499bdeb | 652 | l &= ~(1 << 15); |
1a8bfa1e | 653 | } |
5e1c5ff4 | 654 | |
f31cc962 | 655 | p->dma_write(l, CLNK_CTRL, lch); |
5e1c5ff4 TL |
656 | dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; |
657 | } | |
658 | ||
1a8bfa1e | 659 | static inline void omap2_enable_irq_lch(int lch) |
5e1c5ff4 | 660 | { |
1a8bfa1e | 661 | u32 val; |
ee907324 | 662 | unsigned long flags; |
1a8bfa1e | 663 | |
f8151e5c | 664 | if (!cpu_class_is_omap2()) |
1a8bfa1e TL |
665 | return; |
666 | ||
ee907324 | 667 | spin_lock_irqsave(&dma_chan_lock, flags); |
bedfb7ad OM |
668 | /* clear IRQ STATUS */ |
669 | p->dma_write(1 << lch, IRQSTATUS_L0, lch); | |
670 | /* Enable interrupt */ | |
f31cc962 | 671 | val = p->dma_read(IRQENABLE_L0, lch); |
1a8bfa1e | 672 | val |= 1 << lch; |
f31cc962 | 673 | p->dma_write(val, IRQENABLE_L0, lch); |
ee907324 | 674 | spin_unlock_irqrestore(&dma_chan_lock, flags); |
1a8bfa1e TL |
675 | } |
676 | ||
ada8d4a5 MW |
677 | static inline void omap2_disable_irq_lch(int lch) |
678 | { | |
679 | u32 val; | |
680 | unsigned long flags; | |
681 | ||
682 | if (!cpu_class_is_omap2()) | |
683 | return; | |
684 | ||
685 | spin_lock_irqsave(&dma_chan_lock, flags); | |
bedfb7ad | 686 | /* Disable interrupt */ |
f31cc962 | 687 | val = p->dma_read(IRQENABLE_L0, lch); |
ada8d4a5 | 688 | val &= ~(1 << lch); |
f31cc962 | 689 | p->dma_write(val, IRQENABLE_L0, lch); |
bedfb7ad OM |
690 | /* clear IRQ STATUS */ |
691 | p->dma_write(1 << lch, IRQSTATUS_L0, lch); | |
ada8d4a5 MW |
692 | spin_unlock_irqrestore(&dma_chan_lock, flags); |
693 | } | |
694 | ||
1a8bfa1e | 695 | int omap_request_dma(int dev_id, const char *dev_name, |
97b7f715 | 696 | void (*callback)(int lch, u16 ch_status, void *data), |
1a8bfa1e TL |
697 | void *data, int *dma_ch_out) |
698 | { | |
699 | int ch, free_ch = -1; | |
700 | unsigned long flags; | |
701 | struct omap_dma_lch *chan; | |
702 | ||
703 | spin_lock_irqsave(&dma_chan_lock, flags); | |
704 | for (ch = 0; ch < dma_chan_count; ch++) { | |
705 | if (free_ch == -1 && dma_chan[ch].dev_id == -1) { | |
706 | free_ch = ch; | |
707 | if (dev_id == 0) | |
708 | break; | |
709 | } | |
710 | } | |
711 | if (free_ch == -1) { | |
712 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
713 | return -EBUSY; | |
714 | } | |
715 | chan = dma_chan + free_ch; | |
716 | chan->dev_id = dev_id; | |
717 | ||
f31cc962 MK |
718 | if (p->clear_lch_regs) |
719 | p->clear_lch_regs(free_ch); | |
5e1c5ff4 | 720 | |
f8151e5c | 721 | if (cpu_class_is_omap2()) |
1a8bfa1e TL |
722 | omap_clear_dma(free_ch); |
723 | ||
724 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
725 | ||
726 | chan->dev_name = dev_name; | |
727 | chan->callback = callback; | |
728 | chan->data = data; | |
a92fda19 | 729 | chan->flags = 0; |
97b7f715 | 730 | |
f8151e5c | 731 | #ifndef CONFIG_ARCH_OMAP1 |
97b7f715 TL |
732 | if (cpu_class_is_omap2()) { |
733 | chan->chain_id = -1; | |
734 | chan->next_linked_ch = -1; | |
735 | } | |
f8151e5c | 736 | #endif |
97b7f715 | 737 | |
7ff879db | 738 | chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; |
1a8bfa1e | 739 | |
7ff879db TL |
740 | if (cpu_class_is_omap1()) |
741 | chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ; | |
f8151e5c | 742 | else if (cpu_class_is_omap2()) |
7ff879db TL |
743 | chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ | |
744 | OMAP2_DMA_TRANS_ERR_IRQ; | |
1a8bfa1e TL |
745 | |
746 | if (cpu_is_omap16xx()) { | |
747 | /* If the sync device is set, configure it dynamically. */ | |
748 | if (dev_id != 0) { | |
749 | set_gdma_dev(free_ch + 1, dev_id); | |
750 | dev_id = free_ch + 1; | |
751 | } | |
97b7f715 TL |
752 | /* |
753 | * Disable the 1510 compatibility mode and set the sync device | |
754 | * id. | |
755 | */ | |
f31cc962 | 756 | p->dma_write(dev_id | (1 << 10), CCR, free_ch); |
557096fe | 757 | } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) { |
f31cc962 | 758 | p->dma_write(dev_id, CCR, free_ch); |
1a8bfa1e TL |
759 | } |
760 | ||
f8151e5c | 761 | if (cpu_class_is_omap2()) { |
1a8bfa1e | 762 | omap_enable_channel_irq(free_ch); |
bedfb7ad | 763 | omap2_enable_irq_lch(free_ch); |
1a8bfa1e TL |
764 | } |
765 | ||
766 | *dma_ch_out = free_ch; | |
767 | ||
768 | return 0; | |
769 | } | |
97b7f715 | 770 | EXPORT_SYMBOL(omap_request_dma); |
1a8bfa1e TL |
771 | |
772 | void omap_free_dma(int lch) | |
773 | { | |
774 | unsigned long flags; | |
775 | ||
1a8bfa1e | 776 | if (dma_chan[lch].dev_id == -1) { |
97b7f715 | 777 | pr_err("omap_dma: trying to free unallocated DMA channel %d\n", |
1a8bfa1e | 778 | lch); |
1a8bfa1e TL |
779 | return; |
780 | } | |
97b7f715 | 781 | |
bedfb7ad OM |
782 | /* Disable interrupt for logical channel */ |
783 | if (cpu_class_is_omap2()) | |
ada8d4a5 | 784 | omap2_disable_irq_lch(lch); |
1a8bfa1e | 785 | |
bedfb7ad OM |
786 | /* Disable all DMA interrupts for the channel. */ |
787 | omap_disable_channel_irq(lch); | |
1a8bfa1e | 788 | |
bedfb7ad OM |
789 | /* Make sure the DMA transfer is stopped. */ |
790 | p->dma_write(0, CCR, lch); | |
1a8bfa1e | 791 | |
bedfb7ad OM |
792 | /* Clear registers */ |
793 | if (cpu_class_is_omap2()) | |
1a8bfa1e | 794 | omap_clear_dma(lch); |
da1b94e6 SS |
795 | |
796 | spin_lock_irqsave(&dma_chan_lock, flags); | |
797 | dma_chan[lch].dev_id = -1; | |
798 | dma_chan[lch].next_lch = -1; | |
799 | dma_chan[lch].callback = NULL; | |
800 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
1a8bfa1e | 801 | } |
97b7f715 | 802 | EXPORT_SYMBOL(omap_free_dma); |
1a8bfa1e | 803 | |
f8151e5c AG |
804 | /** |
805 | * @brief omap_dma_set_global_params : Set global priority settings for dma | |
806 | * | |
807 | * @param arb_rate | |
808 | * @param max_fifo_depth | |
70cf644c AA |
809 | * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM |
810 | * DMA_THREAD_RESERVE_ONET | |
811 | * DMA_THREAD_RESERVE_TWOT | |
812 | * DMA_THREAD_RESERVE_THREET | |
f8151e5c AG |
813 | */ |
814 | void | |
815 | omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams) | |
816 | { | |
817 | u32 reg; | |
818 | ||
819 | if (!cpu_class_is_omap2()) { | |
8e86f427 | 820 | printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__); |
f8151e5c AG |
821 | return; |
822 | } | |
823 | ||
70cf644c AA |
824 | if (max_fifo_depth == 0) |
825 | max_fifo_depth = 1; | |
f8151e5c AG |
826 | if (arb_rate == 0) |
827 | arb_rate = 1; | |
828 | ||
70cf644c AA |
829 | reg = 0xff & max_fifo_depth; |
830 | reg |= (0x3 & tparams) << 12; | |
831 | reg |= (arb_rate & 0xff) << 16; | |
f8151e5c | 832 | |
f31cc962 | 833 | p->dma_write(reg, GCR, 0); |
f8151e5c AG |
834 | } |
835 | EXPORT_SYMBOL(omap_dma_set_global_params); | |
836 | ||
837 | /** | |
838 | * @brief omap_dma_set_prio_lch : Set channel wise priority settings | |
839 | * | |
840 | * @param lch | |
841 | * @param read_prio - Read priority | |
842 | * @param write_prio - Write priority | |
843 | * Both of the above can be set with one of the following values : | |
844 | * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW | |
845 | */ | |
846 | int | |
847 | omap_dma_set_prio_lch(int lch, unsigned char read_prio, | |
848 | unsigned char write_prio) | |
849 | { | |
0499bdeb | 850 | u32 l; |
f8151e5c | 851 | |
4d96372e | 852 | if (unlikely((lch < 0 || lch >= dma_lch_count))) { |
f8151e5c AG |
853 | printk(KERN_ERR "Invalid channel id\n"); |
854 | return -EINVAL; | |
855 | } | |
f31cc962 | 856 | l = p->dma_read(CCR, lch); |
0499bdeb | 857 | l &= ~((1 << 6) | (1 << 26)); |
d07c3df8 | 858 | if (cpu_class_is_omap2() && !cpu_is_omap242x()) |
0499bdeb | 859 | l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); |
f8151e5c | 860 | else |
0499bdeb TL |
861 | l |= ((read_prio & 0x1) << 6); |
862 | ||
f31cc962 | 863 | p->dma_write(l, CCR, lch); |
f8151e5c | 864 | |
f8151e5c AG |
865 | return 0; |
866 | } | |
867 | EXPORT_SYMBOL(omap_dma_set_prio_lch); | |
868 | ||
1a8bfa1e TL |
869 | /* |
870 | * Clears any DMA state so the DMA engine is ready to restart with new buffers | |
871 | * through omap_start_dma(). Any buffers in flight are discarded. | |
872 | */ | |
873 | void omap_clear_dma(int lch) | |
874 | { | |
875 | unsigned long flags; | |
876 | ||
877 | local_irq_save(flags); | |
f31cc962 | 878 | p->clear_dma(lch); |
1a8bfa1e TL |
879 | local_irq_restore(flags); |
880 | } | |
97b7f715 | 881 | EXPORT_SYMBOL(omap_clear_dma); |
1a8bfa1e TL |
882 | |
883 | void omap_start_dma(int lch) | |
884 | { | |
0499bdeb TL |
885 | u32 l; |
886 | ||
519e6166 | 887 | /* |
888 | * The CPC/CDAC register needs to be initialized to zero | |
889 | * before starting dma transfer. | |
890 | */ | |
891 | if (cpu_is_omap15xx()) | |
f31cc962 | 892 | p->dma_write(0, CPC, lch); |
519e6166 | 893 | else |
f31cc962 | 894 | p->dma_write(0, CDAC, lch); |
519e6166 | 895 | |
5e1c5ff4 TL |
896 | if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { |
897 | int next_lch, cur_lch; | |
bc4d8b5f | 898 | char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT]; |
5e1c5ff4 TL |
899 | |
900 | dma_chan_link_map[lch] = 1; | |
901 | /* Set the link register of the first channel */ | |
902 | enable_lnk(lch); | |
903 | ||
904 | memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); | |
905 | cur_lch = dma_chan[lch].next_lch; | |
906 | do { | |
907 | next_lch = dma_chan[cur_lch].next_lch; | |
908 | ||
1a8bfa1e | 909 | /* The loop case: we've been here already */ |
5e1c5ff4 TL |
910 | if (dma_chan_link_map[cur_lch]) |
911 | break; | |
912 | /* Mark the current channel */ | |
913 | dma_chan_link_map[cur_lch] = 1; | |
914 | ||
915 | enable_lnk(cur_lch); | |
1a8bfa1e | 916 | omap_enable_channel_irq(cur_lch); |
5e1c5ff4 TL |
917 | |
918 | cur_lch = next_lch; | |
919 | } while (next_lch != -1); | |
d3c9be2f | 920 | } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS)) |
f31cc962 | 921 | p->dma_write(lch, CLNK_CTRL, lch); |
5e1c5ff4 | 922 | |
1a8bfa1e TL |
923 | omap_enable_channel_irq(lch); |
924 | ||
f31cc962 | 925 | l = p->dma_read(CCR, lch); |
0499bdeb | 926 | |
d3c9be2f MK |
927 | if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING)) |
928 | l |= OMAP_DMA_CCR_BUFFERING_DISABLE; | |
0499bdeb | 929 | l |= OMAP_DMA_CCR_EN; |
d3c9be2f | 930 | |
35453584 RK |
931 | /* |
932 | * As dma_write() uses IO accessors which are weakly ordered, there | |
933 | * is no guarantee that data in coherent DMA memory will be visible | |
934 | * to the DMA device. Add a memory barrier here to ensure that any | |
935 | * such data is visible prior to enabling DMA. | |
936 | */ | |
937 | mb(); | |
f31cc962 | 938 | p->dma_write(l, CCR, lch); |
5e1c5ff4 | 939 | |
5e1c5ff4 TL |
940 | dma_chan[lch].flags |= OMAP_DMA_ACTIVE; |
941 | } | |
97b7f715 | 942 | EXPORT_SYMBOL(omap_start_dma); |
5e1c5ff4 TL |
943 | |
944 | void omap_stop_dma(int lch) | |
945 | { | |
0499bdeb TL |
946 | u32 l; |
947 | ||
9da65a99 | 948 | /* Disable all interrupts on the channel */ |
bedfb7ad | 949 | omap_disable_channel_irq(lch); |
9da65a99 | 950 | |
f31cc962 | 951 | l = p->dma_read(CCR, lch); |
d3c9be2f MK |
952 | if (IS_DMA_ERRATA(DMA_ERRATA_i541) && |
953 | (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) { | |
0e4905c0 PU |
954 | int i = 0; |
955 | u32 sys_cf; | |
956 | ||
957 | /* Configure No-Standby */ | |
f31cc962 | 958 | l = p->dma_read(OCP_SYSCONFIG, lch); |
0e4905c0 PU |
959 | sys_cf = l; |
960 | l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK; | |
961 | l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE); | |
f31cc962 | 962 | p->dma_write(l , OCP_SYSCONFIG, 0); |
0e4905c0 | 963 | |
f31cc962 | 964 | l = p->dma_read(CCR, lch); |
0e4905c0 | 965 | l &= ~OMAP_DMA_CCR_EN; |
f31cc962 | 966 | p->dma_write(l, CCR, lch); |
0e4905c0 PU |
967 | |
968 | /* Wait for sDMA FIFO drain */ | |
f31cc962 | 969 | l = p->dma_read(CCR, lch); |
0e4905c0 PU |
970 | while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE | |
971 | OMAP_DMA_CCR_WR_ACTIVE))) { | |
972 | udelay(5); | |
973 | i++; | |
f31cc962 | 974 | l = p->dma_read(CCR, lch); |
0e4905c0 PU |
975 | } |
976 | if (i >= 100) | |
7852ec05 | 977 | pr_err("DMA drain did not complete on lch %d\n", lch); |
0e4905c0 | 978 | /* Restore OCP_SYSCONFIG */ |
f31cc962 | 979 | p->dma_write(sys_cf, OCP_SYSCONFIG, lch); |
0e4905c0 PU |
980 | } else { |
981 | l &= ~OMAP_DMA_CCR_EN; | |
f31cc962 | 982 | p->dma_write(l, CCR, lch); |
0e4905c0 | 983 | } |
9da65a99 | 984 | |
35453584 RK |
985 | /* |
986 | * Ensure that data transferred by DMA is visible to any access | |
987 | * after DMA has been disabled. This is important for coherent | |
988 | * DMA regions. | |
989 | */ | |
990 | mb(); | |
991 | ||
5e1c5ff4 TL |
992 | if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { |
993 | int next_lch, cur_lch = lch; | |
bc4d8b5f | 994 | char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT]; |
5e1c5ff4 TL |
995 | |
996 | memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); | |
997 | do { | |
998 | /* The loop case: we've been here already */ | |
999 | if (dma_chan_link_map[cur_lch]) | |
1000 | break; | |
1001 | /* Mark the current channel */ | |
1002 | dma_chan_link_map[cur_lch] = 1; | |
1003 | ||
1004 | disable_lnk(cur_lch); | |
1005 | ||
1006 | next_lch = dma_chan[cur_lch].next_lch; | |
1007 | cur_lch = next_lch; | |
1008 | } while (next_lch != -1); | |
5e1c5ff4 | 1009 | } |
1a8bfa1e | 1010 | |
5e1c5ff4 TL |
1011 | dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; |
1012 | } | |
97b7f715 | 1013 | EXPORT_SYMBOL(omap_stop_dma); |
5e1c5ff4 | 1014 | |
709eb3e5 TL |
1015 | /* |
1016 | * Allows changing the DMA callback function or data. This may be needed if | |
1017 | * the driver shares a single DMA channel for multiple dma triggers. | |
1018 | */ | |
1019 | int omap_set_dma_callback(int lch, | |
97b7f715 | 1020 | void (*callback)(int lch, u16 ch_status, void *data), |
709eb3e5 TL |
1021 | void *data) |
1022 | { | |
1023 | unsigned long flags; | |
1024 | ||
1025 | if (lch < 0) | |
1026 | return -ENODEV; | |
1027 | ||
1028 | spin_lock_irqsave(&dma_chan_lock, flags); | |
1029 | if (dma_chan[lch].dev_id == -1) { | |
1030 | printk(KERN_ERR "DMA callback for not set for free channel\n"); | |
1031 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
1032 | return -EINVAL; | |
1033 | } | |
1034 | dma_chan[lch].callback = callback; | |
1035 | dma_chan[lch].data = data; | |
1036 | spin_unlock_irqrestore(&dma_chan_lock, flags); | |
1037 | ||
1038 | return 0; | |
1039 | } | |
97b7f715 | 1040 | EXPORT_SYMBOL(omap_set_dma_callback); |
709eb3e5 | 1041 | |
1a8bfa1e TL |
1042 | /* |
1043 | * Returns current physical source address for the given DMA channel. | |
1044 | * If the channel is running the caller must disable interrupts prior calling | |
1045 | * this function and process the returned value before re-enabling interrupt to | |
1046 | * prevent races with the interrupt handler. Note that in continuous mode there | |
25985edc | 1047 | * is a chance for CSSA_L register overflow between the two reads resulting |
1a8bfa1e TL |
1048 | * in incorrect return value. |
1049 | */ | |
1050 | dma_addr_t omap_get_dma_src_pos(int lch) | |
5e1c5ff4 | 1051 | { |
0695de32 | 1052 | dma_addr_t offset = 0; |
5e1c5ff4 | 1053 | |
0499bdeb | 1054 | if (cpu_is_omap15xx()) |
f31cc962 | 1055 | offset = p->dma_read(CPC, lch); |
0499bdeb | 1056 | else |
f31cc962 | 1057 | offset = p->dma_read(CSAC, lch); |
5e1c5ff4 | 1058 | |
d3c9be2f | 1059 | if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0) |
f31cc962 | 1060 | offset = p->dma_read(CSAC, lch); |
0499bdeb | 1061 | |
7ba96680 PU |
1062 | if (!cpu_is_omap15xx()) { |
1063 | /* | |
1064 | * CDAC == 0 indicates that the DMA transfer on the channel has | |
1065 | * not been started (no data has been transferred so far). | |
1066 | * Return the programmed source start address in this case. | |
1067 | */ | |
1068 | if (likely(p->dma_read(CDAC, lch))) | |
1069 | offset = p->dma_read(CSAC, lch); | |
1070 | else | |
1071 | offset = p->dma_read(CSSA, lch); | |
1072 | } | |
1073 | ||
0499bdeb | 1074 | if (cpu_class_is_omap1()) |
f31cc962 | 1075 | offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000); |
5e1c5ff4 | 1076 | |
1a8bfa1e | 1077 | return offset; |
5e1c5ff4 | 1078 | } |
97b7f715 | 1079 | EXPORT_SYMBOL(omap_get_dma_src_pos); |
5e1c5ff4 | 1080 | |
1a8bfa1e TL |
1081 | /* |
1082 | * Returns current physical destination address for the given DMA channel. | |
1083 | * If the channel is running the caller must disable interrupts prior calling | |
1084 | * this function and process the returned value before re-enabling interrupt to | |
1085 | * prevent races with the interrupt handler. Note that in continuous mode there | |
25985edc | 1086 | * is a chance for CDSA_L register overflow between the two reads resulting |
1a8bfa1e TL |
1087 | * in incorrect return value. |
1088 | */ | |
1089 | dma_addr_t omap_get_dma_dst_pos(int lch) | |
5e1c5ff4 | 1090 | { |
0695de32 | 1091 | dma_addr_t offset = 0; |
5e1c5ff4 | 1092 | |
0499bdeb | 1093 | if (cpu_is_omap15xx()) |
f31cc962 | 1094 | offset = p->dma_read(CPC, lch); |
0499bdeb | 1095 | else |
f31cc962 | 1096 | offset = p->dma_read(CDAC, lch); |
5e1c5ff4 | 1097 | |
0499bdeb TL |
1098 | /* |
1099 | * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is | |
1100 | * read before the DMA controller finished disabling the channel. | |
1101 | */ | |
06e8077b | 1102 | if (!cpu_is_omap15xx() && offset == 0) { |
f31cc962 | 1103 | offset = p->dma_read(CDAC, lch); |
06e8077b PU |
1104 | /* |
1105 | * CDAC == 0 indicates that the DMA transfer on the channel has | |
1106 | * not been started (no data has been transferred so far). | |
1107 | * Return the programmed destination start address in this case. | |
1108 | */ | |
1109 | if (unlikely(!offset)) | |
1110 | offset = p->dma_read(CDSA, lch); | |
1111 | } | |
0499bdeb TL |
1112 | |
1113 | if (cpu_class_is_omap1()) | |
f31cc962 | 1114 | offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000); |
5e1c5ff4 | 1115 | |
1a8bfa1e | 1116 | return offset; |
5e1c5ff4 | 1117 | } |
97b7f715 | 1118 | EXPORT_SYMBOL(omap_get_dma_dst_pos); |
0499bdeb TL |
1119 | |
1120 | int omap_get_dma_active_status(int lch) | |
1121 | { | |
f31cc962 | 1122 | return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0; |
5e1c5ff4 | 1123 | } |
0499bdeb | 1124 | EXPORT_SYMBOL(omap_get_dma_active_status); |
5e1c5ff4 | 1125 | |
1a8bfa1e | 1126 | int omap_dma_running(void) |
5e1c5ff4 | 1127 | { |
1a8bfa1e | 1128 | int lch; |
5e1c5ff4 | 1129 | |
f8e9e984 JK |
1130 | if (cpu_class_is_omap1()) |
1131 | if (omap_lcd_dma_running()) | |
1a8bfa1e | 1132 | return 1; |
5e1c5ff4 | 1133 | |
1a8bfa1e | 1134 | for (lch = 0; lch < dma_chan_count; lch++) |
f31cc962 | 1135 | if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) |
1a8bfa1e | 1136 | return 1; |
5e1c5ff4 | 1137 | |
1a8bfa1e | 1138 | return 0; |
5e1c5ff4 TL |
1139 | } |
1140 | ||
1141 | /* | |
1142 | * lch_queue DMA will start right after lch_head one is finished. | |
1143 | * For this DMA link to start, you still need to start (see omap_start_dma) | |
1144 | * the first one. That will fire up the entire queue. | |
1145 | */ | |
97b7f715 | 1146 | void omap_dma_link_lch(int lch_head, int lch_queue) |
5e1c5ff4 TL |
1147 | { |
1148 | if (omap_dma_in_1510_mode()) { | |
9f0f4ae5 | 1149 | if (lch_head == lch_queue) { |
f31cc962 | 1150 | p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8), |
a4c537c7 | 1151 | CCR, lch_head); |
9f0f4ae5 JK |
1152 | return; |
1153 | } | |
5e1c5ff4 TL |
1154 | printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); |
1155 | BUG(); | |
1156 | return; | |
1157 | } | |
1158 | ||
1159 | if ((dma_chan[lch_head].dev_id == -1) || | |
1160 | (dma_chan[lch_queue].dev_id == -1)) { | |
7852ec05 | 1161 | pr_err("omap_dma: trying to link non requested channels\n"); |
5e1c5ff4 TL |
1162 | dump_stack(); |
1163 | } | |
1164 | ||
1165 | dma_chan[lch_head].next_lch = lch_queue; | |
1166 | } | |
97b7f715 | 1167 | EXPORT_SYMBOL(omap_dma_link_lch); |
5e1c5ff4 TL |
1168 | |
1169 | /* | |
1170 | * Once the DMA queue is stopped, we can destroy it. | |
1171 | */ | |
97b7f715 | 1172 | void omap_dma_unlink_lch(int lch_head, int lch_queue) |
5e1c5ff4 TL |
1173 | { |
1174 | if (omap_dma_in_1510_mode()) { | |
9f0f4ae5 | 1175 | if (lch_head == lch_queue) { |
f31cc962 | 1176 | p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8), |
a4c537c7 | 1177 | CCR, lch_head); |
9f0f4ae5 JK |
1178 | return; |
1179 | } | |
5e1c5ff4 TL |
1180 | printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); |
1181 | BUG(); | |
1182 | return; | |
1183 | } | |
1184 | ||
1185 | if (dma_chan[lch_head].next_lch != lch_queue || | |
1186 | dma_chan[lch_head].next_lch == -1) { | |
7852ec05 | 1187 | pr_err("omap_dma: trying to unlink non linked channels\n"); |
5e1c5ff4 TL |
1188 | dump_stack(); |
1189 | } | |
1190 | ||
5e1c5ff4 | 1191 | if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) || |
247421fd | 1192 | (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) { |
7852ec05 | 1193 | pr_err("omap_dma: You need to stop the DMA channels before unlinking\n"); |
5e1c5ff4 TL |
1194 | dump_stack(); |
1195 | } | |
1196 | ||
1197 | dma_chan[lch_head].next_lch = -1; | |
1198 | } | |
97b7f715 TL |
1199 | EXPORT_SYMBOL(omap_dma_unlink_lch); |
1200 | ||
f8151e5c AG |
1201 | #ifndef CONFIG_ARCH_OMAP1 |
1202 | /* Create chain of DMA channesls */ | |
1203 | static void create_dma_lch_chain(int lch_head, int lch_queue) | |
1204 | { | |
0499bdeb | 1205 | u32 l; |
f8151e5c AG |
1206 | |
1207 | /* Check if this is the first link in chain */ | |
1208 | if (dma_chan[lch_head].next_linked_ch == -1) { | |
1209 | dma_chan[lch_head].next_linked_ch = lch_queue; | |
1210 | dma_chan[lch_head].prev_linked_ch = lch_queue; | |
1211 | dma_chan[lch_queue].next_linked_ch = lch_head; | |
1212 | dma_chan[lch_queue].prev_linked_ch = lch_head; | |
1213 | } | |
1214 | ||
1215 | /* a link exists, link the new channel in circular chain */ | |
1216 | else { | |
1217 | dma_chan[lch_queue].next_linked_ch = | |
1218 | dma_chan[lch_head].next_linked_ch; | |
1219 | dma_chan[lch_queue].prev_linked_ch = lch_head; | |
1220 | dma_chan[lch_head].next_linked_ch = lch_queue; | |
1221 | dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch = | |
1222 | lch_queue; | |
1223 | } | |
1224 | ||
f31cc962 | 1225 | l = p->dma_read(CLNK_CTRL, lch_head); |
0499bdeb TL |
1226 | l &= ~(0x1f); |
1227 | l |= lch_queue; | |
f31cc962 | 1228 | p->dma_write(l, CLNK_CTRL, lch_head); |
f8151e5c | 1229 | |
f31cc962 | 1230 | l = p->dma_read(CLNK_CTRL, lch_queue); |
0499bdeb TL |
1231 | l &= ~(0x1f); |
1232 | l |= (dma_chan[lch_queue].next_linked_ch); | |
f31cc962 | 1233 | p->dma_write(l, CLNK_CTRL, lch_queue); |
f8151e5c AG |
1234 | } |
1235 | ||
1236 | /** | |
1237 | * @brief omap_request_dma_chain : Request a chain of DMA channels | |
1238 | * | |
1239 | * @param dev_id - Device id using the dma channel | |
1240 | * @param dev_name - Device name | |
1241 | * @param callback - Call back function | |
1242 | * @chain_id - | |
1243 | * @no_of_chans - Number of channels requested | |
1244 | * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN | |
1245 | * OMAP_DMA_DYNAMIC_CHAIN | |
1246 | * @params - Channel parameters | |
1247 | * | |
af901ca1 | 1248 | * @return - Success : 0 |
f8151e5c AG |
1249 | * Failure: -EINVAL/-ENOMEM |
1250 | */ | |
1251 | int omap_request_dma_chain(int dev_id, const char *dev_name, | |
279b918d | 1252 | void (*callback) (int lch, u16 ch_status, |
f8151e5c AG |
1253 | void *data), |
1254 | int *chain_id, int no_of_chans, int chain_mode, | |
1255 | struct omap_dma_channel_params params) | |
1256 | { | |
1257 | int *channels; | |
1258 | int i, err; | |
1259 | ||
1260 | /* Is the chain mode valid ? */ | |
1261 | if (chain_mode != OMAP_DMA_STATIC_CHAIN | |
1262 | && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) { | |
1263 | printk(KERN_ERR "Invalid chain mode requested\n"); | |
1264 | return -EINVAL; | |
1265 | } | |
1266 | ||
1267 | if (unlikely((no_of_chans < 1 | |
4d96372e | 1268 | || no_of_chans > dma_lch_count))) { |
f8151e5c AG |
1269 | printk(KERN_ERR "Invalid Number of channels requested\n"); |
1270 | return -EINVAL; | |
1271 | } | |
1272 | ||
ea221a6a | 1273 | /* |
1274 | * Allocate a queue to maintain the status of the channels | |
1275 | * in the chain | |
1276 | */ | |
f8151e5c AG |
1277 | channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL); |
1278 | if (channels == NULL) { | |
1279 | printk(KERN_ERR "omap_dma: No memory for channel queue\n"); | |
1280 | return -ENOMEM; | |
1281 | } | |
1282 | ||
1283 | /* request and reserve DMA channels for the chain */ | |
1284 | for (i = 0; i < no_of_chans; i++) { | |
1285 | err = omap_request_dma(dev_id, dev_name, | |
c0fc18c5 | 1286 | callback, NULL, &channels[i]); |
f8151e5c AG |
1287 | if (err < 0) { |
1288 | int j; | |
1289 | for (j = 0; j < i; j++) | |
1290 | omap_free_dma(channels[j]); | |
1291 | kfree(channels); | |
1292 | printk(KERN_ERR "omap_dma: Request failed %d\n", err); | |
1293 | return err; | |
1294 | } | |
f8151e5c AG |
1295 | dma_chan[channels[i]].prev_linked_ch = -1; |
1296 | dma_chan[channels[i]].state = DMA_CH_NOTSTARTED; | |
1297 | ||
1298 | /* | |
1299 | * Allowing client drivers to set common parameters now, | |
1300 | * so that later only relevant (src_start, dest_start | |
1301 | * and element count) can be set | |
1302 | */ | |
1303 | omap_set_dma_params(channels[i], ¶ms); | |
1304 | } | |
1305 | ||
1306 | *chain_id = channels[0]; | |
1307 | dma_linked_lch[*chain_id].linked_dmach_q = channels; | |
1308 | dma_linked_lch[*chain_id].chain_mode = chain_mode; | |
1309 | dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED; | |
1310 | dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans; | |
1311 | ||
1312 | for (i = 0; i < no_of_chans; i++) | |
1313 | dma_chan[channels[i]].chain_id = *chain_id; | |
1314 | ||
1315 | /* Reset the Queue pointers */ | |
1316 | OMAP_DMA_CHAIN_QINIT(*chain_id); | |
1317 | ||
1318 | /* Set up the chain */ | |
1319 | if (no_of_chans == 1) | |
1320 | create_dma_lch_chain(channels[0], channels[0]); | |
1321 | else { | |
1322 | for (i = 0; i < (no_of_chans - 1); i++) | |
1323 | create_dma_lch_chain(channels[i], channels[i + 1]); | |
1324 | } | |
97b7f715 | 1325 | |
f8151e5c AG |
1326 | return 0; |
1327 | } | |
1328 | EXPORT_SYMBOL(omap_request_dma_chain); | |
1329 | ||
1330 | /** | |
1331 | * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the | |
1332 | * params after setting it. Dont do this while dma is running!! | |
1333 | * | |
1334 | * @param chain_id - Chained logical channel id. | |
1335 | * @param params | |
1336 | * | |
1337 | * @return - Success : 0 | |
1338 | * Failure : -EINVAL | |
1339 | */ | |
1340 | int omap_modify_dma_chain_params(int chain_id, | |
1341 | struct omap_dma_channel_params params) | |
1342 | { | |
1343 | int *channels; | |
1344 | u32 i; | |
1345 | ||
1346 | /* Check for input params */ | |
1347 | if (unlikely((chain_id < 0 | |
4d96372e | 1348 | || chain_id >= dma_lch_count))) { |
f8151e5c AG |
1349 | printk(KERN_ERR "Invalid chain id\n"); |
1350 | return -EINVAL; | |
1351 | } | |
1352 | ||
1353 | /* Check if the chain exists */ | |
1354 | if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { | |
1355 | printk(KERN_ERR "Chain doesn't exists\n"); | |
1356 | return -EINVAL; | |
1357 | } | |
1358 | channels = dma_linked_lch[chain_id].linked_dmach_q; | |
1359 | ||
1360 | for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { | |
1361 | /* | |
1362 | * Allowing client drivers to set common parameters now, | |
1363 | * so that later only relevant (src_start, dest_start | |
1364 | * and element count) can be set | |
1365 | */ | |
1366 | omap_set_dma_params(channels[i], ¶ms); | |
1367 | } | |
97b7f715 | 1368 | |
f8151e5c AG |
1369 | return 0; |
1370 | } | |
1371 | EXPORT_SYMBOL(omap_modify_dma_chain_params); | |
1372 | ||
1373 | /** | |
1374 | * @brief omap_free_dma_chain - Free all the logical channels in a chain. | |
1375 | * | |
1376 | * @param chain_id | |
1377 | * | |
1378 | * @return - Success : 0 | |
1379 | * Failure : -EINVAL | |
1380 | */ | |
1381 | int omap_free_dma_chain(int chain_id) | |
1382 | { | |
1383 | int *channels; | |
1384 | u32 i; | |
1385 | ||
1386 | /* Check for input params */ | |
4d96372e | 1387 | if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { |
f8151e5c AG |
1388 | printk(KERN_ERR "Invalid chain id\n"); |
1389 | return -EINVAL; | |
1390 | } | |
1391 | ||
1392 | /* Check if the chain exists */ | |
1393 | if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { | |
1394 | printk(KERN_ERR "Chain doesn't exists\n"); | |
1395 | return -EINVAL; | |
1396 | } | |
1397 | ||
1398 | channels = dma_linked_lch[chain_id].linked_dmach_q; | |
1399 | for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { | |
1400 | dma_chan[channels[i]].next_linked_ch = -1; | |
1401 | dma_chan[channels[i]].prev_linked_ch = -1; | |
1402 | dma_chan[channels[i]].chain_id = -1; | |
1403 | dma_chan[channels[i]].state = DMA_CH_NOTSTARTED; | |
1404 | omap_free_dma(channels[i]); | |
1405 | } | |
1406 | ||
1407 | kfree(channels); | |
1408 | ||
1409 | dma_linked_lch[chain_id].linked_dmach_q = NULL; | |
1410 | dma_linked_lch[chain_id].chain_mode = -1; | |
1411 | dma_linked_lch[chain_id].chain_state = -1; | |
97b7f715 | 1412 | |
f8151e5c AG |
1413 | return (0); |
1414 | } | |
1415 | EXPORT_SYMBOL(omap_free_dma_chain); | |
1416 | ||
1417 | /** | |
1418 | * @brief omap_dma_chain_status - Check if the chain is in | |
1419 | * active / inactive state. | |
1420 | * @param chain_id | |
1421 | * | |
1422 | * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE | |
1423 | * Failure : -EINVAL | |
1424 | */ | |
1425 | int omap_dma_chain_status(int chain_id) | |
1426 | { | |
1427 | /* Check for input params */ | |
4d96372e | 1428 | if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { |
f8151e5c AG |
1429 | printk(KERN_ERR "Invalid chain id\n"); |
1430 | return -EINVAL; | |
1431 | } | |
1432 | ||
1433 | /* Check if the chain exists */ | |
1434 | if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { | |
1435 | printk(KERN_ERR "Chain doesn't exists\n"); | |
1436 | return -EINVAL; | |
1437 | } | |
1438 | pr_debug("CHAINID=%d, qcnt=%d\n", chain_id, | |
1439 | dma_linked_lch[chain_id].q_count); | |
1440 | ||
1441 | if (OMAP_DMA_CHAIN_QEMPTY(chain_id)) | |
1442 | return OMAP_DMA_CHAIN_INACTIVE; | |
97b7f715 | 1443 | |
f8151e5c AG |
1444 | return OMAP_DMA_CHAIN_ACTIVE; |
1445 | } | |
1446 | EXPORT_SYMBOL(omap_dma_chain_status); | |
1447 | ||
1448 | /** | |
1449 | * @brief omap_dma_chain_a_transfer - Get a free channel from a chain, | |
1450 | * set the params and start the transfer. | |
1451 | * | |
1452 | * @param chain_id | |
1453 | * @param src_start - buffer start address | |
1454 | * @param dest_start - Dest address | |
1455 | * @param elem_count | |
1456 | * @param frame_count | |
1457 | * @param callbk_data - channel callback parameter data. | |
1458 | * | |
f4b6a7ef | 1459 | * @return - Success : 0 |
f8151e5c AG |
1460 | * Failure: -EINVAL/-EBUSY |
1461 | */ | |
1462 | int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start, | |
1463 | int elem_count, int frame_count, void *callbk_data) | |
1464 | { | |
1465 | int *channels; | |
0499bdeb | 1466 | u32 l, lch; |
f8151e5c AG |
1467 | int start_dma = 0; |
1468 | ||
97b7f715 TL |
1469 | /* |
1470 | * if buffer size is less than 1 then there is | |
1471 | * no use of starting the chain | |
1472 | */ | |
f8151e5c AG |
1473 | if (elem_count < 1) { |
1474 | printk(KERN_ERR "Invalid buffer size\n"); | |
1475 | return -EINVAL; | |
1476 | } | |
1477 | ||
1478 | /* Check for input params */ | |
1479 | if (unlikely((chain_id < 0 | |
4d96372e | 1480 | || chain_id >= dma_lch_count))) { |
f8151e5c AG |
1481 | printk(KERN_ERR "Invalid chain id\n"); |
1482 | return -EINVAL; | |
1483 | } | |
1484 | ||
1485 | /* Check if the chain exists */ | |
1486 | if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { | |
1487 | printk(KERN_ERR "Chain doesn't exist\n"); | |
1488 | return -EINVAL; | |
1489 | } | |
1490 | ||
1491 | /* Check if all the channels in chain are in use */ | |
1492 | if (OMAP_DMA_CHAIN_QFULL(chain_id)) | |
1493 | return -EBUSY; | |
1494 | ||
1495 | /* Frame count may be negative in case of indexed transfers */ | |
1496 | channels = dma_linked_lch[chain_id].linked_dmach_q; | |
1497 | ||
1498 | /* Get a free channel */ | |
1499 | lch = channels[dma_linked_lch[chain_id].q_tail]; | |
1500 | ||
1501 | /* Store the callback data */ | |
1502 | dma_chan[lch].data = callbk_data; | |
1503 | ||
1504 | /* Increment the q_tail */ | |
1505 | OMAP_DMA_CHAIN_INCQTAIL(chain_id); | |
1506 | ||
1507 | /* Set the params to the free channel */ | |
1508 | if (src_start != 0) | |
f31cc962 | 1509 | p->dma_write(src_start, CSSA, lch); |
f8151e5c | 1510 | if (dest_start != 0) |
f31cc962 | 1511 | p->dma_write(dest_start, CDSA, lch); |
f8151e5c AG |
1512 | |
1513 | /* Write the buffer size */ | |
f31cc962 MK |
1514 | p->dma_write(elem_count, CEN, lch); |
1515 | p->dma_write(frame_count, CFN, lch); | |
f8151e5c | 1516 | |
97b7f715 TL |
1517 | /* |
1518 | * If the chain is dynamically linked, | |
1519 | * then we may have to start the chain if its not active | |
1520 | */ | |
f8151e5c AG |
1521 | if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) { |
1522 | ||
97b7f715 TL |
1523 | /* |
1524 | * In Dynamic chain, if the chain is not started, | |
1525 | * queue the channel | |
1526 | */ | |
f8151e5c AG |
1527 | if (dma_linked_lch[chain_id].chain_state == |
1528 | DMA_CHAIN_NOTSTARTED) { | |
1529 | /* Enable the link in previous channel */ | |
1530 | if (dma_chan[dma_chan[lch].prev_linked_ch].state == | |
1531 | DMA_CH_QUEUED) | |
1532 | enable_lnk(dma_chan[lch].prev_linked_ch); | |
1533 | dma_chan[lch].state = DMA_CH_QUEUED; | |
1534 | } | |
1535 | ||
97b7f715 TL |
1536 | /* |
1537 | * Chain is already started, make sure its active, | |
1538 | * if not then start the chain | |
1539 | */ | |
f8151e5c AG |
1540 | else { |
1541 | start_dma = 1; | |
1542 | ||
1543 | if (dma_chan[dma_chan[lch].prev_linked_ch].state == | |
1544 | DMA_CH_STARTED) { | |
1545 | enable_lnk(dma_chan[lch].prev_linked_ch); | |
1546 | dma_chan[lch].state = DMA_CH_QUEUED; | |
1547 | start_dma = 0; | |
f31cc962 | 1548 | if (0 == ((1 << 7) & p->dma_read( |
a4c537c7 | 1549 | CCR, dma_chan[lch].prev_linked_ch))) { |
f8151e5c AG |
1550 | disable_lnk(dma_chan[lch]. |
1551 | prev_linked_ch); | |
1552 | pr_debug("\n prev ch is stopped\n"); | |
1553 | start_dma = 1; | |
1554 | } | |
1555 | } | |
1556 | ||
1557 | else if (dma_chan[dma_chan[lch].prev_linked_ch].state | |
1558 | == DMA_CH_QUEUED) { | |
1559 | enable_lnk(dma_chan[lch].prev_linked_ch); | |
1560 | dma_chan[lch].state = DMA_CH_QUEUED; | |
1561 | start_dma = 0; | |
1562 | } | |
1563 | omap_enable_channel_irq(lch); | |
1564 | ||
f31cc962 | 1565 | l = p->dma_read(CCR, lch); |
f8151e5c | 1566 | |
0499bdeb TL |
1567 | if ((0 == (l & (1 << 24)))) |
1568 | l &= ~(1 << 25); | |
f8151e5c | 1569 | else |
0499bdeb | 1570 | l |= (1 << 25); |
f8151e5c | 1571 | if (start_dma == 1) { |
0499bdeb TL |
1572 | if (0 == (l & (1 << 7))) { |
1573 | l |= (1 << 7); | |
f8151e5c AG |
1574 | dma_chan[lch].state = DMA_CH_STARTED; |
1575 | pr_debug("starting %d\n", lch); | |
f31cc962 | 1576 | p->dma_write(l, CCR, lch); |
f8151e5c AG |
1577 | } else |
1578 | start_dma = 0; | |
1579 | } else { | |
0499bdeb | 1580 | if (0 == (l & (1 << 7))) |
f31cc962 | 1581 | p->dma_write(l, CCR, lch); |
f8151e5c AG |
1582 | } |
1583 | dma_chan[lch].flags |= OMAP_DMA_ACTIVE; | |
1584 | } | |
1585 | } | |
97b7f715 | 1586 | |
f4b6a7ef | 1587 | return 0; |
f8151e5c AG |
1588 | } |
1589 | EXPORT_SYMBOL(omap_dma_chain_a_transfer); | |
1590 | ||
1591 | /** | |
1592 | * @brief omap_start_dma_chain_transfers - Start the chain | |
1593 | * | |
1594 | * @param chain_id | |
1595 | * | |
1596 | * @return - Success : 0 | |
1597 | * Failure : -EINVAL/-EBUSY | |
1598 | */ | |
1599 | int omap_start_dma_chain_transfers(int chain_id) | |
1600 | { | |
1601 | int *channels; | |
0499bdeb | 1602 | u32 l, i; |
f8151e5c | 1603 | |
4d96372e | 1604 | if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { |
f8151e5c AG |
1605 | printk(KERN_ERR "Invalid chain id\n"); |
1606 | return -EINVAL; | |
1607 | } | |
1608 | ||
1609 | channels = dma_linked_lch[chain_id].linked_dmach_q; | |
1610 | ||
1611 | if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) { | |
1612 | printk(KERN_ERR "Chain is already started\n"); | |
1613 | return -EBUSY; | |
1614 | } | |
1615 | ||
1616 | if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) { | |
1617 | for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; | |
1618 | i++) { | |
1619 | enable_lnk(channels[i]); | |
1620 | omap_enable_channel_irq(channels[i]); | |
1621 | } | |
1622 | } else { | |
1623 | omap_enable_channel_irq(channels[0]); | |
1624 | } | |
1625 | ||
f31cc962 | 1626 | l = p->dma_read(CCR, channels[0]); |
0499bdeb | 1627 | l |= (1 << 7); |
f8151e5c AG |
1628 | dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED; |
1629 | dma_chan[channels[0]].state = DMA_CH_STARTED; | |
1630 | ||
0499bdeb TL |
1631 | if ((0 == (l & (1 << 24)))) |
1632 | l &= ~(1 << 25); | |
f8151e5c | 1633 | else |
0499bdeb | 1634 | l |= (1 << 25); |
f31cc962 | 1635 | p->dma_write(l, CCR, channels[0]); |
f8151e5c AG |
1636 | |
1637 | dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE; | |
97b7f715 | 1638 | |
f8151e5c AG |
1639 | return 0; |
1640 | } | |
1641 | EXPORT_SYMBOL(omap_start_dma_chain_transfers); | |
1642 | ||
1643 | /** | |
1644 | * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain. | |
1645 | * | |
1646 | * @param chain_id | |
1647 | * | |
1648 | * @return - Success : 0 | |
1649 | * Failure : EINVAL | |
1650 | */ | |
1651 | int omap_stop_dma_chain_transfers(int chain_id) | |
1652 | { | |
1653 | int *channels; | |
0499bdeb | 1654 | u32 l, i; |
d3c9be2f | 1655 | u32 sys_cf = 0; |
f8151e5c AG |
1656 | |
1657 | /* Check for input params */ | |
4d96372e | 1658 | if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { |
f8151e5c AG |
1659 | printk(KERN_ERR "Invalid chain id\n"); |
1660 | return -EINVAL; | |
1661 | } | |
1662 | ||
1663 | /* Check if the chain exists */ | |
1664 | if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { | |
1665 | printk(KERN_ERR "Chain doesn't exists\n"); | |
1666 | return -EINVAL; | |
1667 | } | |
1668 | channels = dma_linked_lch[chain_id].linked_dmach_q; | |
1669 | ||
d3c9be2f | 1670 | if (IS_DMA_ERRATA(DMA_ERRATA_i88)) { |
f31cc962 | 1671 | sys_cf = p->dma_read(OCP_SYSCONFIG, 0); |
d3c9be2f MK |
1672 | l = sys_cf; |
1673 | /* Middle mode reg set no Standby */ | |
1674 | l &= ~((1 << 12)|(1 << 13)); | |
f31cc962 | 1675 | p->dma_write(l, OCP_SYSCONFIG, 0); |
d3c9be2f | 1676 | } |
f8151e5c AG |
1677 | |
1678 | for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { | |
1679 | ||
1680 | /* Stop the Channel transmission */ | |
f31cc962 | 1681 | l = p->dma_read(CCR, channels[i]); |
0499bdeb | 1682 | l &= ~(1 << 7); |
f31cc962 | 1683 | p->dma_write(l, CCR, channels[i]); |
f8151e5c AG |
1684 | |
1685 | /* Disable the link in all the channels */ | |
1686 | disable_lnk(channels[i]); | |
1687 | dma_chan[channels[i]].state = DMA_CH_NOTSTARTED; | |
1688 | ||
1689 | } | |
1690 | dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED; | |
1691 | ||
1692 | /* Reset the Queue pointers */ | |
1693 | OMAP_DMA_CHAIN_QINIT(chain_id); | |
1694 | ||
d3c9be2f | 1695 | if (IS_DMA_ERRATA(DMA_ERRATA_i88)) |
f31cc962 | 1696 | p->dma_write(sys_cf, OCP_SYSCONFIG, 0); |
97b7f715 | 1697 | |
f8151e5c AG |
1698 | return 0; |
1699 | } | |
1700 | EXPORT_SYMBOL(omap_stop_dma_chain_transfers); | |
1701 | ||
1702 | /* Get the index of the ongoing DMA in chain */ | |
1703 | /** | |
1704 | * @brief omap_get_dma_chain_index - Get the element and frame index | |
1705 | * of the ongoing DMA in chain | |
1706 | * | |
1707 | * @param chain_id | |
1708 | * @param ei - Element index | |
1709 | * @param fi - Frame index | |
1710 | * | |
1711 | * @return - Success : 0 | |
1712 | * Failure : -EINVAL | |
1713 | */ | |
1714 | int omap_get_dma_chain_index(int chain_id, int *ei, int *fi) | |
1715 | { | |
1716 | int lch; | |
1717 | int *channels; | |
1718 | ||
1719 | /* Check for input params */ | |
4d96372e | 1720 | if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { |
f8151e5c AG |
1721 | printk(KERN_ERR "Invalid chain id\n"); |
1722 | return -EINVAL; | |
1723 | } | |
1724 | ||
1725 | /* Check if the chain exists */ | |
1726 | if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { | |
1727 | printk(KERN_ERR "Chain doesn't exists\n"); | |
1728 | return -EINVAL; | |
1729 | } | |
1730 | if ((!ei) || (!fi)) | |
1731 | return -EINVAL; | |
1732 | ||
1733 | channels = dma_linked_lch[chain_id].linked_dmach_q; | |
1734 | ||
1735 | /* Get the current channel */ | |
1736 | lch = channels[dma_linked_lch[chain_id].q_head]; | |
1737 | ||
f31cc962 MK |
1738 | *ei = p->dma_read(CCEN, lch); |
1739 | *fi = p->dma_read(CCFN, lch); | |
f8151e5c AG |
1740 | |
1741 | return 0; | |
1742 | } | |
1743 | EXPORT_SYMBOL(omap_get_dma_chain_index); | |
1744 | ||
1745 | /** | |
1746 | * @brief omap_get_dma_chain_dst_pos - Get the destination position of the | |
1747 | * ongoing DMA in chain | |
1748 | * | |
1749 | * @param chain_id | |
1750 | * | |
1751 | * @return - Success : Destination position | |
1752 | * Failure : -EINVAL | |
1753 | */ | |
1754 | int omap_get_dma_chain_dst_pos(int chain_id) | |
1755 | { | |
1756 | int lch; | |
1757 | int *channels; | |
1758 | ||
1759 | /* Check for input params */ | |
4d96372e | 1760 | if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { |
f8151e5c AG |
1761 | printk(KERN_ERR "Invalid chain id\n"); |
1762 | return -EINVAL; | |
1763 | } | |
1764 | ||
1765 | /* Check if the chain exists */ | |
1766 | if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { | |
1767 | printk(KERN_ERR "Chain doesn't exists\n"); | |
1768 | return -EINVAL; | |
1769 | } | |
1770 | ||
1771 | channels = dma_linked_lch[chain_id].linked_dmach_q; | |
1772 | ||
1773 | /* Get the current channel */ | |
1774 | lch = channels[dma_linked_lch[chain_id].q_head]; | |
1775 | ||
f31cc962 | 1776 | return p->dma_read(CDAC, lch); |
f8151e5c AG |
1777 | } |
1778 | EXPORT_SYMBOL(omap_get_dma_chain_dst_pos); | |
1779 | ||
1780 | /** | |
1781 | * @brief omap_get_dma_chain_src_pos - Get the source position | |
1782 | * of the ongoing DMA in chain | |
1783 | * @param chain_id | |
1784 | * | |
1785 | * @return - Success : Destination position | |
1786 | * Failure : -EINVAL | |
1787 | */ | |
1788 | int omap_get_dma_chain_src_pos(int chain_id) | |
1789 | { | |
1790 | int lch; | |
1791 | int *channels; | |
1792 | ||
1793 | /* Check for input params */ | |
4d96372e | 1794 | if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) { |
f8151e5c AG |
1795 | printk(KERN_ERR "Invalid chain id\n"); |
1796 | return -EINVAL; | |
1797 | } | |
1798 | ||
1799 | /* Check if the chain exists */ | |
1800 | if (dma_linked_lch[chain_id].linked_dmach_q == NULL) { | |
1801 | printk(KERN_ERR "Chain doesn't exists\n"); | |
1802 | return -EINVAL; | |
1803 | } | |
1804 | ||
1805 | channels = dma_linked_lch[chain_id].linked_dmach_q; | |
1806 | ||
1807 | /* Get the current channel */ | |
1808 | lch = channels[dma_linked_lch[chain_id].q_head]; | |
1809 | ||
f31cc962 | 1810 | return p->dma_read(CSAC, lch); |
f8151e5c AG |
1811 | } |
1812 | EXPORT_SYMBOL(omap_get_dma_chain_src_pos); | |
97b7f715 | 1813 | #endif /* ifndef CONFIG_ARCH_OMAP1 */ |
f8151e5c | 1814 | |
1a8bfa1e TL |
1815 | /*----------------------------------------------------------------------------*/ |
1816 | ||
1817 | #ifdef CONFIG_ARCH_OMAP1 | |
1818 | ||
1819 | static int omap1_dma_handle_ch(int ch) | |
1820 | { | |
0499bdeb | 1821 | u32 csr; |
1a8bfa1e TL |
1822 | |
1823 | if (enable_1510_mode && ch >= 6) { | |
1824 | csr = dma_chan[ch].saved_csr; | |
1825 | dma_chan[ch].saved_csr = 0; | |
1826 | } else | |
f31cc962 | 1827 | csr = p->dma_read(CSR, ch); |
1a8bfa1e TL |
1828 | if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) { |
1829 | dma_chan[ch + 6].saved_csr = csr >> 7; | |
1830 | csr &= 0x7f; | |
1831 | } | |
1832 | if ((csr & 0x3f) == 0) | |
1833 | return 0; | |
1834 | if (unlikely(dma_chan[ch].dev_id == -1)) { | |
7852ec05 PW |
1835 | pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n", |
1836 | ch, csr); | |
1a8bfa1e TL |
1837 | return 0; |
1838 | } | |
7ff879db | 1839 | if (unlikely(csr & OMAP1_DMA_TOUT_IRQ)) |
7852ec05 | 1840 | pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id); |
1a8bfa1e | 1841 | if (unlikely(csr & OMAP_DMA_DROP_IRQ)) |
7852ec05 PW |
1842 | pr_warn("DMA synchronization event drop occurred with device %d\n", |
1843 | dma_chan[ch].dev_id); | |
1a8bfa1e TL |
1844 | if (likely(csr & OMAP_DMA_BLOCK_IRQ)) |
1845 | dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; | |
1846 | if (likely(dma_chan[ch].callback != NULL)) | |
1847 | dma_chan[ch].callback(ch, csr, dma_chan[ch].data); | |
97b7f715 | 1848 | |
1a8bfa1e TL |
1849 | return 1; |
1850 | } | |
1851 | ||
0cd61b68 | 1852 | static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id) |
1a8bfa1e TL |
1853 | { |
1854 | int ch = ((int) dev_id) - 1; | |
1855 | int handled = 0; | |
1856 | ||
1857 | for (;;) { | |
1858 | int handled_now = 0; | |
1859 | ||
1860 | handled_now += omap1_dma_handle_ch(ch); | |
1861 | if (enable_1510_mode && dma_chan[ch + 6].saved_csr) | |
1862 | handled_now += omap1_dma_handle_ch(ch + 6); | |
1863 | if (!handled_now) | |
1864 | break; | |
1865 | handled += handled_now; | |
1866 | } | |
1867 | ||
1868 | return handled ? IRQ_HANDLED : IRQ_NONE; | |
1869 | } | |
1870 | ||
1871 | #else | |
1872 | #define omap1_dma_irq_handler NULL | |
1873 | #endif | |
1874 | ||
140455fa | 1875 | #ifdef CONFIG_ARCH_OMAP2PLUS |
1a8bfa1e TL |
1876 | |
1877 | static int omap2_dma_handle_ch(int ch) | |
1878 | { | |
f31cc962 | 1879 | u32 status = p->dma_read(CSR, ch); |
1a8bfa1e | 1880 | |
3151369d JY |
1881 | if (!status) { |
1882 | if (printk_ratelimit()) | |
7852ec05 | 1883 | pr_warn("Spurious DMA IRQ for lch %d\n", ch); |
f31cc962 | 1884 | p->dma_write(1 << ch, IRQSTATUS_L0, ch); |
1a8bfa1e | 1885 | return 0; |
3151369d JY |
1886 | } |
1887 | if (unlikely(dma_chan[ch].dev_id == -1)) { | |
1888 | if (printk_ratelimit()) | |
7852ec05 PW |
1889 | pr_warn("IRQ %04x for non-allocated DMA channel %d\n", |
1890 | status, ch); | |
1a8bfa1e | 1891 | return 0; |
3151369d | 1892 | } |
1a8bfa1e | 1893 | if (unlikely(status & OMAP_DMA_DROP_IRQ)) |
7852ec05 PW |
1894 | pr_info("DMA synchronization event drop occurred with device %d\n", |
1895 | dma_chan[ch].dev_id); | |
a50f18c7 | 1896 | if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) { |
1a8bfa1e TL |
1897 | printk(KERN_INFO "DMA transaction error with device %d\n", |
1898 | dma_chan[ch].dev_id); | |
d3c9be2f | 1899 | if (IS_DMA_ERRATA(DMA_ERRATA_i378)) { |
a50f18c7 SS |
1900 | u32 ccr; |
1901 | ||
f31cc962 | 1902 | ccr = p->dma_read(CCR, ch); |
a50f18c7 | 1903 | ccr &= ~OMAP_DMA_CCR_EN; |
f31cc962 | 1904 | p->dma_write(ccr, CCR, ch); |
a50f18c7 SS |
1905 | dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; |
1906 | } | |
1907 | } | |
7ff879db TL |
1908 | if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ)) |
1909 | printk(KERN_INFO "DMA secure error with device %d\n", | |
1910 | dma_chan[ch].dev_id); | |
1911 | if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ)) | |
1912 | printk(KERN_INFO "DMA misaligned error with device %d\n", | |
1913 | dma_chan[ch].dev_id); | |
1a8bfa1e | 1914 | |
4fb699b4 | 1915 | p->dma_write(status, CSR, ch); |
f31cc962 | 1916 | p->dma_write(1 << ch, IRQSTATUS_L0, ch); |
e860e6da | 1917 | /* read back the register to flush the write */ |
f31cc962 | 1918 | p->dma_read(IRQSTATUS_L0, ch); |
1a8bfa1e | 1919 | |
f8151e5c AG |
1920 | /* If the ch is not chained then chain_id will be -1 */ |
1921 | if (dma_chan[ch].chain_id != -1) { | |
1922 | int chain_id = dma_chan[ch].chain_id; | |
1923 | dma_chan[ch].state = DMA_CH_NOTSTARTED; | |
f31cc962 | 1924 | if (p->dma_read(CLNK_CTRL, ch) & (1 << 15)) |
f8151e5c AG |
1925 | dma_chan[dma_chan[ch].next_linked_ch].state = |
1926 | DMA_CH_STARTED; | |
1927 | if (dma_linked_lch[chain_id].chain_mode == | |
1928 | OMAP_DMA_DYNAMIC_CHAIN) | |
1929 | disable_lnk(ch); | |
1930 | ||
1931 | if (!OMAP_DMA_CHAIN_QEMPTY(chain_id)) | |
1932 | OMAP_DMA_CHAIN_INCQHEAD(chain_id); | |
1933 | ||
f31cc962 | 1934 | status = p->dma_read(CSR, ch); |
4fb699b4 | 1935 | p->dma_write(status, CSR, ch); |
f8151e5c AG |
1936 | } |
1937 | ||
538528de JN |
1938 | if (likely(dma_chan[ch].callback != NULL)) |
1939 | dma_chan[ch].callback(ch, status, dma_chan[ch].data); | |
f8151e5c | 1940 | |
1a8bfa1e TL |
1941 | return 0; |
1942 | } | |
1943 | ||
1944 | /* STATUS register count is from 1-32 while our is 0-31 */ | |
0cd61b68 | 1945 | static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) |
1a8bfa1e | 1946 | { |
52176e70 | 1947 | u32 val, enable_reg; |
1a8bfa1e TL |
1948 | int i; |
1949 | ||
f31cc962 | 1950 | val = p->dma_read(IRQSTATUS_L0, 0); |
3151369d JY |
1951 | if (val == 0) { |
1952 | if (printk_ratelimit()) | |
1953 | printk(KERN_WARNING "Spurious DMA IRQ\n"); | |
1954 | return IRQ_HANDLED; | |
1955 | } | |
f31cc962 | 1956 | enable_reg = p->dma_read(IRQENABLE_L0, 0); |
52176e70 | 1957 | val &= enable_reg; /* Dispatch only relevant interrupts */ |
4d96372e | 1958 | for (i = 0; i < dma_lch_count && val != 0; i++) { |
3151369d JY |
1959 | if (val & 1) |
1960 | omap2_dma_handle_ch(i); | |
1961 | val >>= 1; | |
1a8bfa1e TL |
1962 | } |
1963 | ||
1964 | return IRQ_HANDLED; | |
1965 | } | |
1966 | ||
1967 | static struct irqaction omap24xx_dma_irq = { | |
1968 | .name = "DMA", | |
1969 | .handler = omap2_dma_irq_handler, | |
52e405ea | 1970 | .flags = IRQF_DISABLED |
1a8bfa1e TL |
1971 | }; |
1972 | ||
1973 | #else | |
1974 | static struct irqaction omap24xx_dma_irq; | |
1975 | #endif | |
1976 | ||
1977 | /*----------------------------------------------------------------------------*/ | |
5e1c5ff4 | 1978 | |
f2d11858 TK |
1979 | void omap_dma_global_context_save(void) |
1980 | { | |
1981 | omap_dma_global_context.dma_irqenable_l0 = | |
f31cc962 | 1982 | p->dma_read(IRQENABLE_L0, 0); |
f2d11858 | 1983 | omap_dma_global_context.dma_ocp_sysconfig = |
f31cc962 MK |
1984 | p->dma_read(OCP_SYSCONFIG, 0); |
1985 | omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0); | |
f2d11858 TK |
1986 | } |
1987 | ||
1988 | void omap_dma_global_context_restore(void) | |
1989 | { | |
bf07c9f2 AK |
1990 | int ch; |
1991 | ||
f31cc962 MK |
1992 | p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0); |
1993 | p->dma_write(omap_dma_global_context.dma_ocp_sysconfig, | |
a4c537c7 | 1994 | OCP_SYSCONFIG, 0); |
f31cc962 | 1995 | p->dma_write(omap_dma_global_context.dma_irqenable_l0, |
a4c537c7 | 1996 | IRQENABLE_L0, 0); |
f2d11858 | 1997 | |
d3c9be2f | 1998 | if (IS_DMA_ERRATA(DMA_ROMCODE_BUG)) |
f31cc962 | 1999 | p->dma_write(0x3 , IRQSTATUS_L0, 0); |
bf07c9f2 AK |
2000 | |
2001 | for (ch = 0; ch < dma_chan_count; ch++) | |
2002 | if (dma_chan[ch].dev_id != -1) | |
2003 | omap_clear_dma(ch); | |
f2d11858 TK |
2004 | } |
2005 | ||
f31cc962 | 2006 | static int __devinit omap_system_dma_probe(struct platform_device *pdev) |
d3c9be2f | 2007 | { |
f31cc962 MK |
2008 | int ch, ret = 0; |
2009 | int dma_irq; | |
2010 | char irq_name[4]; | |
2011 | int irq_rel; | |
2012 | ||
2013 | p = pdev->dev.platform_data; | |
2014 | if (!p) { | |
7852ec05 PW |
2015 | dev_err(&pdev->dev, |
2016 | "%s: System DMA initialized without platform data\n", | |
2017 | __func__); | |
f31cc962 | 2018 | return -EINVAL; |
0499bdeb | 2019 | } |
4d96372e | 2020 | |
f31cc962 MK |
2021 | d = p->dma_attr; |
2022 | errata = p->errata; | |
a4c537c7 | 2023 | |
f31cc962 | 2024 | if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels |
2263f022 | 2025 | && (omap_dma_reserve_channels <= dma_lch_count)) |
f31cc962 | 2026 | d->lch_count = omap_dma_reserve_channels; |
2263f022 | 2027 | |
f31cc962 MK |
2028 | dma_lch_count = d->lch_count; |
2029 | dma_chan_count = dma_lch_count; | |
2030 | dma_chan = d->chan; | |
2031 | enable_1510_mode = d->dev_caps & ENABLE_1510_MODE; | |
4d96372e TL |
2032 | |
2033 | if (cpu_class_is_omap2()) { | |
2034 | dma_linked_lch = kzalloc(sizeof(struct dma_link_info) * | |
2035 | dma_lch_count, GFP_KERNEL); | |
2036 | if (!dma_linked_lch) { | |
f31cc962 MK |
2037 | ret = -ENOMEM; |
2038 | goto exit_dma_lch_fail; | |
4d96372e TL |
2039 | } |
2040 | } | |
2041 | ||
5e1c5ff4 | 2042 | spin_lock_init(&dma_chan_lock); |
5e1c5ff4 | 2043 | for (ch = 0; ch < dma_chan_count; ch++) { |
1a8bfa1e | 2044 | omap_clear_dma(ch); |
ada8d4a5 MW |
2045 | if (cpu_class_is_omap2()) |
2046 | omap2_disable_irq_lch(ch); | |
2047 | ||
5e1c5ff4 TL |
2048 | dma_chan[ch].dev_id = -1; |
2049 | dma_chan[ch].next_lch = -1; | |
2050 | ||
2051 | if (ch >= 6 && enable_1510_mode) | |
2052 | continue; | |
2053 | ||
1a8bfa1e | 2054 | if (cpu_class_is_omap1()) { |
97b7f715 TL |
2055 | /* |
2056 | * request_irq() doesn't like dev_id (ie. ch) being | |
2057 | * zero, so we have to kludge around this. | |
2058 | */ | |
f31cc962 MK |
2059 | sprintf(&irq_name[0], "%d", ch); |
2060 | dma_irq = platform_get_irq_byname(pdev, irq_name); | |
2061 | ||
2062 | if (dma_irq < 0) { | |
2063 | ret = dma_irq; | |
2064 | goto exit_dma_irq_fail; | |
2065 | } | |
2066 | ||
2067 | /* INT_DMA_LCD is handled in lcd_dma.c */ | |
2068 | if (dma_irq == INT_DMA_LCD) | |
2069 | continue; | |
2070 | ||
2071 | ret = request_irq(dma_irq, | |
1a8bfa1e TL |
2072 | omap1_dma_irq_handler, 0, "DMA", |
2073 | (void *) (ch + 1)); | |
f31cc962 MK |
2074 | if (ret != 0) |
2075 | goto exit_dma_irq_fail; | |
1a8bfa1e TL |
2076 | } |
2077 | } | |
2078 | ||
d07c3df8 | 2079 | if (cpu_class_is_omap2() && !cpu_is_omap242x()) |
f8151e5c AG |
2080 | omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE, |
2081 | DMA_DEFAULT_FIFO_DEPTH, 0); | |
2082 | ||
44169075 | 2083 | if (cpu_class_is_omap2()) { |
f31cc962 MK |
2084 | strcpy(irq_name, "0"); |
2085 | dma_irq = platform_get_irq_byname(pdev, irq_name); | |
2086 | if (dma_irq < 0) { | |
2087 | dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq); | |
2088 | goto exit_dma_lch_fail; | |
2089 | } | |
2090 | ret = setup_irq(dma_irq, &omap24xx_dma_irq); | |
2091 | if (ret) { | |
7852ec05 PW |
2092 | dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n", |
2093 | dma_irq, ret); | |
f31cc962 | 2094 | goto exit_dma_lch_fail; |
ba50ea7e | 2095 | } |
aecedb94 KJ |
2096 | } |
2097 | ||
f31cc962 MK |
2098 | /* reserve dma channels 0 and 1 in high security devices */ |
2099 | if (cpu_is_omap34xx() && | |
2100 | (omap_type() != OMAP2_DEVICE_TYPE_GP)) { | |
7852ec05 | 2101 | pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n"); |
f31cc962 MK |
2102 | dma_chan[0].dev_id = 0; |
2103 | dma_chan[1].dev_id = 1; | |
2104 | } | |
2105 | p->show_dma_caps(); | |
5e1c5ff4 | 2106 | return 0; |
7e9bf847 | 2107 | |
f31cc962 | 2108 | exit_dma_irq_fail: |
7852ec05 PW |
2109 | dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n", |
2110 | dma_irq, ret); | |
f31cc962 MK |
2111 | for (irq_rel = 0; irq_rel < ch; irq_rel++) { |
2112 | dma_irq = platform_get_irq(pdev, irq_rel); | |
2113 | free_irq(dma_irq, (void *)(irq_rel + 1)); | |
2114 | } | |
2115 | ||
2116 | exit_dma_lch_fail: | |
2117 | kfree(p); | |
2118 | kfree(d); | |
7e9bf847 | 2119 | kfree(dma_chan); |
f31cc962 MK |
2120 | return ret; |
2121 | } | |
7e9bf847 | 2122 | |
f31cc962 MK |
2123 | static int __devexit omap_system_dma_remove(struct platform_device *pdev) |
2124 | { | |
2125 | int dma_irq; | |
7e9bf847 | 2126 | |
f31cc962 MK |
2127 | if (cpu_class_is_omap2()) { |
2128 | char irq_name[4]; | |
2129 | strcpy(irq_name, "0"); | |
2130 | dma_irq = platform_get_irq_byname(pdev, irq_name); | |
2131 | remove_irq(dma_irq, &omap24xx_dma_irq); | |
2132 | } else { | |
2133 | int irq_rel = 0; | |
2134 | for ( ; irq_rel < dma_chan_count; irq_rel++) { | |
2135 | dma_irq = platform_get_irq(pdev, irq_rel); | |
2136 | free_irq(dma_irq, (void *)(irq_rel + 1)); | |
2137 | } | |
2138 | } | |
2139 | kfree(p); | |
2140 | kfree(d); | |
2141 | kfree(dma_chan); | |
2142 | return 0; | |
2143 | } | |
2144 | ||
2145 | static struct platform_driver omap_system_dma_driver = { | |
2146 | .probe = omap_system_dma_probe, | |
3e2e613f | 2147 | .remove = __devexit_p(omap_system_dma_remove), |
f31cc962 MK |
2148 | .driver = { |
2149 | .name = "omap_dma_system" | |
2150 | }, | |
2151 | }; | |
2152 | ||
2153 | static int __init omap_system_dma_init(void) | |
2154 | { | |
2155 | return platform_driver_register(&omap_system_dma_driver); | |
2156 | } | |
2157 | arch_initcall(omap_system_dma_init); | |
2158 | ||
2159 | static void __exit omap_system_dma_exit(void) | |
2160 | { | |
2161 | platform_driver_unregister(&omap_system_dma_driver); | |
5e1c5ff4 TL |
2162 | } |
2163 | ||
f31cc962 MK |
2164 | MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER"); |
2165 | MODULE_LICENSE("GPL"); | |
2166 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
2167 | MODULE_AUTHOR("Texas Instruments Inc"); | |
5e1c5ff4 | 2168 | |
2263f022 SS |
2169 | /* |
2170 | * Reserve the omap SDMA channels using cmdline bootarg | |
2171 | * "omap_dma_reserve_ch=". The valid range is 1 to 32 | |
2172 | */ | |
2173 | static int __init omap_dma_cmdline_reserve_ch(char *str) | |
2174 | { | |
2175 | if (get_option(&str, &omap_dma_reserve_channels) != 1) | |
2176 | omap_dma_reserve_channels = 0; | |
2177 | return 1; | |
2178 | } | |
2179 | ||
2180 | __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch); | |
2181 | ||
5e1c5ff4 | 2182 |