Commit | Line | Data |
---|---|---|
92105bb7 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/dmtimer.c | |
3 | * | |
4 | * OMAP Dual-Mode Timers | |
5 | * | |
97933d6c TKD |
6 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ |
7 | * Tarun Kanti DebBarma <tarun.kanti@ti.com> | |
8 | * Thara Gopinath <thara@ti.com> | |
9 | * | |
10 | * dmtimer adaptation to platform_driver. | |
11 | * | |
92105bb7 | 12 | * Copyright (C) 2005 Nokia Corporation |
77900a2f TT |
13 | * OMAP2 support by Juha Yrjola |
14 | * API improvements and OMAP2 clock framework support by Timo Teras | |
92105bb7 | 15 | * |
44169075 SS |
16 | * Copyright (C) 2009 Texas Instruments |
17 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
18 | * | |
92105bb7 TL |
19 | * This program is free software; you can redistribute it and/or modify it |
20 | * under the terms of the GNU General Public License as published by the | |
21 | * Free Software Foundation; either version 2 of the License, or (at your | |
22 | * option) any later version. | |
23 | * | |
24 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
25 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
26 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
27 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
28 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License along | |
34 | * with this program; if not, write to the Free Software Foundation, Inc., | |
35 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
36 | */ | |
37 | ||
b1538832 | 38 | #include <linux/clk.h> |
ea05d2ea | 39 | #include <linux/clk-provider.h> |
869dec15 | 40 | #include <linux/module.h> |
fced80c7 | 41 | #include <linux/io.h> |
74dd9ec6 | 42 | #include <linux/device.h> |
3392cdd3 | 43 | #include <linux/err.h> |
ffe07cea | 44 | #include <linux/pm_runtime.h> |
9725f445 JH |
45 | #include <linux/of.h> |
46 | #include <linux/of_device.h> | |
40fc3bb5 JH |
47 | #include <linux/platform_device.h> |
48 | #include <linux/platform_data/dmtimer-omap.h> | |
44169075 | 49 | |
3392cdd3 | 50 | #include <plat/dmtimer.h> |
2c799cef | 51 | |
b7b4ff76 | 52 | static u32 omap_reserved_systimers; |
df28472a | 53 | static LIST_HEAD(omap_timer_list); |
3392cdd3 | 54 | static DEFINE_SPINLOCK(dm_timer_lock); |
92105bb7 | 55 | |
8fc7fcb5 JH |
56 | enum { |
57 | REQUEST_ANY = 0, | |
58 | REQUEST_BY_ID, | |
59 | REQUEST_BY_CAP, | |
60 | REQUEST_BY_NODE, | |
61 | }; | |
62 | ||
3392cdd3 TKD |
63 | /** |
64 | * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode | |
65 | * @timer: timer pointer over which read operation to perform | |
66 | * @reg: lowest byte holds the register offset | |
67 | * | |
68 | * The posted mode bit is encoded in reg. Note that in posted mode write | |
69 | * pending bit must be checked. Otherwise a read of a non completed write | |
70 | * will produce an error. | |
0f0d0807 RW |
71 | */ |
72 | static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) | |
77900a2f | 73 | { |
ee17f114 TL |
74 | WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
75 | return __omap_dm_timer_read(timer, reg, timer->posted); | |
77900a2f | 76 | } |
92105bb7 | 77 | |
3392cdd3 TKD |
78 | /** |
79 | * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode | |
80 | * @timer: timer pointer over which write operation is to perform | |
81 | * @reg: lowest byte holds the register offset | |
82 | * @value: data to write into the register | |
83 | * | |
84 | * The posted mode bit is encoded in reg. Note that in posted mode the write | |
85 | * pending bit must be checked. Otherwise a write on a register which has a | |
86 | * pending write will be lost. | |
0f0d0807 RW |
87 | */ |
88 | static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, | |
89 | u32 value) | |
92105bb7 | 90 | { |
ee17f114 TL |
91 | WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
92 | __omap_dm_timer_write(timer, reg, value, timer->posted); | |
92105bb7 TL |
93 | } |
94 | ||
b481113a TKD |
95 | static void omap_timer_restore_context(struct omap_dm_timer *timer) |
96 | { | |
b481113a TKD |
97 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, |
98 | timer->context.twer); | |
99 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, | |
100 | timer->context.tcrr); | |
101 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, | |
102 | timer->context.tldr); | |
103 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, | |
104 | timer->context.tmar); | |
105 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, | |
106 | timer->context.tsicr); | |
834cacfb | 107 | writel_relaxed(timer->context.tier, timer->irq_ena); |
b481113a TKD |
108 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, |
109 | timer->context.tclr); | |
110 | } | |
111 | ||
ae6672cb | 112 | static int omap_dm_timer_reset(struct omap_dm_timer *timer) |
92105bb7 | 113 | { |
ae6672cb | 114 | u32 l, timeout = 100000; |
77900a2f | 115 | |
ae6672cb JH |
116 | if (timer->revision != 1) |
117 | return -EINVAL; | |
ee17f114 | 118 | |
ae6672cb JH |
119 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); |
120 | ||
121 | do { | |
122 | l = __omap_dm_timer_read(timer, | |
123 | OMAP_TIMER_V1_SYS_STAT_OFFSET, 0); | |
124 | } while (!l && timeout--); | |
125 | ||
126 | if (!timeout) { | |
127 | dev_err(&timer->pdev->dev, "Timer failed to reset\n"); | |
128 | return -ETIMEDOUT; | |
77900a2f | 129 | } |
92105bb7 | 130 | |
ae6672cb JH |
131 | /* Configure timer for smart-idle mode */ |
132 | l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0); | |
133 | l |= 0x2 << 0x3; | |
134 | __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0); | |
135 | ||
136 | timer->posted = 0; | |
137 | ||
138 | return 0; | |
77900a2f TT |
139 | } |
140 | ||
31a7448f NA |
141 | static int omap_dm_timer_of_set_source(struct omap_dm_timer *timer) |
142 | { | |
143 | int ret; | |
144 | struct clk *parent; | |
145 | ||
146 | /* | |
147 | * FIXME: OMAP1 devices do not use the clock framework for dmtimers so | |
148 | * do not call clk_get() for these devices. | |
149 | */ | |
150 | if (!timer->fclk) | |
151 | return -ENODEV; | |
152 | ||
153 | parent = clk_get(&timer->pdev->dev, NULL); | |
154 | if (IS_ERR(parent)) | |
155 | return -ENODEV; | |
156 | ||
157 | ret = clk_set_parent(timer->fclk, parent); | |
158 | if (ret < 0) | |
159 | pr_err("%s: failed to set parent\n", __func__); | |
160 | ||
161 | clk_put(parent); | |
162 | ||
163 | return ret; | |
164 | } | |
165 | ||
b0cadb3c | 166 | static int omap_dm_timer_prepare(struct omap_dm_timer *timer) |
77900a2f | 167 | { |
ae6672cb JH |
168 | int rc; |
169 | ||
bca45808 JH |
170 | /* |
171 | * FIXME: OMAP1 devices do not use the clock framework for dmtimers so | |
172 | * do not call clk_get() for these devices. | |
173 | */ | |
174 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { | |
175 | timer->fclk = clk_get(&timer->pdev->dev, "fck"); | |
86287958 | 176 | if (WARN_ON_ONCE(IS_ERR(timer->fclk))) { |
bca45808 JH |
177 | dev_err(&timer->pdev->dev, ": No fclk handle.\n"); |
178 | return -EINVAL; | |
179 | } | |
3392cdd3 TKD |
180 | } |
181 | ||
7b44cf2c JH |
182 | omap_dm_timer_enable(timer); |
183 | ||
ae6672cb JH |
184 | if (timer->capability & OMAP_TIMER_NEEDS_RESET) { |
185 | rc = omap_dm_timer_reset(timer); | |
186 | if (rc) { | |
187 | omap_dm_timer_disable(timer); | |
188 | return rc; | |
189 | } | |
190 | } | |
3392cdd3 | 191 | |
7b44cf2c JH |
192 | __omap_dm_timer_enable_posted(timer); |
193 | omap_dm_timer_disable(timer); | |
3392cdd3 | 194 | |
31a7448f NA |
195 | rc = omap_dm_timer_of_set_source(timer); |
196 | if (rc == -ENODEV) | |
197 | return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); | |
198 | ||
199 | return rc; | |
77900a2f TT |
200 | } |
201 | ||
b7b4ff76 JH |
202 | static inline u32 omap_dm_timer_reserved_systimer(int id) |
203 | { | |
204 | return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0; | |
205 | } | |
206 | ||
207 | int omap_dm_timer_reserve_systimer(int id) | |
208 | { | |
209 | if (omap_dm_timer_reserved_systimer(id)) | |
210 | return -ENODEV; | |
211 | ||
212 | omap_reserved_systimers |= (1 << (id - 1)); | |
213 | ||
214 | return 0; | |
215 | } | |
216 | ||
8fc7fcb5 | 217 | static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *data) |
77900a2f | 218 | { |
3392cdd3 | 219 | struct omap_dm_timer *timer = NULL, *t; |
8fc7fcb5 | 220 | struct device_node *np = NULL; |
77900a2f | 221 | unsigned long flags; |
8fc7fcb5 JH |
222 | u32 cap = 0; |
223 | int id = 0; | |
224 | ||
225 | switch (req_type) { | |
226 | case REQUEST_BY_ID: | |
227 | id = *(int *)data; | |
228 | break; | |
229 | case REQUEST_BY_CAP: | |
230 | cap = *(u32 *)data; | |
231 | break; | |
232 | case REQUEST_BY_NODE: | |
233 | np = (struct device_node *)data; | |
234 | break; | |
235 | default: | |
236 | /* REQUEST_ANY */ | |
237 | break; | |
238 | } | |
77900a2f TT |
239 | |
240 | spin_lock_irqsave(&dm_timer_lock, flags); | |
3392cdd3 TKD |
241 | list_for_each_entry(t, &omap_timer_list, node) { |
242 | if (t->reserved) | |
77900a2f TT |
243 | continue; |
244 | ||
8fc7fcb5 JH |
245 | switch (req_type) { |
246 | case REQUEST_BY_ID: | |
247 | if (id == t->pdev->id) { | |
248 | timer = t; | |
249 | timer->reserved = 1; | |
250 | goto found; | |
251 | } | |
252 | break; | |
253 | case REQUEST_BY_CAP: | |
254 | if (cap == (t->capability & cap)) { | |
255 | /* | |
256 | * If timer is not NULL, we have already found | |
257 | * one timer but it was not an exact match | |
258 | * because it had more capabilites that what | |
259 | * was required. Therefore, unreserve the last | |
260 | * timer found and see if this one is a better | |
261 | * match. | |
262 | */ | |
263 | if (timer) | |
264 | timer->reserved = 0; | |
265 | timer = t; | |
266 | timer->reserved = 1; | |
267 | ||
268 | /* Exit loop early if we find an exact match */ | |
269 | if (t->capability == cap) | |
270 | goto found; | |
271 | } | |
272 | break; | |
273 | case REQUEST_BY_NODE: | |
274 | if (np == t->pdev->dev.of_node) { | |
275 | timer = t; | |
276 | timer->reserved = 1; | |
277 | goto found; | |
278 | } | |
279 | break; | |
280 | default: | |
281 | /* REQUEST_ANY */ | |
282 | timer = t; | |
283 | timer->reserved = 1; | |
284 | goto found; | |
285 | } | |
77900a2f | 286 | } |
8fc7fcb5 | 287 | found: |
c5491d1a | 288 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
3392cdd3 | 289 | |
8fc7fcb5 JH |
290 | if (timer && omap_dm_timer_prepare(timer)) { |
291 | timer->reserved = 0; | |
292 | timer = NULL; | |
3392cdd3 | 293 | } |
77900a2f | 294 | |
3392cdd3 TKD |
295 | if (!timer) |
296 | pr_debug("%s: timer request failed!\n", __func__); | |
83379c81 | 297 | |
77900a2f TT |
298 | return timer; |
299 | } | |
8fc7fcb5 JH |
300 | |
301 | struct omap_dm_timer *omap_dm_timer_request(void) | |
302 | { | |
303 | return _omap_dm_timer_request(REQUEST_ANY, NULL); | |
304 | } | |
6c366e32 | 305 | EXPORT_SYMBOL_GPL(omap_dm_timer_request); |
77900a2f TT |
306 | |
307 | struct omap_dm_timer *omap_dm_timer_request_specific(int id) | |
92105bb7 | 308 | { |
9725f445 JH |
309 | /* Requesting timer by ID is not supported when device tree is used */ |
310 | if (of_have_populated_dt()) { | |
8fc7fcb5 | 311 | pr_warn("%s: Please use omap_dm_timer_request_by_cap/node()\n", |
9725f445 JH |
312 | __func__); |
313 | return NULL; | |
314 | } | |
315 | ||
8fc7fcb5 | 316 | return _omap_dm_timer_request(REQUEST_BY_ID, &id); |
92105bb7 | 317 | } |
6c366e32 | 318 | EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific); |
92105bb7 | 319 | |
373fe0bd JH |
320 | /** |
321 | * omap_dm_timer_request_by_cap - Request a timer by capability | |
322 | * @cap: Bit mask of capabilities to match | |
323 | * | |
324 | * Find a timer based upon capabilities bit mask. Callers of this function | |
325 | * should use the definitions found in the plat/dmtimer.h file under the | |
326 | * comment "timer capabilities used in hwmod database". Returns pointer to | |
327 | * timer handle on success and a NULL pointer on failure. | |
328 | */ | |
329 | struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap) | |
330 | { | |
8fc7fcb5 JH |
331 | return _omap_dm_timer_request(REQUEST_BY_CAP, &cap); |
332 | } | |
333 | EXPORT_SYMBOL_GPL(omap_dm_timer_request_by_cap); | |
373fe0bd | 334 | |
8fc7fcb5 JH |
335 | /** |
336 | * omap_dm_timer_request_by_node - Request a timer by device-tree node | |
337 | * @np: Pointer to device-tree timer node | |
338 | * | |
339 | * Request a timer based upon a device node pointer. Returns pointer to | |
340 | * timer handle on success and a NULL pointer on failure. | |
341 | */ | |
342 | struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np) | |
343 | { | |
344 | if (!np) | |
373fe0bd JH |
345 | return NULL; |
346 | ||
8fc7fcb5 | 347 | return _omap_dm_timer_request(REQUEST_BY_NODE, np); |
373fe0bd | 348 | } |
8fc7fcb5 | 349 | EXPORT_SYMBOL_GPL(omap_dm_timer_request_by_node); |
373fe0bd | 350 | |
ab4eb8b0 | 351 | int omap_dm_timer_free(struct omap_dm_timer *timer) |
77900a2f | 352 | { |
ab4eb8b0 TKD |
353 | if (unlikely(!timer)) |
354 | return -EINVAL; | |
355 | ||
3392cdd3 | 356 | clk_put(timer->fclk); |
fa4bb626 | 357 | |
77900a2f TT |
358 | WARN_ON(!timer->reserved); |
359 | timer->reserved = 0; | |
ab4eb8b0 | 360 | return 0; |
77900a2f | 361 | } |
6c366e32 | 362 | EXPORT_SYMBOL_GPL(omap_dm_timer_free); |
77900a2f | 363 | |
12583a70 TT |
364 | void omap_dm_timer_enable(struct omap_dm_timer *timer) |
365 | { | |
9cc268d5 N |
366 | int c; |
367 | ||
ffe07cea | 368 | pm_runtime_get_sync(&timer->pdev->dev); |
9cc268d5 N |
369 | |
370 | if (!(timer->capability & OMAP_TIMER_ALWON)) { | |
371 | if (timer->get_context_loss_count) { | |
372 | c = timer->get_context_loss_count(&timer->pdev->dev); | |
373 | if (c != timer->ctx_loss_count) { | |
374 | omap_timer_restore_context(timer); | |
375 | timer->ctx_loss_count = c; | |
376 | } | |
385c4c7b JH |
377 | } else { |
378 | omap_timer_restore_context(timer); | |
9cc268d5 N |
379 | } |
380 | } | |
12583a70 | 381 | } |
6c366e32 | 382 | EXPORT_SYMBOL_GPL(omap_dm_timer_enable); |
12583a70 TT |
383 | |
384 | void omap_dm_timer_disable(struct omap_dm_timer *timer) | |
385 | { | |
54f32a35 | 386 | pm_runtime_put_sync(&timer->pdev->dev); |
12583a70 | 387 | } |
6c366e32 | 388 | EXPORT_SYMBOL_GPL(omap_dm_timer_disable); |
12583a70 | 389 | |
77900a2f TT |
390 | int omap_dm_timer_get_irq(struct omap_dm_timer *timer) |
391 | { | |
ab4eb8b0 TKD |
392 | if (timer) |
393 | return timer->irq; | |
394 | return -EINVAL; | |
77900a2f | 395 | } |
6c366e32 | 396 | EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq); |
77900a2f TT |
397 | |
398 | #if defined(CONFIG_ARCH_OMAP1) | |
7136f8d8 | 399 | #include <mach/hardware.h> |
a569c6ec TL |
400 | /** |
401 | * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR | |
402 | * @inputmask: current value of idlect mask | |
403 | */ | |
404 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) | |
405 | { | |
3392cdd3 TKD |
406 | int i = 0; |
407 | struct omap_dm_timer *timer = NULL; | |
408 | unsigned long flags; | |
a569c6ec TL |
409 | |
410 | /* If ARMXOR cannot be idled this function call is unnecessary */ | |
411 | if (!(inputmask & (1 << 1))) | |
412 | return inputmask; | |
413 | ||
414 | /* If any active timer is using ARMXOR return modified mask */ | |
3392cdd3 TKD |
415 | spin_lock_irqsave(&dm_timer_lock, flags); |
416 | list_for_each_entry(timer, &omap_timer_list, node) { | |
77900a2f TT |
417 | u32 l; |
418 | ||
3392cdd3 | 419 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
420 | if (l & OMAP_TIMER_CTRL_ST) { |
421 | if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0) | |
a569c6ec TL |
422 | inputmask &= ~(1 << 1); |
423 | else | |
424 | inputmask &= ~(1 << 2); | |
425 | } | |
3392cdd3 | 426 | i++; |
77900a2f | 427 | } |
3392cdd3 | 428 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
a569c6ec TL |
429 | |
430 | return inputmask; | |
431 | } | |
6c366e32 | 432 | EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); |
a569c6ec | 433 | |
140455fa | 434 | #else |
a569c6ec | 435 | |
77900a2f | 436 | struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) |
92105bb7 | 437 | { |
86287958 | 438 | if (timer && !IS_ERR(timer->fclk)) |
ab4eb8b0 TKD |
439 | return timer->fclk; |
440 | return NULL; | |
77900a2f | 441 | } |
6c366e32 | 442 | EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk); |
92105bb7 | 443 | |
77900a2f TT |
444 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) |
445 | { | |
446 | BUG(); | |
2121880e DB |
447 | |
448 | return 0; | |
92105bb7 | 449 | } |
6c366e32 | 450 | EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); |
92105bb7 | 451 | |
77900a2f | 452 | #endif |
92105bb7 | 453 | |
ab4eb8b0 | 454 | int omap_dm_timer_trigger(struct omap_dm_timer *timer) |
92105bb7 | 455 | { |
ab4eb8b0 TKD |
456 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
457 | pr_err("%s: timer not available or enabled.\n", __func__); | |
458 | return -EINVAL; | |
b481113a TKD |
459 | } |
460 | ||
77900a2f | 461 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
ab4eb8b0 | 462 | return 0; |
92105bb7 | 463 | } |
6c366e32 | 464 | EXPORT_SYMBOL_GPL(omap_dm_timer_trigger); |
92105bb7 | 465 | |
ab4eb8b0 | 466 | int omap_dm_timer_start(struct omap_dm_timer *timer) |
77900a2f TT |
467 | { |
468 | u32 l; | |
92105bb7 | 469 | |
ab4eb8b0 TKD |
470 | if (unlikely(!timer)) |
471 | return -EINVAL; | |
472 | ||
b481113a TKD |
473 | omap_dm_timer_enable(timer); |
474 | ||
77900a2f TT |
475 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
476 | if (!(l & OMAP_TIMER_CTRL_ST)) { | |
477 | l |= OMAP_TIMER_CTRL_ST; | |
478 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | |
479 | } | |
b481113a TKD |
480 | |
481 | /* Save the context */ | |
482 | timer->context.tclr = l; | |
ab4eb8b0 | 483 | return 0; |
77900a2f | 484 | } |
6c366e32 | 485 | EXPORT_SYMBOL_GPL(omap_dm_timer_start); |
92105bb7 | 486 | |
ab4eb8b0 | 487 | int omap_dm_timer_stop(struct omap_dm_timer *timer) |
92105bb7 | 488 | { |
caf64f2f | 489 | unsigned long rate = 0; |
92105bb7 | 490 | |
ab4eb8b0 TKD |
491 | if (unlikely(!timer)) |
492 | return -EINVAL; | |
493 | ||
6615975b | 494 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) |
3392cdd3 | 495 | rate = clk_get_rate(timer->fclk); |
caf64f2f | 496 | |
ee17f114 | 497 | __omap_dm_timer_stop(timer, timer->posted, rate); |
ab4eb8b0 | 498 | |
dffc9dae TKD |
499 | /* |
500 | * Since the register values are computed and written within | |
501 | * __omap_dm_timer_stop, we need to use read to retrieve the | |
502 | * context. | |
503 | */ | |
504 | timer->context.tclr = | |
505 | omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); | |
dffc9dae | 506 | omap_dm_timer_disable(timer); |
ab4eb8b0 | 507 | return 0; |
92105bb7 | 508 | } |
6c366e32 | 509 | EXPORT_SYMBOL_GPL(omap_dm_timer_stop); |
92105bb7 | 510 | |
f248076c | 511 | int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) |
92105bb7 | 512 | { |
3392cdd3 | 513 | int ret; |
2b2d3523 | 514 | char *parent_name = NULL; |
d7aba554 | 515 | struct clk *parent; |
ab4eb8b0 TKD |
516 | struct dmtimer_platform_data *pdata; |
517 | ||
518 | if (unlikely(!timer)) | |
519 | return -EINVAL; | |
520 | ||
521 | pdata = timer->pdev->dev.platform_data; | |
3392cdd3 | 522 | |
77900a2f | 523 | if (source < 0 || source >= 3) |
f248076c | 524 | return -EINVAL; |
77900a2f | 525 | |
2b2d3523 JH |
526 | /* |
527 | * FIXME: Used for OMAP1 devices only because they do not currently | |
528 | * use the clock framework to set the parent clock. To be removed | |
529 | * once OMAP1 migrated to using clock framework for dmtimers | |
530 | */ | |
9725f445 | 531 | if (pdata && pdata->set_timer_src) |
2b2d3523 JH |
532 | return pdata->set_timer_src(timer->pdev, source); |
533 | ||
86287958 | 534 | if (IS_ERR(timer->fclk)) |
2b2d3523 | 535 | return -EINVAL; |
2b2d3523 | 536 | |
ea05d2ea SA |
537 | #if defined(CONFIG_COMMON_CLK) |
538 | /* Check if the clock has configurable parents */ | |
539 | if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2) | |
540 | return 0; | |
541 | #endif | |
542 | ||
2b2d3523 JH |
543 | switch (source) { |
544 | case OMAP_TIMER_SRC_SYS_CLK: | |
c59b537d | 545 | parent_name = "timer_sys_ck"; |
2b2d3523 JH |
546 | break; |
547 | ||
548 | case OMAP_TIMER_SRC_32_KHZ: | |
c59b537d | 549 | parent_name = "timer_32k_ck"; |
2b2d3523 JH |
550 | break; |
551 | ||
552 | case OMAP_TIMER_SRC_EXT_CLK: | |
c59b537d | 553 | parent_name = "timer_ext_ck"; |
2b2d3523 JH |
554 | break; |
555 | } | |
556 | ||
557 | parent = clk_get(&timer->pdev->dev, parent_name); | |
86287958 | 558 | if (IS_ERR(parent)) { |
2b2d3523 | 559 | pr_err("%s: %s not found\n", __func__, parent_name); |
d7aba554 | 560 | return -EINVAL; |
2b2d3523 JH |
561 | } |
562 | ||
d7aba554 | 563 | ret = clk_set_parent(timer->fclk, parent); |
c48cd659 | 564 | if (ret < 0) |
2b2d3523 JH |
565 | pr_err("%s: failed to set %s as parent\n", __func__, |
566 | parent_name); | |
567 | ||
568 | clk_put(parent); | |
3392cdd3 TKD |
569 | |
570 | return ret; | |
92105bb7 | 571 | } |
6c366e32 | 572 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); |
92105bb7 | 573 | |
ab4eb8b0 | 574 | int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, |
77900a2f | 575 | unsigned int load) |
92105bb7 TL |
576 | { |
577 | u32 l; | |
77900a2f | 578 | |
ab4eb8b0 TKD |
579 | if (unlikely(!timer)) |
580 | return -EINVAL; | |
581 | ||
b481113a | 582 | omap_dm_timer_enable(timer); |
92105bb7 | 583 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
584 | if (autoreload) |
585 | l |= OMAP_TIMER_CTRL_AR; | |
586 | else | |
587 | l &= ~OMAP_TIMER_CTRL_AR; | |
92105bb7 | 588 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
77900a2f | 589 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); |
0f0d0807 | 590 | |
77900a2f | 591 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
b481113a TKD |
592 | /* Save the context */ |
593 | timer->context.tclr = l; | |
594 | timer->context.tldr = load; | |
595 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 596 | return 0; |
92105bb7 | 597 | } |
6c366e32 | 598 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_load); |
92105bb7 | 599 | |
3fddd09e | 600 | /* Optimized set_load which removes costly spin wait in timer_start */ |
ab4eb8b0 | 601 | int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, |
3fddd09e RW |
602 | unsigned int load) |
603 | { | |
604 | u32 l; | |
605 | ||
ab4eb8b0 TKD |
606 | if (unlikely(!timer)) |
607 | return -EINVAL; | |
608 | ||
b481113a TKD |
609 | omap_dm_timer_enable(timer); |
610 | ||
3fddd09e | 611 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
64ce2907 | 612 | if (autoreload) { |
3fddd09e | 613 | l |= OMAP_TIMER_CTRL_AR; |
64ce2907 PW |
614 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); |
615 | } else { | |
3fddd09e | 616 | l &= ~OMAP_TIMER_CTRL_AR; |
64ce2907 | 617 | } |
3fddd09e RW |
618 | l |= OMAP_TIMER_CTRL_ST; |
619 | ||
ee17f114 | 620 | __omap_dm_timer_load_start(timer, l, load, timer->posted); |
b481113a TKD |
621 | |
622 | /* Save the context */ | |
623 | timer->context.tclr = l; | |
624 | timer->context.tldr = load; | |
625 | timer->context.tcrr = load; | |
ab4eb8b0 | 626 | return 0; |
3fddd09e | 627 | } |
6c366e32 | 628 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start); |
3fddd09e | 629 | |
ab4eb8b0 | 630 | int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, |
77900a2f | 631 | unsigned int match) |
92105bb7 TL |
632 | { |
633 | u32 l; | |
634 | ||
ab4eb8b0 TKD |
635 | if (unlikely(!timer)) |
636 | return -EINVAL; | |
637 | ||
b481113a | 638 | omap_dm_timer_enable(timer); |
92105bb7 | 639 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
83379c81 | 640 | if (enable) |
77900a2f TT |
641 | l |= OMAP_TIMER_CTRL_CE; |
642 | else | |
643 | l &= ~OMAP_TIMER_CTRL_CE; | |
77900a2f | 644 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); |
991ad16a | 645 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
646 | |
647 | /* Save the context */ | |
648 | timer->context.tclr = l; | |
649 | timer->context.tmar = match; | |
650 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 651 | return 0; |
92105bb7 | 652 | } |
6c366e32 | 653 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_match); |
92105bb7 | 654 | |
ab4eb8b0 | 655 | int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, |
77900a2f | 656 | int toggle, int trigger) |
92105bb7 TL |
657 | { |
658 | u32 l; | |
659 | ||
ab4eb8b0 TKD |
660 | if (unlikely(!timer)) |
661 | return -EINVAL; | |
662 | ||
b481113a | 663 | omap_dm_timer_enable(timer); |
92105bb7 | 664 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
665 | l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | |
666 | OMAP_TIMER_CTRL_PT | (0x03 << 10)); | |
667 | if (def_on) | |
668 | l |= OMAP_TIMER_CTRL_SCPWM; | |
669 | if (toggle) | |
670 | l |= OMAP_TIMER_CTRL_PT; | |
671 | l |= trigger << 10; | |
92105bb7 | 672 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
673 | |
674 | /* Save the context */ | |
675 | timer->context.tclr = l; | |
676 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 677 | return 0; |
92105bb7 | 678 | } |
6c366e32 | 679 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm); |
92105bb7 | 680 | |
ab4eb8b0 | 681 | int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler) |
92105bb7 TL |
682 | { |
683 | u32 l; | |
684 | ||
ab4eb8b0 TKD |
685 | if (unlikely(!timer)) |
686 | return -EINVAL; | |
687 | ||
b481113a | 688 | omap_dm_timer_enable(timer); |
92105bb7 | 689 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
690 | l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); |
691 | if (prescaler >= 0x00 && prescaler <= 0x07) { | |
692 | l |= OMAP_TIMER_CTRL_PRE; | |
693 | l |= prescaler << 2; | |
694 | } | |
92105bb7 | 695 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
696 | |
697 | /* Save the context */ | |
698 | timer->context.tclr = l; | |
699 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 700 | return 0; |
92105bb7 | 701 | } |
6c366e32 | 702 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler); |
92105bb7 | 703 | |
ab4eb8b0 | 704 | int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, |
77900a2f | 705 | unsigned int value) |
92105bb7 | 706 | { |
ab4eb8b0 TKD |
707 | if (unlikely(!timer)) |
708 | return -EINVAL; | |
709 | ||
b481113a | 710 | omap_dm_timer_enable(timer); |
ee17f114 | 711 | __omap_dm_timer_int_enable(timer, value); |
b481113a TKD |
712 | |
713 | /* Save the context */ | |
714 | timer->context.tier = value; | |
715 | timer->context.twer = value; | |
716 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 717 | return 0; |
92105bb7 | 718 | } |
6c366e32 | 719 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable); |
92105bb7 | 720 | |
4249d96c JH |
721 | /** |
722 | * omap_dm_timer_set_int_disable - disable timer interrupts | |
723 | * @timer: pointer to timer handle | |
724 | * @mask: bit mask of interrupts to be disabled | |
725 | * | |
726 | * Disables the specified timer interrupts for a timer. | |
727 | */ | |
728 | int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask) | |
729 | { | |
730 | u32 l = mask; | |
731 | ||
732 | if (unlikely(!timer)) | |
733 | return -EINVAL; | |
734 | ||
735 | omap_dm_timer_enable(timer); | |
736 | ||
737 | if (timer->revision == 1) | |
834cacfb | 738 | l = readl_relaxed(timer->irq_ena) & ~mask; |
4249d96c | 739 | |
834cacfb | 740 | writel_relaxed(l, timer->irq_dis); |
4249d96c JH |
741 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; |
742 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l); | |
743 | ||
744 | /* Save the context */ | |
745 | timer->context.tier &= ~mask; | |
746 | timer->context.twer &= ~mask; | |
747 | omap_dm_timer_disable(timer); | |
748 | return 0; | |
749 | } | |
750 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_disable); | |
751 | ||
77900a2f | 752 | unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) |
92105bb7 | 753 | { |
fa4bb626 TT |
754 | unsigned int l; |
755 | ||
ab4eb8b0 TKD |
756 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
757 | pr_err("%s: timer not available or enabled.\n", __func__); | |
b481113a TKD |
758 | return 0; |
759 | } | |
760 | ||
834cacfb | 761 | l = readl_relaxed(timer->irq_stat); |
fa4bb626 TT |
762 | |
763 | return l; | |
92105bb7 | 764 | } |
6c366e32 | 765 | EXPORT_SYMBOL_GPL(omap_dm_timer_read_status); |
92105bb7 | 766 | |
ab4eb8b0 | 767 | int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) |
92105bb7 | 768 | { |
ab4eb8b0 TKD |
769 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) |
770 | return -EINVAL; | |
771 | ||
ee17f114 | 772 | __omap_dm_timer_write_status(timer, value); |
1eaff710 | 773 | |
ab4eb8b0 | 774 | return 0; |
92105bb7 | 775 | } |
6c366e32 | 776 | EXPORT_SYMBOL_GPL(omap_dm_timer_write_status); |
92105bb7 | 777 | |
77900a2f | 778 | unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) |
92105bb7 | 779 | { |
ab4eb8b0 TKD |
780 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
781 | pr_err("%s: timer not iavailable or enabled.\n", __func__); | |
b481113a TKD |
782 | return 0; |
783 | } | |
784 | ||
ee17f114 | 785 | return __omap_dm_timer_read_counter(timer, timer->posted); |
92105bb7 | 786 | } |
6c366e32 | 787 | EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter); |
92105bb7 | 788 | |
ab4eb8b0 | 789 | int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) |
83379c81 | 790 | { |
ab4eb8b0 TKD |
791 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
792 | pr_err("%s: timer not available or enabled.\n", __func__); | |
793 | return -EINVAL; | |
b481113a TKD |
794 | } |
795 | ||
fa4bb626 | 796 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); |
b481113a TKD |
797 | |
798 | /* Save the context */ | |
799 | timer->context.tcrr = value; | |
ab4eb8b0 | 800 | return 0; |
83379c81 | 801 | } |
6c366e32 | 802 | EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter); |
83379c81 | 803 | |
77900a2f | 804 | int omap_dm_timers_active(void) |
92105bb7 | 805 | { |
3392cdd3 | 806 | struct omap_dm_timer *timer; |
12583a70 | 807 | |
3392cdd3 | 808 | list_for_each_entry(timer, &omap_timer_list, node) { |
ffe07cea | 809 | if (!timer->reserved) |
12583a70 TT |
810 | continue; |
811 | ||
77900a2f | 812 | if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & |
fa4bb626 | 813 | OMAP_TIMER_CTRL_ST) { |
77900a2f | 814 | return 1; |
fa4bb626 | 815 | } |
77900a2f TT |
816 | } |
817 | return 0; | |
818 | } | |
6c366e32 | 819 | EXPORT_SYMBOL_GPL(omap_dm_timers_active); |
92105bb7 | 820 | |
d1c6ccfe JH |
821 | static const struct of_device_id omap_timer_match[]; |
822 | ||
df28472a TKD |
823 | /** |
824 | * omap_dm_timer_probe - probe function called for every registered device | |
825 | * @pdev: pointer to current timer platform device | |
826 | * | |
827 | * Called by driver framework at the end of device registration for all | |
828 | * timer devices. | |
829 | */ | |
351a102d | 830 | static int omap_dm_timer_probe(struct platform_device *pdev) |
df28472a | 831 | { |
df28472a TKD |
832 | unsigned long flags; |
833 | struct omap_dm_timer *timer; | |
74dd9ec6 TKD |
834 | struct resource *mem, *irq; |
835 | struct device *dev = &pdev->dev; | |
d1c6ccfe JH |
836 | const struct of_device_id *match; |
837 | const struct dmtimer_platform_data *pdata; | |
a76fc9dd | 838 | int ret; |
d1c6ccfe JH |
839 | |
840 | match = of_match_device(of_match_ptr(omap_timer_match), dev); | |
841 | pdata = match ? match->data : dev->platform_data; | |
df28472a | 842 | |
9725f445 | 843 | if (!pdata && !dev->of_node) { |
74dd9ec6 | 844 | dev_err(dev, "%s: no platform data.\n", __func__); |
df28472a TKD |
845 | return -ENODEV; |
846 | } | |
847 | ||
848 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
849 | if (unlikely(!irq)) { | |
74dd9ec6 | 850 | dev_err(dev, "%s: no IRQ resource.\n", __func__); |
df28472a TKD |
851 | return -ENODEV; |
852 | } | |
853 | ||
854 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
855 | if (unlikely(!mem)) { | |
74dd9ec6 | 856 | dev_err(dev, "%s: no memory resource.\n", __func__); |
df28472a TKD |
857 | return -ENODEV; |
858 | } | |
859 | ||
74dd9ec6 | 860 | timer = devm_kzalloc(dev, sizeof(struct omap_dm_timer), GFP_KERNEL); |
df28472a | 861 | if (!timer) { |
74dd9ec6 TKD |
862 | dev_err(dev, "%s: memory alloc failed!\n", __func__); |
863 | return -ENOMEM; | |
df28472a TKD |
864 | } |
865 | ||
86287958 | 866 | timer->fclk = ERR_PTR(-ENODEV); |
5857bd98 TR |
867 | timer->io_base = devm_ioremap_resource(dev, mem); |
868 | if (IS_ERR(timer->io_base)) | |
869 | return PTR_ERR(timer->io_base); | |
df28472a | 870 | |
9725f445 JH |
871 | if (dev->of_node) { |
872 | if (of_find_property(dev->of_node, "ti,timer-alwon", NULL)) | |
873 | timer->capability |= OMAP_TIMER_ALWON; | |
874 | if (of_find_property(dev->of_node, "ti,timer-dsp", NULL)) | |
875 | timer->capability |= OMAP_TIMER_HAS_DSP_IRQ; | |
876 | if (of_find_property(dev->of_node, "ti,timer-pwm", NULL)) | |
877 | timer->capability |= OMAP_TIMER_HAS_PWM; | |
878 | if (of_find_property(dev->of_node, "ti,timer-secure", NULL)) | |
879 | timer->capability |= OMAP_TIMER_SECURE; | |
880 | } else { | |
881 | timer->id = pdev->id; | |
882 | timer->capability = pdata->timer_capability; | |
883 | timer->reserved = omap_dm_timer_reserved_systimer(timer->id); | |
f56f52e0 | 884 | timer->get_context_loss_count = pdata->get_context_loss_count; |
9725f445 JH |
885 | } |
886 | ||
d1c6ccfe JH |
887 | if (pdata) |
888 | timer->errata = pdata->timer_errata; | |
889 | ||
df28472a TKD |
890 | timer->irq = irq->start; |
891 | timer->pdev = pdev; | |
df28472a | 892 | |
ffe07cea | 893 | /* Skip pm_runtime_enable for OMAP1 */ |
6615975b | 894 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { |
74dd9ec6 TKD |
895 | pm_runtime_enable(dev); |
896 | pm_runtime_irq_safe(dev); | |
ffe07cea TKD |
897 | } |
898 | ||
0dad9fae | 899 | if (!timer->reserved) { |
a76fc9dd SA |
900 | ret = pm_runtime_get_sync(dev); |
901 | if (ret < 0) { | |
902 | dev_err(dev, "%s: pm_runtime_get_sync failed!\n", | |
903 | __func__); | |
904 | goto err_get_sync; | |
905 | } | |
0dad9fae | 906 | __omap_dm_timer_init_regs(timer); |
74dd9ec6 | 907 | pm_runtime_put(dev); |
0dad9fae TL |
908 | } |
909 | ||
df28472a TKD |
910 | /* add the timer element to the list */ |
911 | spin_lock_irqsave(&dm_timer_lock, flags); | |
912 | list_add_tail(&timer->node, &omap_timer_list); | |
913 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
914 | ||
74dd9ec6 | 915 | dev_dbg(dev, "Device Probed.\n"); |
df28472a TKD |
916 | |
917 | return 0; | |
a76fc9dd SA |
918 | |
919 | err_get_sync: | |
920 | pm_runtime_put_noidle(dev); | |
921 | pm_runtime_disable(dev); | |
922 | return ret; | |
df28472a TKD |
923 | } |
924 | ||
925 | /** | |
926 | * omap_dm_timer_remove - cleanup a registered timer device | |
927 | * @pdev: pointer to current timer platform device | |
928 | * | |
929 | * Called by driver framework whenever a timer device is unregistered. | |
930 | * In addition to freeing platform resources it also deletes the timer | |
931 | * entry from the local list. | |
932 | */ | |
351a102d | 933 | static int omap_dm_timer_remove(struct platform_device *pdev) |
df28472a TKD |
934 | { |
935 | struct omap_dm_timer *timer; | |
936 | unsigned long flags; | |
937 | int ret = -EINVAL; | |
938 | ||
939 | spin_lock_irqsave(&dm_timer_lock, flags); | |
940 | list_for_each_entry(timer, &omap_timer_list, node) | |
9725f445 JH |
941 | if (!strcmp(dev_name(&timer->pdev->dev), |
942 | dev_name(&pdev->dev))) { | |
df28472a | 943 | list_del(&timer->node); |
df28472a TKD |
944 | ret = 0; |
945 | break; | |
946 | } | |
947 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
948 | ||
51b7e572 SA |
949 | pm_runtime_disable(&pdev->dev); |
950 | ||
df28472a TKD |
951 | return ret; |
952 | } | |
953 | ||
d1c6ccfe JH |
954 | static const struct dmtimer_platform_data omap3plus_pdata = { |
955 | .timer_errata = OMAP_TIMER_ERRATA_I103_I767, | |
956 | }; | |
957 | ||
9725f445 | 958 | static const struct of_device_id omap_timer_match[] = { |
d1c6ccfe JH |
959 | { |
960 | .compatible = "ti,omap2420-timer", | |
961 | }, | |
962 | { | |
963 | .compatible = "ti,omap3430-timer", | |
964 | .data = &omap3plus_pdata, | |
965 | }, | |
966 | { | |
967 | .compatible = "ti,omap4430-timer", | |
968 | .data = &omap3plus_pdata, | |
969 | }, | |
970 | { | |
971 | .compatible = "ti,omap5430-timer", | |
972 | .data = &omap3plus_pdata, | |
973 | }, | |
974 | { | |
975 | .compatible = "ti,am335x-timer", | |
976 | .data = &omap3plus_pdata, | |
977 | }, | |
978 | { | |
979 | .compatible = "ti,am335x-timer-1ms", | |
980 | .data = &omap3plus_pdata, | |
981 | }, | |
8c0cabd7 NA |
982 | { |
983 | .compatible = "ti,dm816-timer", | |
984 | .data = &omap3plus_pdata, | |
985 | }, | |
9725f445 JH |
986 | {}, |
987 | }; | |
988 | MODULE_DEVICE_TABLE(of, omap_timer_match); | |
989 | ||
df28472a TKD |
990 | static struct platform_driver omap_dm_timer_driver = { |
991 | .probe = omap_dm_timer_probe, | |
351a102d | 992 | .remove = omap_dm_timer_remove, |
df28472a TKD |
993 | .driver = { |
994 | .name = "omap_timer", | |
9725f445 | 995 | .of_match_table = of_match_ptr(omap_timer_match), |
df28472a TKD |
996 | }, |
997 | }; | |
998 | ||
df28472a | 999 | early_platform_init("earlytimer", &omap_dm_timer_driver); |
e4e9f7ea | 1000 | module_platform_driver(omap_dm_timer_driver); |
df28472a TKD |
1001 | |
1002 | MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver"); | |
1003 | MODULE_LICENSE("GPL"); | |
1004 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
1005 | MODULE_AUTHOR("Texas Instruments Inc"); |