Commit | Line | Data |
---|---|---|
92105bb7 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/dmtimer.c | |
3 | * | |
4 | * OMAP Dual-Mode Timers | |
5 | * | |
97933d6c TKD |
6 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ |
7 | * Tarun Kanti DebBarma <tarun.kanti@ti.com> | |
8 | * Thara Gopinath <thara@ti.com> | |
9 | * | |
10 | * dmtimer adaptation to platform_driver. | |
11 | * | |
92105bb7 | 12 | * Copyright (C) 2005 Nokia Corporation |
77900a2f TT |
13 | * OMAP2 support by Juha Yrjola |
14 | * API improvements and OMAP2 clock framework support by Timo Teras | |
92105bb7 | 15 | * |
44169075 SS |
16 | * Copyright (C) 2009 Texas Instruments |
17 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
18 | * | |
92105bb7 TL |
19 | * This program is free software; you can redistribute it and/or modify it |
20 | * under the terms of the GNU General Public License as published by the | |
21 | * Free Software Foundation; either version 2 of the License, or (at your | |
22 | * option) any later version. | |
23 | * | |
24 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
25 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
26 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
27 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
28 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License along | |
34 | * with this program; if not, write to the Free Software Foundation, Inc., | |
35 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
36 | */ | |
37 | ||
869dec15 | 38 | #include <linux/module.h> |
fced80c7 | 39 | #include <linux/io.h> |
df28472a | 40 | #include <linux/slab.h> |
3392cdd3 | 41 | #include <linux/err.h> |
ffe07cea | 42 | #include <linux/pm_runtime.h> |
44169075 | 43 | |
3392cdd3 | 44 | #include <plat/dmtimer.h> |
471b3aa7 | 45 | |
2c799cef TL |
46 | #include <mach/hardware.h> |
47 | ||
b7b4ff76 | 48 | static u32 omap_reserved_systimers; |
df28472a | 49 | static LIST_HEAD(omap_timer_list); |
3392cdd3 | 50 | static DEFINE_SPINLOCK(dm_timer_lock); |
92105bb7 | 51 | |
3392cdd3 TKD |
52 | /** |
53 | * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode | |
54 | * @timer: timer pointer over which read operation to perform | |
55 | * @reg: lowest byte holds the register offset | |
56 | * | |
57 | * The posted mode bit is encoded in reg. Note that in posted mode write | |
58 | * pending bit must be checked. Otherwise a read of a non completed write | |
59 | * will produce an error. | |
0f0d0807 RW |
60 | */ |
61 | static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) | |
77900a2f | 62 | { |
ee17f114 TL |
63 | WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
64 | return __omap_dm_timer_read(timer, reg, timer->posted); | |
77900a2f | 65 | } |
92105bb7 | 66 | |
3392cdd3 TKD |
67 | /** |
68 | * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode | |
69 | * @timer: timer pointer over which write operation is to perform | |
70 | * @reg: lowest byte holds the register offset | |
71 | * @value: data to write into the register | |
72 | * | |
73 | * The posted mode bit is encoded in reg. Note that in posted mode the write | |
74 | * pending bit must be checked. Otherwise a write on a register which has a | |
75 | * pending write will be lost. | |
0f0d0807 RW |
76 | */ |
77 | static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, | |
78 | u32 value) | |
92105bb7 | 79 | { |
ee17f114 TL |
80 | WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
81 | __omap_dm_timer_write(timer, reg, value, timer->posted); | |
92105bb7 TL |
82 | } |
83 | ||
b481113a TKD |
84 | static void omap_timer_restore_context(struct omap_dm_timer *timer) |
85 | { | |
dffc9dae | 86 | if (timer->revision == 1) |
b481113a TKD |
87 | __raw_writel(timer->context.tistat, timer->sys_stat); |
88 | ||
89 | __raw_writel(timer->context.tisr, timer->irq_stat); | |
90 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, | |
91 | timer->context.twer); | |
92 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, | |
93 | timer->context.tcrr); | |
94 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, | |
95 | timer->context.tldr); | |
96 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, | |
97 | timer->context.tmar); | |
98 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, | |
99 | timer->context.tsicr); | |
100 | __raw_writel(timer->context.tier, timer->irq_ena); | |
101 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, | |
102 | timer->context.tclr); | |
103 | } | |
104 | ||
77900a2f | 105 | static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer) |
92105bb7 | 106 | { |
77900a2f TT |
107 | int c; |
108 | ||
ee17f114 TL |
109 | if (!timer->sys_stat) |
110 | return; | |
111 | ||
77900a2f | 112 | c = 0; |
ee17f114 | 113 | while (!(__raw_readl(timer->sys_stat) & 1)) { |
77900a2f TT |
114 | c++; |
115 | if (c > 100000) { | |
116 | printk(KERN_ERR "Timer failed to reset\n"); | |
117 | return; | |
118 | } | |
119 | } | |
92105bb7 TL |
120 | } |
121 | ||
77900a2f TT |
122 | static void omap_dm_timer_reset(struct omap_dm_timer *timer) |
123 | { | |
b481113a | 124 | omap_dm_timer_enable(timer); |
3392cdd3 | 125 | if (timer->pdev->id != 1) { |
e32f7ec2 TT |
126 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); |
127 | omap_dm_timer_wait_for_reset(timer); | |
128 | } | |
0f0d0807 | 129 | |
3392cdd3 | 130 | __omap_dm_timer_reset(timer, 0, 0); |
b481113a | 131 | omap_dm_timer_disable(timer); |
0f0d0807 | 132 | timer->posted = 1; |
77900a2f TT |
133 | } |
134 | ||
3392cdd3 | 135 | int omap_dm_timer_prepare(struct omap_dm_timer *timer) |
77900a2f | 136 | { |
3392cdd3 TKD |
137 | struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data; |
138 | int ret; | |
139 | ||
140 | timer->fclk = clk_get(&timer->pdev->dev, "fck"); | |
141 | if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) { | |
142 | timer->fclk = NULL; | |
143 | dev_err(&timer->pdev->dev, ": No fclk handle.\n"); | |
144 | return -EINVAL; | |
145 | } | |
146 | ||
3392cdd3 TKD |
147 | if (pdata->needs_manual_reset) |
148 | omap_dm_timer_reset(timer); | |
149 | ||
150 | ret = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); | |
151 | ||
152 | timer->posted = 1; | |
153 | return ret; | |
77900a2f TT |
154 | } |
155 | ||
b7b4ff76 JH |
156 | static inline u32 omap_dm_timer_reserved_systimer(int id) |
157 | { | |
158 | return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0; | |
159 | } | |
160 | ||
161 | int omap_dm_timer_reserve_systimer(int id) | |
162 | { | |
163 | if (omap_dm_timer_reserved_systimer(id)) | |
164 | return -ENODEV; | |
165 | ||
166 | omap_reserved_systimers |= (1 << (id - 1)); | |
167 | ||
168 | return 0; | |
169 | } | |
170 | ||
77900a2f TT |
171 | struct omap_dm_timer *omap_dm_timer_request(void) |
172 | { | |
3392cdd3 | 173 | struct omap_dm_timer *timer = NULL, *t; |
77900a2f | 174 | unsigned long flags; |
3392cdd3 | 175 | int ret = 0; |
77900a2f TT |
176 | |
177 | spin_lock_irqsave(&dm_timer_lock, flags); | |
3392cdd3 TKD |
178 | list_for_each_entry(t, &omap_timer_list, node) { |
179 | if (t->reserved) | |
77900a2f TT |
180 | continue; |
181 | ||
3392cdd3 | 182 | timer = t; |
83379c81 | 183 | timer->reserved = 1; |
77900a2f TT |
184 | break; |
185 | } | |
3392cdd3 TKD |
186 | |
187 | if (timer) { | |
188 | ret = omap_dm_timer_prepare(timer); | |
189 | if (ret) { | |
190 | timer->reserved = 0; | |
191 | timer = NULL; | |
192 | } | |
193 | } | |
77900a2f TT |
194 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
195 | ||
3392cdd3 TKD |
196 | if (!timer) |
197 | pr_debug("%s: timer request failed!\n", __func__); | |
83379c81 | 198 | |
77900a2f TT |
199 | return timer; |
200 | } | |
6c366e32 | 201 | EXPORT_SYMBOL_GPL(omap_dm_timer_request); |
77900a2f TT |
202 | |
203 | struct omap_dm_timer *omap_dm_timer_request_specific(int id) | |
92105bb7 | 204 | { |
3392cdd3 | 205 | struct omap_dm_timer *timer = NULL, *t; |
77900a2f | 206 | unsigned long flags; |
3392cdd3 | 207 | int ret = 0; |
92105bb7 | 208 | |
77900a2f | 209 | spin_lock_irqsave(&dm_timer_lock, flags); |
3392cdd3 TKD |
210 | list_for_each_entry(t, &omap_timer_list, node) { |
211 | if (t->pdev->id == id && !t->reserved) { | |
212 | timer = t; | |
213 | timer->reserved = 1; | |
214 | break; | |
215 | } | |
77900a2f | 216 | } |
92105bb7 | 217 | |
3392cdd3 TKD |
218 | if (timer) { |
219 | ret = omap_dm_timer_prepare(timer); | |
220 | if (ret) { | |
221 | timer->reserved = 0; | |
222 | timer = NULL; | |
223 | } | |
224 | } | |
77900a2f TT |
225 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
226 | ||
3392cdd3 TKD |
227 | if (!timer) |
228 | pr_debug("%s: timer%d request failed!\n", __func__, id); | |
83379c81 | 229 | |
77900a2f | 230 | return timer; |
92105bb7 | 231 | } |
6c366e32 | 232 | EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific); |
92105bb7 | 233 | |
ab4eb8b0 | 234 | int omap_dm_timer_free(struct omap_dm_timer *timer) |
77900a2f | 235 | { |
ab4eb8b0 TKD |
236 | if (unlikely(!timer)) |
237 | return -EINVAL; | |
238 | ||
3392cdd3 | 239 | clk_put(timer->fclk); |
fa4bb626 | 240 | |
77900a2f TT |
241 | WARN_ON(!timer->reserved); |
242 | timer->reserved = 0; | |
ab4eb8b0 | 243 | return 0; |
77900a2f | 244 | } |
6c366e32 | 245 | EXPORT_SYMBOL_GPL(omap_dm_timer_free); |
77900a2f | 246 | |
12583a70 TT |
247 | void omap_dm_timer_enable(struct omap_dm_timer *timer) |
248 | { | |
ffe07cea | 249 | pm_runtime_get_sync(&timer->pdev->dev); |
12583a70 | 250 | } |
6c366e32 | 251 | EXPORT_SYMBOL_GPL(omap_dm_timer_enable); |
12583a70 TT |
252 | |
253 | void omap_dm_timer_disable(struct omap_dm_timer *timer) | |
254 | { | |
ffe07cea | 255 | pm_runtime_put(&timer->pdev->dev); |
12583a70 | 256 | } |
6c366e32 | 257 | EXPORT_SYMBOL_GPL(omap_dm_timer_disable); |
12583a70 | 258 | |
77900a2f TT |
259 | int omap_dm_timer_get_irq(struct omap_dm_timer *timer) |
260 | { | |
ab4eb8b0 TKD |
261 | if (timer) |
262 | return timer->irq; | |
263 | return -EINVAL; | |
77900a2f | 264 | } |
6c366e32 | 265 | EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq); |
77900a2f TT |
266 | |
267 | #if defined(CONFIG_ARCH_OMAP1) | |
268 | ||
a569c6ec TL |
269 | /** |
270 | * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR | |
271 | * @inputmask: current value of idlect mask | |
272 | */ | |
273 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) | |
274 | { | |
3392cdd3 TKD |
275 | int i = 0; |
276 | struct omap_dm_timer *timer = NULL; | |
277 | unsigned long flags; | |
a569c6ec TL |
278 | |
279 | /* If ARMXOR cannot be idled this function call is unnecessary */ | |
280 | if (!(inputmask & (1 << 1))) | |
281 | return inputmask; | |
282 | ||
283 | /* If any active timer is using ARMXOR return modified mask */ | |
3392cdd3 TKD |
284 | spin_lock_irqsave(&dm_timer_lock, flags); |
285 | list_for_each_entry(timer, &omap_timer_list, node) { | |
77900a2f TT |
286 | u32 l; |
287 | ||
3392cdd3 | 288 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
289 | if (l & OMAP_TIMER_CTRL_ST) { |
290 | if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0) | |
a569c6ec TL |
291 | inputmask &= ~(1 << 1); |
292 | else | |
293 | inputmask &= ~(1 << 2); | |
294 | } | |
3392cdd3 | 295 | i++; |
77900a2f | 296 | } |
3392cdd3 | 297 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
a569c6ec TL |
298 | |
299 | return inputmask; | |
300 | } | |
6c366e32 | 301 | EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); |
a569c6ec | 302 | |
140455fa | 303 | #else |
a569c6ec | 304 | |
77900a2f | 305 | struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) |
92105bb7 | 306 | { |
ab4eb8b0 TKD |
307 | if (timer) |
308 | return timer->fclk; | |
309 | return NULL; | |
77900a2f | 310 | } |
6c366e32 | 311 | EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk); |
92105bb7 | 312 | |
77900a2f TT |
313 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) |
314 | { | |
315 | BUG(); | |
2121880e DB |
316 | |
317 | return 0; | |
92105bb7 | 318 | } |
6c366e32 | 319 | EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); |
92105bb7 | 320 | |
77900a2f | 321 | #endif |
92105bb7 | 322 | |
ab4eb8b0 | 323 | int omap_dm_timer_trigger(struct omap_dm_timer *timer) |
92105bb7 | 324 | { |
ab4eb8b0 TKD |
325 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
326 | pr_err("%s: timer not available or enabled.\n", __func__); | |
327 | return -EINVAL; | |
b481113a TKD |
328 | } |
329 | ||
77900a2f | 330 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
ab4eb8b0 | 331 | return 0; |
92105bb7 | 332 | } |
6c366e32 | 333 | EXPORT_SYMBOL_GPL(omap_dm_timer_trigger); |
92105bb7 | 334 | |
ab4eb8b0 | 335 | int omap_dm_timer_start(struct omap_dm_timer *timer) |
77900a2f TT |
336 | { |
337 | u32 l; | |
92105bb7 | 338 | |
ab4eb8b0 TKD |
339 | if (unlikely(!timer)) |
340 | return -EINVAL; | |
341 | ||
b481113a TKD |
342 | omap_dm_timer_enable(timer); |
343 | ||
1c2d076b | 344 | if (!(timer->capability & OMAP_TIMER_ALWON)) { |
b481113a TKD |
345 | u32 ctx_loss_cnt_after = |
346 | timer->get_context_loss_count(&timer->pdev->dev); | |
347 | if (ctx_loss_cnt_after != timer->ctx_loss_count) | |
348 | omap_timer_restore_context(timer); | |
349 | } | |
350 | ||
77900a2f TT |
351 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
352 | if (!(l & OMAP_TIMER_CTRL_ST)) { | |
353 | l |= OMAP_TIMER_CTRL_ST; | |
354 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | |
355 | } | |
b481113a TKD |
356 | |
357 | /* Save the context */ | |
358 | timer->context.tclr = l; | |
ab4eb8b0 | 359 | return 0; |
77900a2f | 360 | } |
6c366e32 | 361 | EXPORT_SYMBOL_GPL(omap_dm_timer_start); |
92105bb7 | 362 | |
ab4eb8b0 | 363 | int omap_dm_timer_stop(struct omap_dm_timer *timer) |
92105bb7 | 364 | { |
caf64f2f | 365 | unsigned long rate = 0; |
eeb3711b | 366 | struct dmtimer_platform_data *pdata; |
92105bb7 | 367 | |
ab4eb8b0 TKD |
368 | if (unlikely(!timer)) |
369 | return -EINVAL; | |
370 | ||
eeb3711b | 371 | pdata = timer->pdev->dev.platform_data; |
3392cdd3 TKD |
372 | if (!pdata->needs_manual_reset) |
373 | rate = clk_get_rate(timer->fclk); | |
caf64f2f | 374 | |
ee17f114 | 375 | __omap_dm_timer_stop(timer, timer->posted, rate); |
ab4eb8b0 | 376 | |
1c2d076b JH |
377 | if (!(timer->capability & OMAP_TIMER_ALWON) && |
378 | timer->get_context_loss_count) | |
dffc9dae TKD |
379 | timer->ctx_loss_count = |
380 | timer->get_context_loss_count(&timer->pdev->dev); | |
381 | ||
382 | /* | |
383 | * Since the register values are computed and written within | |
384 | * __omap_dm_timer_stop, we need to use read to retrieve the | |
385 | * context. | |
386 | */ | |
387 | timer->context.tclr = | |
388 | omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); | |
389 | timer->context.tisr = __raw_readl(timer->irq_stat); | |
390 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 391 | return 0; |
92105bb7 | 392 | } |
6c366e32 | 393 | EXPORT_SYMBOL_GPL(omap_dm_timer_stop); |
92105bb7 | 394 | |
f248076c | 395 | int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) |
92105bb7 | 396 | { |
3392cdd3 | 397 | int ret; |
ab4eb8b0 TKD |
398 | struct dmtimer_platform_data *pdata; |
399 | ||
400 | if (unlikely(!timer)) | |
401 | return -EINVAL; | |
402 | ||
403 | pdata = timer->pdev->dev.platform_data; | |
3392cdd3 | 404 | |
77900a2f | 405 | if (source < 0 || source >= 3) |
f248076c | 406 | return -EINVAL; |
77900a2f | 407 | |
3392cdd3 | 408 | ret = pdata->set_timer_src(timer->pdev, source); |
3392cdd3 TKD |
409 | |
410 | return ret; | |
92105bb7 | 411 | } |
6c366e32 | 412 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); |
92105bb7 | 413 | |
ab4eb8b0 | 414 | int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, |
77900a2f | 415 | unsigned int load) |
92105bb7 TL |
416 | { |
417 | u32 l; | |
77900a2f | 418 | |
ab4eb8b0 TKD |
419 | if (unlikely(!timer)) |
420 | return -EINVAL; | |
421 | ||
b481113a | 422 | omap_dm_timer_enable(timer); |
92105bb7 | 423 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
424 | if (autoreload) |
425 | l |= OMAP_TIMER_CTRL_AR; | |
426 | else | |
427 | l &= ~OMAP_TIMER_CTRL_AR; | |
92105bb7 | 428 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
77900a2f | 429 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); |
0f0d0807 | 430 | |
77900a2f | 431 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
b481113a TKD |
432 | /* Save the context */ |
433 | timer->context.tclr = l; | |
434 | timer->context.tldr = load; | |
435 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 436 | return 0; |
92105bb7 | 437 | } |
6c366e32 | 438 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_load); |
92105bb7 | 439 | |
3fddd09e | 440 | /* Optimized set_load which removes costly spin wait in timer_start */ |
ab4eb8b0 | 441 | int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, |
3fddd09e RW |
442 | unsigned int load) |
443 | { | |
444 | u32 l; | |
445 | ||
ab4eb8b0 TKD |
446 | if (unlikely(!timer)) |
447 | return -EINVAL; | |
448 | ||
b481113a TKD |
449 | omap_dm_timer_enable(timer); |
450 | ||
1c2d076b | 451 | if (!(timer->capability & OMAP_TIMER_ALWON)) { |
b481113a TKD |
452 | u32 ctx_loss_cnt_after = |
453 | timer->get_context_loss_count(&timer->pdev->dev); | |
454 | if (ctx_loss_cnt_after != timer->ctx_loss_count) | |
455 | omap_timer_restore_context(timer); | |
456 | } | |
457 | ||
3fddd09e | 458 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
64ce2907 | 459 | if (autoreload) { |
3fddd09e | 460 | l |= OMAP_TIMER_CTRL_AR; |
64ce2907 PW |
461 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); |
462 | } else { | |
3fddd09e | 463 | l &= ~OMAP_TIMER_CTRL_AR; |
64ce2907 | 464 | } |
3fddd09e RW |
465 | l |= OMAP_TIMER_CTRL_ST; |
466 | ||
ee17f114 | 467 | __omap_dm_timer_load_start(timer, l, load, timer->posted); |
b481113a TKD |
468 | |
469 | /* Save the context */ | |
470 | timer->context.tclr = l; | |
471 | timer->context.tldr = load; | |
472 | timer->context.tcrr = load; | |
ab4eb8b0 | 473 | return 0; |
3fddd09e | 474 | } |
6c366e32 | 475 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start); |
3fddd09e | 476 | |
ab4eb8b0 | 477 | int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, |
77900a2f | 478 | unsigned int match) |
92105bb7 TL |
479 | { |
480 | u32 l; | |
481 | ||
ab4eb8b0 TKD |
482 | if (unlikely(!timer)) |
483 | return -EINVAL; | |
484 | ||
b481113a | 485 | omap_dm_timer_enable(timer); |
92105bb7 | 486 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
83379c81 | 487 | if (enable) |
77900a2f TT |
488 | l |= OMAP_TIMER_CTRL_CE; |
489 | else | |
490 | l &= ~OMAP_TIMER_CTRL_CE; | |
92105bb7 | 491 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
77900a2f | 492 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); |
b481113a TKD |
493 | |
494 | /* Save the context */ | |
495 | timer->context.tclr = l; | |
496 | timer->context.tmar = match; | |
497 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 498 | return 0; |
92105bb7 | 499 | } |
6c366e32 | 500 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_match); |
92105bb7 | 501 | |
ab4eb8b0 | 502 | int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, |
77900a2f | 503 | int toggle, int trigger) |
92105bb7 TL |
504 | { |
505 | u32 l; | |
506 | ||
ab4eb8b0 TKD |
507 | if (unlikely(!timer)) |
508 | return -EINVAL; | |
509 | ||
b481113a | 510 | omap_dm_timer_enable(timer); |
92105bb7 | 511 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
512 | l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | |
513 | OMAP_TIMER_CTRL_PT | (0x03 << 10)); | |
514 | if (def_on) | |
515 | l |= OMAP_TIMER_CTRL_SCPWM; | |
516 | if (toggle) | |
517 | l |= OMAP_TIMER_CTRL_PT; | |
518 | l |= trigger << 10; | |
92105bb7 | 519 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
520 | |
521 | /* Save the context */ | |
522 | timer->context.tclr = l; | |
523 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 524 | return 0; |
92105bb7 | 525 | } |
6c366e32 | 526 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm); |
92105bb7 | 527 | |
ab4eb8b0 | 528 | int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler) |
92105bb7 TL |
529 | { |
530 | u32 l; | |
531 | ||
ab4eb8b0 TKD |
532 | if (unlikely(!timer)) |
533 | return -EINVAL; | |
534 | ||
b481113a | 535 | omap_dm_timer_enable(timer); |
92105bb7 | 536 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
537 | l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); |
538 | if (prescaler >= 0x00 && prescaler <= 0x07) { | |
539 | l |= OMAP_TIMER_CTRL_PRE; | |
540 | l |= prescaler << 2; | |
541 | } | |
92105bb7 | 542 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
543 | |
544 | /* Save the context */ | |
545 | timer->context.tclr = l; | |
546 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 547 | return 0; |
92105bb7 | 548 | } |
6c366e32 | 549 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler); |
92105bb7 | 550 | |
ab4eb8b0 | 551 | int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, |
77900a2f | 552 | unsigned int value) |
92105bb7 | 553 | { |
ab4eb8b0 TKD |
554 | if (unlikely(!timer)) |
555 | return -EINVAL; | |
556 | ||
b481113a | 557 | omap_dm_timer_enable(timer); |
ee17f114 | 558 | __omap_dm_timer_int_enable(timer, value); |
b481113a TKD |
559 | |
560 | /* Save the context */ | |
561 | timer->context.tier = value; | |
562 | timer->context.twer = value; | |
563 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 564 | return 0; |
92105bb7 | 565 | } |
6c366e32 | 566 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable); |
92105bb7 | 567 | |
77900a2f | 568 | unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) |
92105bb7 | 569 | { |
fa4bb626 TT |
570 | unsigned int l; |
571 | ||
ab4eb8b0 TKD |
572 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
573 | pr_err("%s: timer not available or enabled.\n", __func__); | |
b481113a TKD |
574 | return 0; |
575 | } | |
576 | ||
ee17f114 | 577 | l = __raw_readl(timer->irq_stat); |
fa4bb626 TT |
578 | |
579 | return l; | |
92105bb7 | 580 | } |
6c366e32 | 581 | EXPORT_SYMBOL_GPL(omap_dm_timer_read_status); |
92105bb7 | 582 | |
ab4eb8b0 | 583 | int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) |
92105bb7 | 584 | { |
ab4eb8b0 TKD |
585 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) |
586 | return -EINVAL; | |
587 | ||
ee17f114 | 588 | __omap_dm_timer_write_status(timer, value); |
b481113a TKD |
589 | /* Save the context */ |
590 | timer->context.tisr = value; | |
ab4eb8b0 | 591 | return 0; |
92105bb7 | 592 | } |
6c366e32 | 593 | EXPORT_SYMBOL_GPL(omap_dm_timer_write_status); |
92105bb7 | 594 | |
77900a2f | 595 | unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) |
92105bb7 | 596 | { |
ab4eb8b0 TKD |
597 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
598 | pr_err("%s: timer not iavailable or enabled.\n", __func__); | |
b481113a TKD |
599 | return 0; |
600 | } | |
601 | ||
ee17f114 | 602 | return __omap_dm_timer_read_counter(timer, timer->posted); |
92105bb7 | 603 | } |
6c366e32 | 604 | EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter); |
92105bb7 | 605 | |
ab4eb8b0 | 606 | int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) |
83379c81 | 607 | { |
ab4eb8b0 TKD |
608 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
609 | pr_err("%s: timer not available or enabled.\n", __func__); | |
610 | return -EINVAL; | |
b481113a TKD |
611 | } |
612 | ||
fa4bb626 | 613 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); |
b481113a TKD |
614 | |
615 | /* Save the context */ | |
616 | timer->context.tcrr = value; | |
ab4eb8b0 | 617 | return 0; |
83379c81 | 618 | } |
6c366e32 | 619 | EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter); |
83379c81 | 620 | |
77900a2f | 621 | int omap_dm_timers_active(void) |
92105bb7 | 622 | { |
3392cdd3 | 623 | struct omap_dm_timer *timer; |
12583a70 | 624 | |
3392cdd3 | 625 | list_for_each_entry(timer, &omap_timer_list, node) { |
ffe07cea | 626 | if (!timer->reserved) |
12583a70 TT |
627 | continue; |
628 | ||
77900a2f | 629 | if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & |
fa4bb626 | 630 | OMAP_TIMER_CTRL_ST) { |
77900a2f | 631 | return 1; |
fa4bb626 | 632 | } |
77900a2f TT |
633 | } |
634 | return 0; | |
635 | } | |
6c366e32 | 636 | EXPORT_SYMBOL_GPL(omap_dm_timers_active); |
92105bb7 | 637 | |
df28472a TKD |
638 | /** |
639 | * omap_dm_timer_probe - probe function called for every registered device | |
640 | * @pdev: pointer to current timer platform device | |
641 | * | |
642 | * Called by driver framework at the end of device registration for all | |
643 | * timer devices. | |
644 | */ | |
645 | static int __devinit omap_dm_timer_probe(struct platform_device *pdev) | |
646 | { | |
647 | int ret; | |
648 | unsigned long flags; | |
649 | struct omap_dm_timer *timer; | |
650 | struct resource *mem, *irq, *ioarea; | |
651 | struct dmtimer_platform_data *pdata = pdev->dev.platform_data; | |
652 | ||
653 | if (!pdata) { | |
654 | dev_err(&pdev->dev, "%s: no platform data.\n", __func__); | |
655 | return -ENODEV; | |
656 | } | |
657 | ||
658 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
659 | if (unlikely(!irq)) { | |
660 | dev_err(&pdev->dev, "%s: no IRQ resource.\n", __func__); | |
661 | return -ENODEV; | |
662 | } | |
663 | ||
664 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
665 | if (unlikely(!mem)) { | |
666 | dev_err(&pdev->dev, "%s: no memory resource.\n", __func__); | |
667 | return -ENODEV; | |
668 | } | |
669 | ||
670 | ioarea = request_mem_region(mem->start, resource_size(mem), | |
671 | pdev->name); | |
672 | if (!ioarea) { | |
673 | dev_err(&pdev->dev, "%s: region already claimed.\n", __func__); | |
674 | return -EBUSY; | |
675 | } | |
676 | ||
677 | timer = kzalloc(sizeof(struct omap_dm_timer), GFP_KERNEL); | |
678 | if (!timer) { | |
679 | dev_err(&pdev->dev, "%s: no memory for omap_dm_timer.\n", | |
680 | __func__); | |
681 | ret = -ENOMEM; | |
682 | goto err_free_ioregion; | |
683 | } | |
684 | ||
685 | timer->io_base = ioremap(mem->start, resource_size(mem)); | |
686 | if (!timer->io_base) { | |
687 | dev_err(&pdev->dev, "%s: ioremap failed.\n", __func__); | |
688 | ret = -ENOMEM; | |
689 | goto err_free_mem; | |
690 | } | |
691 | ||
692 | timer->id = pdev->id; | |
693 | timer->irq = irq->start; | |
b7b4ff76 | 694 | timer->reserved = omap_dm_timer_reserved_systimer(timer->id); |
df28472a | 695 | timer->pdev = pdev; |
b481113a | 696 | timer->get_context_loss_count = pdata->get_context_loss_count; |
d1c1691b | 697 | timer->capability = pdata->timer_capability; |
df28472a | 698 | |
ffe07cea TKD |
699 | /* Skip pm_runtime_enable for OMAP1 */ |
700 | if (!pdata->needs_manual_reset) { | |
701 | pm_runtime_enable(&pdev->dev); | |
702 | pm_runtime_irq_safe(&pdev->dev); | |
703 | } | |
704 | ||
0dad9fae TL |
705 | if (!timer->reserved) { |
706 | pm_runtime_get_sync(&pdev->dev); | |
707 | __omap_dm_timer_init_regs(timer); | |
708 | pm_runtime_put(&pdev->dev); | |
709 | } | |
710 | ||
df28472a TKD |
711 | /* add the timer element to the list */ |
712 | spin_lock_irqsave(&dm_timer_lock, flags); | |
713 | list_add_tail(&timer->node, &omap_timer_list); | |
714 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
715 | ||
716 | dev_dbg(&pdev->dev, "Device Probed.\n"); | |
717 | ||
718 | return 0; | |
719 | ||
720 | err_free_mem: | |
721 | kfree(timer); | |
722 | ||
723 | err_free_ioregion: | |
724 | release_mem_region(mem->start, resource_size(mem)); | |
725 | ||
726 | return ret; | |
727 | } | |
728 | ||
729 | /** | |
730 | * omap_dm_timer_remove - cleanup a registered timer device | |
731 | * @pdev: pointer to current timer platform device | |
732 | * | |
733 | * Called by driver framework whenever a timer device is unregistered. | |
734 | * In addition to freeing platform resources it also deletes the timer | |
735 | * entry from the local list. | |
736 | */ | |
737 | static int __devexit omap_dm_timer_remove(struct platform_device *pdev) | |
738 | { | |
739 | struct omap_dm_timer *timer; | |
740 | unsigned long flags; | |
741 | int ret = -EINVAL; | |
742 | ||
743 | spin_lock_irqsave(&dm_timer_lock, flags); | |
744 | list_for_each_entry(timer, &omap_timer_list, node) | |
745 | if (timer->pdev->id == pdev->id) { | |
746 | list_del(&timer->node); | |
747 | kfree(timer); | |
748 | ret = 0; | |
749 | break; | |
750 | } | |
751 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
752 | ||
753 | return ret; | |
754 | } | |
755 | ||
756 | static struct platform_driver omap_dm_timer_driver = { | |
757 | .probe = omap_dm_timer_probe, | |
4c23c8da | 758 | .remove = __devexit_p(omap_dm_timer_remove), |
df28472a TKD |
759 | .driver = { |
760 | .name = "omap_timer", | |
761 | }, | |
762 | }; | |
763 | ||
764 | static int __init omap_dm_timer_driver_init(void) | |
765 | { | |
766 | return platform_driver_register(&omap_dm_timer_driver); | |
767 | } | |
768 | ||
769 | static void __exit omap_dm_timer_driver_exit(void) | |
770 | { | |
771 | platform_driver_unregister(&omap_dm_timer_driver); | |
772 | } | |
773 | ||
774 | early_platform_init("earlytimer", &omap_dm_timer_driver); | |
775 | module_init(omap_dm_timer_driver_init); | |
776 | module_exit(omap_dm_timer_driver_exit); | |
777 | ||
778 | MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver"); | |
779 | MODULE_LICENSE("GPL"); | |
780 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
781 | MODULE_AUTHOR("Texas Instruments Inc"); |