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92105bb7 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/dmtimer.c | |
3 | * | |
4 | * OMAP Dual-Mode Timers | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
77900a2f TT |
7 | * OMAP2 support by Juha Yrjola |
8 | * API improvements and OMAP2 clock framework support by Timo Teras | |
92105bb7 TL |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the | |
12 | * Free Software Foundation; either version 2 of the License, or (at your | |
13 | * option) any later version. | |
14 | * | |
15 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
16 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
17 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
18 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License along | |
25 | * with this program; if not, write to the Free Software Foundation, Inc., | |
26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
27 | */ | |
28 | ||
29 | #include <linux/init.h> | |
77900a2f TT |
30 | #include <linux/spinlock.h> |
31 | #include <linux/errno.h> | |
32 | #include <linux/list.h> | |
33 | #include <linux/clk.h> | |
34 | #include <linux/delay.h> | |
fced80c7 | 35 | #include <linux/io.h> |
6c366e32 | 36 | #include <linux/module.h> |
a09e64fb RK |
37 | #include <mach/hardware.h> |
38 | #include <mach/dmtimer.h> | |
a09e64fb | 39 | #include <mach/irqs.h> |
92105bb7 | 40 | |
77900a2f | 41 | /* register offsets */ |
0f0d0807 RW |
42 | #define _OMAP_TIMER_ID_OFFSET 0x00 |
43 | #define _OMAP_TIMER_OCP_CFG_OFFSET 0x10 | |
44 | #define _OMAP_TIMER_SYS_STAT_OFFSET 0x14 | |
45 | #define _OMAP_TIMER_STAT_OFFSET 0x18 | |
46 | #define _OMAP_TIMER_INT_EN_OFFSET 0x1c | |
47 | #define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20 | |
48 | #define _OMAP_TIMER_CTRL_OFFSET 0x24 | |
49 | #define OMAP_TIMER_CTRL_GPOCFG (1 << 14) | |
50 | #define OMAP_TIMER_CTRL_CAPTMODE (1 << 13) | |
51 | #define OMAP_TIMER_CTRL_PT (1 << 12) | |
52 | #define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8) | |
53 | #define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8) | |
54 | #define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8) | |
55 | #define OMAP_TIMER_CTRL_SCPWM (1 << 7) | |
56 | #define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */ | |
57 | #define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */ | |
58 | #define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */ | |
59 | #define OMAP_TIMER_CTRL_POSTED (1 << 2) | |
60 | #define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */ | |
61 | #define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */ | |
62 | #define _OMAP_TIMER_COUNTER_OFFSET 0x28 | |
63 | #define _OMAP_TIMER_LOAD_OFFSET 0x2c | |
64 | #define _OMAP_TIMER_TRIGGER_OFFSET 0x30 | |
65 | #define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34 | |
66 | #define WP_NONE 0 /* no write pending bit */ | |
67 | #define WP_TCLR (1 << 0) | |
68 | #define WP_TCRR (1 << 1) | |
69 | #define WP_TLDR (1 << 2) | |
70 | #define WP_TTGR (1 << 3) | |
71 | #define WP_TMAR (1 << 4) | |
72 | #define WP_TPIR (1 << 5) | |
73 | #define WP_TNIR (1 << 6) | |
74 | #define WP_TCVR (1 << 7) | |
75 | #define WP_TOCR (1 << 8) | |
76 | #define WP_TOWR (1 << 9) | |
77 | #define _OMAP_TIMER_MATCH_OFFSET 0x38 | |
78 | #define _OMAP_TIMER_CAPTURE_OFFSET 0x3c | |
79 | #define _OMAP_TIMER_IF_CTRL_OFFSET 0x40 | |
80 | #define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */ | |
81 | #define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */ | |
82 | #define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */ | |
83 | #define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */ | |
84 | #define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */ | |
85 | #define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */ | |
86 | ||
87 | /* register offsets with the write pending bit encoded */ | |
88 | #define WPSHIFT 16 | |
89 | ||
90 | #define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \ | |
91 | | (WP_NONE << WPSHIFT)) | |
92 | ||
93 | #define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \ | |
94 | | (WP_NONE << WPSHIFT)) | |
95 | ||
96 | #define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \ | |
97 | | (WP_NONE << WPSHIFT)) | |
98 | ||
99 | #define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \ | |
100 | | (WP_NONE << WPSHIFT)) | |
101 | ||
102 | #define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \ | |
103 | | (WP_NONE << WPSHIFT)) | |
104 | ||
105 | #define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \ | |
106 | | (WP_NONE << WPSHIFT)) | |
107 | ||
108 | #define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \ | |
109 | | (WP_TCLR << WPSHIFT)) | |
110 | ||
111 | #define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \ | |
112 | | (WP_TCRR << WPSHIFT)) | |
113 | ||
114 | #define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \ | |
115 | | (WP_TLDR << WPSHIFT)) | |
116 | ||
117 | #define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \ | |
118 | | (WP_TTGR << WPSHIFT)) | |
119 | ||
120 | #define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \ | |
121 | | (WP_NONE << WPSHIFT)) | |
122 | ||
123 | #define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \ | |
124 | | (WP_TMAR << WPSHIFT)) | |
125 | ||
126 | #define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \ | |
127 | | (WP_NONE << WPSHIFT)) | |
128 | ||
129 | #define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \ | |
130 | | (WP_NONE << WPSHIFT)) | |
131 | ||
132 | #define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \ | |
133 | | (WP_NONE << WPSHIFT)) | |
134 | ||
135 | #define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \ | |
136 | | (WP_TPIR << WPSHIFT)) | |
137 | ||
138 | #define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \ | |
139 | | (WP_TNIR << WPSHIFT)) | |
140 | ||
141 | #define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \ | |
142 | | (WP_TCVR << WPSHIFT)) | |
143 | ||
144 | #define OMAP_TIMER_TICK_INT_MASK_SET_REG \ | |
145 | (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT)) | |
146 | ||
147 | #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \ | |
148 | (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT)) | |
77900a2f TT |
149 | |
150 | struct omap_dm_timer { | |
151 | unsigned long phys_base; | |
152 | int irq; | |
ce2df9ca | 153 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
77900a2f TT |
154 | struct clk *iclk, *fclk; |
155 | #endif | |
156 | void __iomem *io_base; | |
157 | unsigned reserved:1; | |
12583a70 | 158 | unsigned enabled:1; |
0f0d0807 | 159 | unsigned posted:1; |
77900a2f TT |
160 | }; |
161 | ||
162 | #ifdef CONFIG_ARCH_OMAP1 | |
163 | ||
fa4bb626 TT |
164 | #define omap_dm_clk_enable(x) |
165 | #define omap_dm_clk_disable(x) | |
471b3aa7 SMK |
166 | #define omap2_dm_timers NULL |
167 | #define omap2_dm_source_names NULL | |
168 | #define omap2_dm_source_clocks NULL | |
ce2df9ca SMK |
169 | #define omap3_dm_timers NULL |
170 | #define omap3_dm_source_names NULL | |
171 | #define omap3_dm_source_clocks NULL | |
fa4bb626 | 172 | |
471b3aa7 | 173 | static struct omap_dm_timer omap1_dm_timers[] = { |
77900a2f TT |
174 | { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 }, |
175 | { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 }, | |
176 | { .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 }, | |
177 | { .phys_base = 0xfffb2c00, .irq = INT_1610_GPTIMER4 }, | |
178 | { .phys_base = 0xfffb3400, .irq = INT_1610_GPTIMER5 }, | |
179 | { .phys_base = 0xfffb3c00, .irq = INT_1610_GPTIMER6 }, | |
53037f4c MP |
180 | { .phys_base = 0xfffb7400, .irq = INT_1610_GPTIMER7 }, |
181 | { .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 }, | |
77900a2f | 182 | }; |
92105bb7 | 183 | |
471b3aa7 SMK |
184 | static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers); |
185 | ||
77900a2f | 186 | #elif defined(CONFIG_ARCH_OMAP2) |
92105bb7 | 187 | |
471b3aa7 SMK |
188 | #define omap_dm_clk_enable(x) clk_enable(x) |
189 | #define omap_dm_clk_disable(x) clk_disable(x) | |
190 | #define omap1_dm_timers NULL | |
ce2df9ca SMK |
191 | #define omap3_dm_timers NULL |
192 | #define omap3_dm_source_names NULL | |
193 | #define omap3_dm_source_clocks NULL | |
fa4bb626 | 194 | |
471b3aa7 | 195 | static struct omap_dm_timer omap2_dm_timers[] = { |
77900a2f TT |
196 | { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 }, |
197 | { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 }, | |
198 | { .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 }, | |
199 | { .phys_base = 0x4807a000, .irq = INT_24XX_GPTIMER4 }, | |
200 | { .phys_base = 0x4807c000, .irq = INT_24XX_GPTIMER5 }, | |
201 | { .phys_base = 0x4807e000, .irq = INT_24XX_GPTIMER6 }, | |
202 | { .phys_base = 0x48080000, .irq = INT_24XX_GPTIMER7 }, | |
203 | { .phys_base = 0x48082000, .irq = INT_24XX_GPTIMER8 }, | |
204 | { .phys_base = 0x48084000, .irq = INT_24XX_GPTIMER9 }, | |
205 | { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 }, | |
206 | { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 }, | |
207 | { .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 }, | |
92105bb7 TL |
208 | }; |
209 | ||
471b3aa7 | 210 | static const char *omap2_dm_source_names[] __initdata = { |
83379c81 TT |
211 | "sys_ck", |
212 | "func_32k_ck", | |
471b3aa7 SMK |
213 | "alt_ck", |
214 | NULL | |
83379c81 TT |
215 | }; |
216 | ||
471b3aa7 SMK |
217 | static struct clk **omap2_dm_source_clocks[3]; |
218 | static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers); | |
83379c81 | 219 | |
ce2df9ca SMK |
220 | #elif defined(CONFIG_ARCH_OMAP3) |
221 | ||
222 | #define omap_dm_clk_enable(x) clk_enable(x) | |
223 | #define omap_dm_clk_disable(x) clk_disable(x) | |
224 | #define omap1_dm_timers NULL | |
225 | #define omap2_dm_timers NULL | |
226 | #define omap2_dm_source_names NULL | |
227 | #define omap2_dm_source_clocks NULL | |
228 | ||
229 | static struct omap_dm_timer omap3_dm_timers[] = { | |
230 | { .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 }, | |
231 | { .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 }, | |
232 | { .phys_base = 0x49034000, .irq = INT_24XX_GPTIMER3 }, | |
233 | { .phys_base = 0x49036000, .irq = INT_24XX_GPTIMER4 }, | |
234 | { .phys_base = 0x49038000, .irq = INT_24XX_GPTIMER5 }, | |
235 | { .phys_base = 0x4903A000, .irq = INT_24XX_GPTIMER6 }, | |
236 | { .phys_base = 0x4903C000, .irq = INT_24XX_GPTIMER7 }, | |
237 | { .phys_base = 0x4903E000, .irq = INT_24XX_GPTIMER8 }, | |
238 | { .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 }, | |
239 | { .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 }, | |
240 | { .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 }, | |
9198a406 | 241 | { .phys_base = 0x48304000, .irq = INT_34XX_GPT12_IRQ }, |
ce2df9ca SMK |
242 | }; |
243 | ||
244 | static const char *omap3_dm_source_names[] __initdata = { | |
245 | "sys_ck", | |
246 | "omap_32k_fck", | |
247 | NULL | |
248 | }; | |
249 | ||
250 | static struct clk **omap3_dm_source_clocks[2]; | |
251 | static const int dm_timer_count = ARRAY_SIZE(omap3_dm_timers); | |
252 | ||
77900a2f TT |
253 | #else |
254 | ||
255 | #error OMAP architecture not supported! | |
256 | ||
257 | #endif | |
258 | ||
471b3aa7 SMK |
259 | static struct omap_dm_timer *dm_timers; |
260 | static char **dm_source_names; | |
261 | static struct clk **dm_source_clocks; | |
262 | ||
92105bb7 TL |
263 | static spinlock_t dm_timer_lock; |
264 | ||
0f0d0807 RW |
265 | /* |
266 | * Reads timer registers in posted and non-posted mode. The posted mode bit | |
267 | * is encoded in reg. Note that in posted mode write pending bit must be | |
268 | * checked. Otherwise a read of a non completed write will produce an error. | |
269 | */ | |
270 | static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) | |
77900a2f | 271 | { |
0f0d0807 RW |
272 | if (timer->posted) |
273 | while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff)) | |
274 | & (reg >> WPSHIFT)) | |
275 | cpu_relax(); | |
276 | return readl(timer->io_base + (reg & 0xff)); | |
77900a2f | 277 | } |
92105bb7 | 278 | |
0f0d0807 RW |
279 | /* |
280 | * Writes timer registers in posted and non-posted mode. The posted mode bit | |
281 | * is encoded in reg. Note that in posted mode the write pending bit must be | |
282 | * checked. Otherwise a write on a register which has a pending write will be | |
283 | * lost. | |
284 | */ | |
285 | static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, | |
286 | u32 value) | |
92105bb7 | 287 | { |
0f0d0807 RW |
288 | if (timer->posted) |
289 | while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff)) | |
290 | & (reg >> WPSHIFT)) | |
291 | cpu_relax(); | |
292 | writel(value, timer->io_base + (reg & 0xff)); | |
92105bb7 TL |
293 | } |
294 | ||
77900a2f | 295 | static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer) |
92105bb7 | 296 | { |
77900a2f TT |
297 | int c; |
298 | ||
299 | c = 0; | |
300 | while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) { | |
301 | c++; | |
302 | if (c > 100000) { | |
303 | printk(KERN_ERR "Timer failed to reset\n"); | |
304 | return; | |
305 | } | |
306 | } | |
92105bb7 TL |
307 | } |
308 | ||
77900a2f TT |
309 | static void omap_dm_timer_reset(struct omap_dm_timer *timer) |
310 | { | |
311 | u32 l; | |
312 | ||
39020842 | 313 | if (!cpu_class_is_omap2() || timer != &dm_timers[0]) { |
e32f7ec2 TT |
314 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); |
315 | omap_dm_timer_wait_for_reset(timer); | |
316 | } | |
12583a70 | 317 | omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); |
77900a2f | 318 | |
77900a2f | 319 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG); |
0f0d0807 RW |
320 | l |= 0x02 << 3; /* Set to smart-idle mode */ |
321 | l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */ | |
322 | ||
323 | /* | |
219c5b98 | 324 | * Enable wake-up on OMAP2 CPUs. |
0f0d0807 | 325 | */ |
219c5b98 | 326 | if (cpu_class_is_omap2()) |
39020842 | 327 | l |= 1 << 2; |
77900a2f | 328 | omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l); |
0f0d0807 RW |
329 | |
330 | /* Match hardware reset default of posted mode */ | |
331 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, | |
332 | OMAP_TIMER_CTRL_POSTED); | |
333 | timer->posted = 1; | |
77900a2f TT |
334 | } |
335 | ||
83379c81 | 336 | static void omap_dm_timer_prepare(struct omap_dm_timer *timer) |
77900a2f | 337 | { |
12583a70 | 338 | omap_dm_timer_enable(timer); |
77900a2f TT |
339 | omap_dm_timer_reset(timer); |
340 | } | |
341 | ||
342 | struct omap_dm_timer *omap_dm_timer_request(void) | |
343 | { | |
344 | struct omap_dm_timer *timer = NULL; | |
345 | unsigned long flags; | |
346 | int i; | |
347 | ||
348 | spin_lock_irqsave(&dm_timer_lock, flags); | |
349 | for (i = 0; i < dm_timer_count; i++) { | |
350 | if (dm_timers[i].reserved) | |
351 | continue; | |
352 | ||
353 | timer = &dm_timers[i]; | |
83379c81 | 354 | timer->reserved = 1; |
77900a2f TT |
355 | break; |
356 | } | |
357 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
358 | ||
83379c81 TT |
359 | if (timer != NULL) |
360 | omap_dm_timer_prepare(timer); | |
361 | ||
77900a2f TT |
362 | return timer; |
363 | } | |
6c366e32 | 364 | EXPORT_SYMBOL_GPL(omap_dm_timer_request); |
77900a2f TT |
365 | |
366 | struct omap_dm_timer *omap_dm_timer_request_specific(int id) | |
92105bb7 TL |
367 | { |
368 | struct omap_dm_timer *timer; | |
77900a2f | 369 | unsigned long flags; |
92105bb7 | 370 | |
77900a2f TT |
371 | spin_lock_irqsave(&dm_timer_lock, flags); |
372 | if (id <= 0 || id > dm_timer_count || dm_timers[id-1].reserved) { | |
373 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
374 | printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n", | |
8e86f427 | 375 | __FILE__, __LINE__, __func__, id); |
77900a2f TT |
376 | dump_stack(); |
377 | return NULL; | |
378 | } | |
92105bb7 | 379 | |
77900a2f | 380 | timer = &dm_timers[id-1]; |
83379c81 | 381 | timer->reserved = 1; |
77900a2f TT |
382 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
383 | ||
83379c81 TT |
384 | omap_dm_timer_prepare(timer); |
385 | ||
77900a2f | 386 | return timer; |
92105bb7 | 387 | } |
6c366e32 | 388 | EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific); |
92105bb7 | 389 | |
77900a2f TT |
390 | void omap_dm_timer_free(struct omap_dm_timer *timer) |
391 | { | |
12583a70 | 392 | omap_dm_timer_enable(timer); |
77900a2f | 393 | omap_dm_timer_reset(timer); |
12583a70 | 394 | omap_dm_timer_disable(timer); |
fa4bb626 | 395 | |
77900a2f TT |
396 | WARN_ON(!timer->reserved); |
397 | timer->reserved = 0; | |
398 | } | |
6c366e32 | 399 | EXPORT_SYMBOL_GPL(omap_dm_timer_free); |
77900a2f | 400 | |
12583a70 TT |
401 | void omap_dm_timer_enable(struct omap_dm_timer *timer) |
402 | { | |
403 | if (timer->enabled) | |
404 | return; | |
405 | ||
406 | omap_dm_clk_enable(timer->fclk); | |
407 | omap_dm_clk_enable(timer->iclk); | |
408 | ||
409 | timer->enabled = 1; | |
410 | } | |
6c366e32 | 411 | EXPORT_SYMBOL_GPL(omap_dm_timer_enable); |
12583a70 TT |
412 | |
413 | void omap_dm_timer_disable(struct omap_dm_timer *timer) | |
414 | { | |
415 | if (!timer->enabled) | |
416 | return; | |
417 | ||
418 | omap_dm_clk_disable(timer->iclk); | |
419 | omap_dm_clk_disable(timer->fclk); | |
420 | ||
421 | timer->enabled = 0; | |
422 | } | |
6c366e32 | 423 | EXPORT_SYMBOL_GPL(omap_dm_timer_disable); |
12583a70 | 424 | |
77900a2f TT |
425 | int omap_dm_timer_get_irq(struct omap_dm_timer *timer) |
426 | { | |
427 | return timer->irq; | |
428 | } | |
6c366e32 | 429 | EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq); |
77900a2f TT |
430 | |
431 | #if defined(CONFIG_ARCH_OMAP1) | |
432 | ||
a569c6ec TL |
433 | /** |
434 | * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR | |
435 | * @inputmask: current value of idlect mask | |
436 | */ | |
437 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) | |
438 | { | |
77900a2f | 439 | int i; |
a569c6ec TL |
440 | |
441 | /* If ARMXOR cannot be idled this function call is unnecessary */ | |
442 | if (!(inputmask & (1 << 1))) | |
443 | return inputmask; | |
444 | ||
445 | /* If any active timer is using ARMXOR return modified mask */ | |
77900a2f TT |
446 | for (i = 0; i < dm_timer_count; i++) { |
447 | u32 l; | |
448 | ||
35912c79 | 449 | l = omap_dm_timer_read_reg(&dm_timers[i], OMAP_TIMER_CTRL_REG); |
77900a2f TT |
450 | if (l & OMAP_TIMER_CTRL_ST) { |
451 | if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0) | |
a569c6ec TL |
452 | inputmask &= ~(1 << 1); |
453 | else | |
454 | inputmask &= ~(1 << 2); | |
455 | } | |
77900a2f | 456 | } |
a569c6ec TL |
457 | |
458 | return inputmask; | |
459 | } | |
6c366e32 | 460 | EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); |
a569c6ec | 461 | |
ce2df9ca | 462 | #elif defined(CONFIG_ARCH_OMAP2) || defined (CONFIG_ARCH_OMAP3) |
a569c6ec | 463 | |
77900a2f | 464 | struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) |
92105bb7 | 465 | { |
fa4bb626 | 466 | return timer->fclk; |
77900a2f | 467 | } |
6c366e32 | 468 | EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk); |
92105bb7 | 469 | |
77900a2f TT |
470 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) |
471 | { | |
472 | BUG(); | |
2121880e DB |
473 | |
474 | return 0; | |
92105bb7 | 475 | } |
6c366e32 | 476 | EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); |
92105bb7 | 477 | |
77900a2f | 478 | #endif |
92105bb7 | 479 | |
77900a2f | 480 | void omap_dm_timer_trigger(struct omap_dm_timer *timer) |
92105bb7 | 481 | { |
77900a2f | 482 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
92105bb7 | 483 | } |
6c366e32 | 484 | EXPORT_SYMBOL_GPL(omap_dm_timer_trigger); |
92105bb7 | 485 | |
77900a2f TT |
486 | void omap_dm_timer_start(struct omap_dm_timer *timer) |
487 | { | |
488 | u32 l; | |
92105bb7 | 489 | |
77900a2f TT |
490 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
491 | if (!(l & OMAP_TIMER_CTRL_ST)) { | |
492 | l |= OMAP_TIMER_CTRL_ST; | |
493 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | |
494 | } | |
495 | } | |
6c366e32 | 496 | EXPORT_SYMBOL_GPL(omap_dm_timer_start); |
92105bb7 | 497 | |
77900a2f | 498 | void omap_dm_timer_stop(struct omap_dm_timer *timer) |
92105bb7 | 499 | { |
77900a2f | 500 | u32 l; |
92105bb7 | 501 | |
77900a2f TT |
502 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
503 | if (l & OMAP_TIMER_CTRL_ST) { | |
504 | l &= ~0x1; | |
505 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | |
92105bb7 | 506 | } |
92105bb7 | 507 | } |
6c366e32 | 508 | EXPORT_SYMBOL_GPL(omap_dm_timer_stop); |
92105bb7 | 509 | |
77900a2f | 510 | #ifdef CONFIG_ARCH_OMAP1 |
92105bb7 | 511 | |
77900a2f | 512 | void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) |
92105bb7 | 513 | { |
77900a2f TT |
514 | int n = (timer - dm_timers) << 1; |
515 | u32 l; | |
92105bb7 | 516 | |
77900a2f TT |
517 | l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n); |
518 | l |= source << n; | |
519 | omap_writel(l, MOD_CONF_CTRL_1); | |
92105bb7 | 520 | } |
6c366e32 | 521 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); |
92105bb7 | 522 | |
77900a2f | 523 | #else |
92105bb7 | 524 | |
77900a2f | 525 | void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) |
92105bb7 | 526 | { |
77900a2f TT |
527 | if (source < 0 || source >= 3) |
528 | return; | |
529 | ||
77900a2f | 530 | clk_disable(timer->fclk); |
83379c81 | 531 | clk_set_parent(timer->fclk, dm_source_clocks[source]); |
77900a2f | 532 | clk_enable(timer->fclk); |
77900a2f TT |
533 | |
534 | /* When the functional clock disappears, too quick writes seem to | |
535 | * cause an abort. */ | |
c40fae95 | 536 | __delay(150000); |
92105bb7 | 537 | } |
6c366e32 | 538 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); |
92105bb7 | 539 | |
77900a2f | 540 | #endif |
92105bb7 | 541 | |
77900a2f TT |
542 | void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, |
543 | unsigned int load) | |
92105bb7 TL |
544 | { |
545 | u32 l; | |
77900a2f | 546 | |
92105bb7 | 547 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
548 | if (autoreload) |
549 | l |= OMAP_TIMER_CTRL_AR; | |
550 | else | |
551 | l &= ~OMAP_TIMER_CTRL_AR; | |
92105bb7 | 552 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
77900a2f | 553 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); |
0f0d0807 | 554 | |
77900a2f | 555 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
92105bb7 | 556 | } |
6c366e32 | 557 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_load); |
92105bb7 | 558 | |
3fddd09e RW |
559 | /* Optimized set_load which removes costly spin wait in timer_start */ |
560 | void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, | |
561 | unsigned int load) | |
562 | { | |
563 | u32 l; | |
564 | ||
565 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); | |
64ce2907 | 566 | if (autoreload) { |
3fddd09e | 567 | l |= OMAP_TIMER_CTRL_AR; |
64ce2907 PW |
568 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); |
569 | } else { | |
3fddd09e | 570 | l &= ~OMAP_TIMER_CTRL_AR; |
64ce2907 | 571 | } |
3fddd09e RW |
572 | l |= OMAP_TIMER_CTRL_ST; |
573 | ||
574 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load); | |
3fddd09e RW |
575 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
576 | } | |
6c366e32 | 577 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start); |
3fddd09e | 578 | |
77900a2f TT |
579 | void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, |
580 | unsigned int match) | |
92105bb7 TL |
581 | { |
582 | u32 l; | |
583 | ||
584 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); | |
83379c81 | 585 | if (enable) |
77900a2f TT |
586 | l |= OMAP_TIMER_CTRL_CE; |
587 | else | |
588 | l &= ~OMAP_TIMER_CTRL_CE; | |
92105bb7 | 589 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
77900a2f | 590 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); |
92105bb7 | 591 | } |
6c366e32 | 592 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_match); |
92105bb7 | 593 | |
77900a2f TT |
594 | void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, |
595 | int toggle, int trigger) | |
92105bb7 TL |
596 | { |
597 | u32 l; | |
598 | ||
599 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); | |
77900a2f TT |
600 | l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | |
601 | OMAP_TIMER_CTRL_PT | (0x03 << 10)); | |
602 | if (def_on) | |
603 | l |= OMAP_TIMER_CTRL_SCPWM; | |
604 | if (toggle) | |
605 | l |= OMAP_TIMER_CTRL_PT; | |
606 | l |= trigger << 10; | |
92105bb7 TL |
607 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
608 | } | |
6c366e32 | 609 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm); |
92105bb7 | 610 | |
77900a2f | 611 | void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler) |
92105bb7 TL |
612 | { |
613 | u32 l; | |
614 | ||
615 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); | |
77900a2f TT |
616 | l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); |
617 | if (prescaler >= 0x00 && prescaler <= 0x07) { | |
618 | l |= OMAP_TIMER_CTRL_PRE; | |
619 | l |= prescaler << 2; | |
620 | } | |
92105bb7 TL |
621 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
622 | } | |
6c366e32 | 623 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler); |
92105bb7 | 624 | |
77900a2f TT |
625 | void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, |
626 | unsigned int value) | |
92105bb7 | 627 | { |
77900a2f | 628 | omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value); |
39020842 | 629 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value); |
92105bb7 | 630 | } |
6c366e32 | 631 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable); |
92105bb7 | 632 | |
77900a2f | 633 | unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) |
92105bb7 | 634 | { |
fa4bb626 TT |
635 | unsigned int l; |
636 | ||
fa4bb626 | 637 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG); |
fa4bb626 TT |
638 | |
639 | return l; | |
92105bb7 | 640 | } |
6c366e32 | 641 | EXPORT_SYMBOL_GPL(omap_dm_timer_read_status); |
92105bb7 | 642 | |
77900a2f | 643 | void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) |
92105bb7 | 644 | { |
77900a2f | 645 | omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value); |
92105bb7 | 646 | } |
6c366e32 | 647 | EXPORT_SYMBOL_GPL(omap_dm_timer_write_status); |
92105bb7 | 648 | |
77900a2f | 649 | unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) |
92105bb7 | 650 | { |
fa4bb626 TT |
651 | unsigned int l; |
652 | ||
fa4bb626 | 653 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG); |
fa4bb626 TT |
654 | |
655 | return l; | |
92105bb7 | 656 | } |
6c366e32 | 657 | EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter); |
92105bb7 | 658 | |
83379c81 TT |
659 | void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) |
660 | { | |
fa4bb626 | 661 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); |
83379c81 | 662 | } |
6c366e32 | 663 | EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter); |
83379c81 | 664 | |
77900a2f | 665 | int omap_dm_timers_active(void) |
92105bb7 | 666 | { |
77900a2f | 667 | int i; |
92105bb7 | 668 | |
77900a2f TT |
669 | for (i = 0; i < dm_timer_count; i++) { |
670 | struct omap_dm_timer *timer; | |
92105bb7 | 671 | |
77900a2f | 672 | timer = &dm_timers[i]; |
12583a70 TT |
673 | |
674 | if (!timer->enabled) | |
675 | continue; | |
676 | ||
77900a2f | 677 | if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & |
fa4bb626 | 678 | OMAP_TIMER_CTRL_ST) { |
77900a2f | 679 | return 1; |
fa4bb626 | 680 | } |
77900a2f TT |
681 | } |
682 | return 0; | |
683 | } | |
6c366e32 | 684 | EXPORT_SYMBOL_GPL(omap_dm_timers_active); |
92105bb7 | 685 | |
471b3aa7 | 686 | int __init omap_dm_timer_init(void) |
92105bb7 TL |
687 | { |
688 | struct omap_dm_timer *timer; | |
77900a2f TT |
689 | int i; |
690 | ||
ce2df9ca | 691 | if (!(cpu_is_omap16xx() || cpu_class_is_omap2())) |
77900a2f | 692 | return -ENODEV; |
92105bb7 TL |
693 | |
694 | spin_lock_init(&dm_timer_lock); | |
471b3aa7 SMK |
695 | |
696 | if (cpu_class_is_omap1()) | |
697 | dm_timers = omap1_dm_timers; | |
698 | else if (cpu_is_omap24xx()) { | |
699 | dm_timers = omap2_dm_timers; | |
700 | dm_source_names = (char **)omap2_dm_source_names; | |
701 | dm_source_clocks = (struct clk **)omap2_dm_source_clocks; | |
ce2df9ca SMK |
702 | } else if (cpu_is_omap34xx()) { |
703 | dm_timers = omap3_dm_timers; | |
704 | dm_source_names = (char **)omap3_dm_source_names; | |
705 | dm_source_clocks = (struct clk **)omap3_dm_source_clocks; | |
83379c81 | 706 | } |
471b3aa7 SMK |
707 | |
708 | if (cpu_class_is_omap2()) | |
709 | for (i = 0; dm_source_names[i] != NULL; i++) | |
710 | dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]); | |
711 | ||
56a25641 SMK |
712 | if (cpu_is_omap243x()) |
713 | dm_timers[0].phys_base = 0x49018000; | |
83379c81 | 714 | |
77900a2f | 715 | for (i = 0; i < dm_timer_count; i++) { |
77900a2f | 716 | timer = &dm_timers[i]; |
e8a91c95 | 717 | timer->io_base = IO_ADDRESS(timer->phys_base); |
ce2df9ca | 718 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
471b3aa7 SMK |
719 | if (cpu_class_is_omap2()) { |
720 | char clk_name[16]; | |
721 | sprintf(clk_name, "gpt%d_ick", i + 1); | |
722 | timer->iclk = clk_get(NULL, clk_name); | |
723 | sprintf(clk_name, "gpt%d_fck", i + 1); | |
724 | timer->fclk = clk_get(NULL, clk_name); | |
725 | } | |
77900a2f | 726 | #endif |
92105bb7 | 727 | } |
92105bb7 | 728 | |
92105bb7 TL |
729 | return 0; |
730 | } |