Commit | Line | Data |
---|---|---|
92105bb7 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/dmtimer.c | |
3 | * | |
4 | * OMAP Dual-Mode Timers | |
5 | * | |
97933d6c TKD |
6 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ |
7 | * Tarun Kanti DebBarma <tarun.kanti@ti.com> | |
8 | * Thara Gopinath <thara@ti.com> | |
9 | * | |
10 | * dmtimer adaptation to platform_driver. | |
11 | * | |
92105bb7 | 12 | * Copyright (C) 2005 Nokia Corporation |
77900a2f TT |
13 | * OMAP2 support by Juha Yrjola |
14 | * API improvements and OMAP2 clock framework support by Timo Teras | |
92105bb7 | 15 | * |
44169075 SS |
16 | * Copyright (C) 2009 Texas Instruments |
17 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
18 | * | |
92105bb7 TL |
19 | * This program is free software; you can redistribute it and/or modify it |
20 | * under the terms of the GNU General Public License as published by the | |
21 | * Free Software Foundation; either version 2 of the License, or (at your | |
22 | * option) any later version. | |
23 | * | |
24 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
25 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
26 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
27 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
28 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License along | |
34 | * with this program; if not, write to the Free Software Foundation, Inc., | |
35 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
36 | */ | |
37 | ||
869dec15 | 38 | #include <linux/module.h> |
fced80c7 | 39 | #include <linux/io.h> |
74dd9ec6 | 40 | #include <linux/device.h> |
3392cdd3 | 41 | #include <linux/err.h> |
ffe07cea | 42 | #include <linux/pm_runtime.h> |
9725f445 JH |
43 | #include <linux/of.h> |
44 | #include <linux/of_device.h> | |
44169075 | 45 | |
3392cdd3 | 46 | #include <plat/dmtimer.h> |
0b30ec1c | 47 | #include <plat/omap-pm.h> |
471b3aa7 | 48 | |
2c799cef TL |
49 | #include <mach/hardware.h> |
50 | ||
b7b4ff76 | 51 | static u32 omap_reserved_systimers; |
df28472a | 52 | static LIST_HEAD(omap_timer_list); |
3392cdd3 | 53 | static DEFINE_SPINLOCK(dm_timer_lock); |
92105bb7 | 54 | |
3392cdd3 TKD |
55 | /** |
56 | * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode | |
57 | * @timer: timer pointer over which read operation to perform | |
58 | * @reg: lowest byte holds the register offset | |
59 | * | |
60 | * The posted mode bit is encoded in reg. Note that in posted mode write | |
61 | * pending bit must be checked. Otherwise a read of a non completed write | |
62 | * will produce an error. | |
0f0d0807 RW |
63 | */ |
64 | static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) | |
77900a2f | 65 | { |
ee17f114 TL |
66 | WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
67 | return __omap_dm_timer_read(timer, reg, timer->posted); | |
77900a2f | 68 | } |
92105bb7 | 69 | |
3392cdd3 TKD |
70 | /** |
71 | * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode | |
72 | * @timer: timer pointer over which write operation is to perform | |
73 | * @reg: lowest byte holds the register offset | |
74 | * @value: data to write into the register | |
75 | * | |
76 | * The posted mode bit is encoded in reg. Note that in posted mode the write | |
77 | * pending bit must be checked. Otherwise a write on a register which has a | |
78 | * pending write will be lost. | |
0f0d0807 RW |
79 | */ |
80 | static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, | |
81 | u32 value) | |
92105bb7 | 82 | { |
ee17f114 TL |
83 | WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
84 | __omap_dm_timer_write(timer, reg, value, timer->posted); | |
92105bb7 TL |
85 | } |
86 | ||
b481113a TKD |
87 | static void omap_timer_restore_context(struct omap_dm_timer *timer) |
88 | { | |
dffc9dae | 89 | if (timer->revision == 1) |
b481113a TKD |
90 | __raw_writel(timer->context.tistat, timer->sys_stat); |
91 | ||
92 | __raw_writel(timer->context.tisr, timer->irq_stat); | |
93 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, | |
94 | timer->context.twer); | |
95 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, | |
96 | timer->context.tcrr); | |
97 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, | |
98 | timer->context.tldr); | |
99 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, | |
100 | timer->context.tmar); | |
101 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, | |
102 | timer->context.tsicr); | |
103 | __raw_writel(timer->context.tier, timer->irq_ena); | |
104 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, | |
105 | timer->context.tclr); | |
106 | } | |
107 | ||
77900a2f | 108 | static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer) |
92105bb7 | 109 | { |
77900a2f TT |
110 | int c; |
111 | ||
ee17f114 TL |
112 | if (!timer->sys_stat) |
113 | return; | |
114 | ||
77900a2f | 115 | c = 0; |
ee17f114 | 116 | while (!(__raw_readl(timer->sys_stat) & 1)) { |
77900a2f TT |
117 | c++; |
118 | if (c > 100000) { | |
119 | printk(KERN_ERR "Timer failed to reset\n"); | |
120 | return; | |
121 | } | |
122 | } | |
92105bb7 TL |
123 | } |
124 | ||
77900a2f TT |
125 | static void omap_dm_timer_reset(struct omap_dm_timer *timer) |
126 | { | |
b481113a | 127 | omap_dm_timer_enable(timer); |
3392cdd3 | 128 | if (timer->pdev->id != 1) { |
e32f7ec2 TT |
129 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); |
130 | omap_dm_timer_wait_for_reset(timer); | |
131 | } | |
0f0d0807 | 132 | |
3392cdd3 | 133 | __omap_dm_timer_reset(timer, 0, 0); |
b481113a | 134 | omap_dm_timer_disable(timer); |
0f0d0807 | 135 | timer->posted = 1; |
77900a2f TT |
136 | } |
137 | ||
3392cdd3 | 138 | int omap_dm_timer_prepare(struct omap_dm_timer *timer) |
77900a2f | 139 | { |
3392cdd3 TKD |
140 | int ret; |
141 | ||
bca45808 JH |
142 | /* |
143 | * FIXME: OMAP1 devices do not use the clock framework for dmtimers so | |
144 | * do not call clk_get() for these devices. | |
145 | */ | |
146 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { | |
147 | timer->fclk = clk_get(&timer->pdev->dev, "fck"); | |
148 | if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) { | |
149 | timer->fclk = NULL; | |
150 | dev_err(&timer->pdev->dev, ": No fclk handle.\n"); | |
151 | return -EINVAL; | |
152 | } | |
3392cdd3 TKD |
153 | } |
154 | ||
6615975b | 155 | if (timer->capability & OMAP_TIMER_NEEDS_RESET) |
3392cdd3 TKD |
156 | omap_dm_timer_reset(timer); |
157 | ||
158 | ret = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); | |
159 | ||
160 | timer->posted = 1; | |
161 | return ret; | |
77900a2f TT |
162 | } |
163 | ||
b7b4ff76 JH |
164 | static inline u32 omap_dm_timer_reserved_systimer(int id) |
165 | { | |
166 | return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0; | |
167 | } | |
168 | ||
169 | int omap_dm_timer_reserve_systimer(int id) | |
170 | { | |
171 | if (omap_dm_timer_reserved_systimer(id)) | |
172 | return -ENODEV; | |
173 | ||
174 | omap_reserved_systimers |= (1 << (id - 1)); | |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
77900a2f TT |
179 | struct omap_dm_timer *omap_dm_timer_request(void) |
180 | { | |
3392cdd3 | 181 | struct omap_dm_timer *timer = NULL, *t; |
77900a2f | 182 | unsigned long flags; |
3392cdd3 | 183 | int ret = 0; |
77900a2f TT |
184 | |
185 | spin_lock_irqsave(&dm_timer_lock, flags); | |
3392cdd3 TKD |
186 | list_for_each_entry(t, &omap_timer_list, node) { |
187 | if (t->reserved) | |
77900a2f TT |
188 | continue; |
189 | ||
3392cdd3 | 190 | timer = t; |
83379c81 | 191 | timer->reserved = 1; |
77900a2f TT |
192 | break; |
193 | } | |
c5491d1a | 194 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
3392cdd3 TKD |
195 | |
196 | if (timer) { | |
197 | ret = omap_dm_timer_prepare(timer); | |
198 | if (ret) { | |
199 | timer->reserved = 0; | |
200 | timer = NULL; | |
201 | } | |
202 | } | |
77900a2f | 203 | |
3392cdd3 TKD |
204 | if (!timer) |
205 | pr_debug("%s: timer request failed!\n", __func__); | |
83379c81 | 206 | |
77900a2f TT |
207 | return timer; |
208 | } | |
6c366e32 | 209 | EXPORT_SYMBOL_GPL(omap_dm_timer_request); |
77900a2f TT |
210 | |
211 | struct omap_dm_timer *omap_dm_timer_request_specific(int id) | |
92105bb7 | 212 | { |
3392cdd3 | 213 | struct omap_dm_timer *timer = NULL, *t; |
77900a2f | 214 | unsigned long flags; |
3392cdd3 | 215 | int ret = 0; |
92105bb7 | 216 | |
9725f445 JH |
217 | /* Requesting timer by ID is not supported when device tree is used */ |
218 | if (of_have_populated_dt()) { | |
219 | pr_warn("%s: Please use omap_dm_timer_request_by_cap()\n", | |
220 | __func__); | |
221 | return NULL; | |
222 | } | |
223 | ||
77900a2f | 224 | spin_lock_irqsave(&dm_timer_lock, flags); |
3392cdd3 TKD |
225 | list_for_each_entry(t, &omap_timer_list, node) { |
226 | if (t->pdev->id == id && !t->reserved) { | |
227 | timer = t; | |
228 | timer->reserved = 1; | |
229 | break; | |
230 | } | |
77900a2f | 231 | } |
c5491d1a | 232 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
92105bb7 | 233 | |
3392cdd3 TKD |
234 | if (timer) { |
235 | ret = omap_dm_timer_prepare(timer); | |
236 | if (ret) { | |
237 | timer->reserved = 0; | |
238 | timer = NULL; | |
239 | } | |
240 | } | |
77900a2f | 241 | |
3392cdd3 TKD |
242 | if (!timer) |
243 | pr_debug("%s: timer%d request failed!\n", __func__, id); | |
83379c81 | 244 | |
77900a2f | 245 | return timer; |
92105bb7 | 246 | } |
6c366e32 | 247 | EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific); |
92105bb7 | 248 | |
373fe0bd JH |
249 | /** |
250 | * omap_dm_timer_request_by_cap - Request a timer by capability | |
251 | * @cap: Bit mask of capabilities to match | |
252 | * | |
253 | * Find a timer based upon capabilities bit mask. Callers of this function | |
254 | * should use the definitions found in the plat/dmtimer.h file under the | |
255 | * comment "timer capabilities used in hwmod database". Returns pointer to | |
256 | * timer handle on success and a NULL pointer on failure. | |
257 | */ | |
258 | struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap) | |
259 | { | |
260 | struct omap_dm_timer *timer = NULL, *t; | |
261 | unsigned long flags; | |
262 | ||
263 | if (!cap) | |
264 | return NULL; | |
265 | ||
266 | spin_lock_irqsave(&dm_timer_lock, flags); | |
267 | list_for_each_entry(t, &omap_timer_list, node) { | |
268 | if ((!t->reserved) && ((t->capability & cap) == cap)) { | |
269 | /* | |
270 | * If timer is not NULL, we have already found one timer | |
271 | * but it was not an exact match because it had more | |
272 | * capabilites that what was required. Therefore, | |
273 | * unreserve the last timer found and see if this one | |
274 | * is a better match. | |
275 | */ | |
276 | if (timer) | |
277 | timer->reserved = 0; | |
278 | ||
279 | timer = t; | |
280 | timer->reserved = 1; | |
281 | ||
282 | /* Exit loop early if we find an exact match */ | |
283 | if (t->capability == cap) | |
284 | break; | |
285 | } | |
286 | } | |
287 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
288 | ||
289 | if (timer && omap_dm_timer_prepare(timer)) { | |
290 | timer->reserved = 0; | |
291 | timer = NULL; | |
292 | } | |
293 | ||
294 | if (!timer) | |
295 | pr_debug("%s: timer request failed!\n", __func__); | |
296 | ||
297 | return timer; | |
298 | } | |
299 | EXPORT_SYMBOL_GPL(omap_dm_timer_request_by_cap); | |
300 | ||
ab4eb8b0 | 301 | int omap_dm_timer_free(struct omap_dm_timer *timer) |
77900a2f | 302 | { |
ab4eb8b0 TKD |
303 | if (unlikely(!timer)) |
304 | return -EINVAL; | |
305 | ||
3392cdd3 | 306 | clk_put(timer->fclk); |
fa4bb626 | 307 | |
77900a2f TT |
308 | WARN_ON(!timer->reserved); |
309 | timer->reserved = 0; | |
ab4eb8b0 | 310 | return 0; |
77900a2f | 311 | } |
6c366e32 | 312 | EXPORT_SYMBOL_GPL(omap_dm_timer_free); |
77900a2f | 313 | |
12583a70 TT |
314 | void omap_dm_timer_enable(struct omap_dm_timer *timer) |
315 | { | |
ffe07cea | 316 | pm_runtime_get_sync(&timer->pdev->dev); |
12583a70 | 317 | } |
6c366e32 | 318 | EXPORT_SYMBOL_GPL(omap_dm_timer_enable); |
12583a70 TT |
319 | |
320 | void omap_dm_timer_disable(struct omap_dm_timer *timer) | |
321 | { | |
54f32a35 | 322 | pm_runtime_put_sync(&timer->pdev->dev); |
12583a70 | 323 | } |
6c366e32 | 324 | EXPORT_SYMBOL_GPL(omap_dm_timer_disable); |
12583a70 | 325 | |
77900a2f TT |
326 | int omap_dm_timer_get_irq(struct omap_dm_timer *timer) |
327 | { | |
ab4eb8b0 TKD |
328 | if (timer) |
329 | return timer->irq; | |
330 | return -EINVAL; | |
77900a2f | 331 | } |
6c366e32 | 332 | EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq); |
77900a2f TT |
333 | |
334 | #if defined(CONFIG_ARCH_OMAP1) | |
335 | ||
a569c6ec TL |
336 | /** |
337 | * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR | |
338 | * @inputmask: current value of idlect mask | |
339 | */ | |
340 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) | |
341 | { | |
3392cdd3 TKD |
342 | int i = 0; |
343 | struct omap_dm_timer *timer = NULL; | |
344 | unsigned long flags; | |
a569c6ec TL |
345 | |
346 | /* If ARMXOR cannot be idled this function call is unnecessary */ | |
347 | if (!(inputmask & (1 << 1))) | |
348 | return inputmask; | |
349 | ||
350 | /* If any active timer is using ARMXOR return modified mask */ | |
3392cdd3 TKD |
351 | spin_lock_irqsave(&dm_timer_lock, flags); |
352 | list_for_each_entry(timer, &omap_timer_list, node) { | |
77900a2f TT |
353 | u32 l; |
354 | ||
3392cdd3 | 355 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
356 | if (l & OMAP_TIMER_CTRL_ST) { |
357 | if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0) | |
a569c6ec TL |
358 | inputmask &= ~(1 << 1); |
359 | else | |
360 | inputmask &= ~(1 << 2); | |
361 | } | |
3392cdd3 | 362 | i++; |
77900a2f | 363 | } |
3392cdd3 | 364 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
a569c6ec TL |
365 | |
366 | return inputmask; | |
367 | } | |
6c366e32 | 368 | EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); |
a569c6ec | 369 | |
140455fa | 370 | #else |
a569c6ec | 371 | |
77900a2f | 372 | struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) |
92105bb7 | 373 | { |
ab4eb8b0 TKD |
374 | if (timer) |
375 | return timer->fclk; | |
376 | return NULL; | |
77900a2f | 377 | } |
6c366e32 | 378 | EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk); |
92105bb7 | 379 | |
77900a2f TT |
380 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) |
381 | { | |
382 | BUG(); | |
2121880e DB |
383 | |
384 | return 0; | |
92105bb7 | 385 | } |
6c366e32 | 386 | EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); |
92105bb7 | 387 | |
77900a2f | 388 | #endif |
92105bb7 | 389 | |
ab4eb8b0 | 390 | int omap_dm_timer_trigger(struct omap_dm_timer *timer) |
92105bb7 | 391 | { |
ab4eb8b0 TKD |
392 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
393 | pr_err("%s: timer not available or enabled.\n", __func__); | |
394 | return -EINVAL; | |
b481113a TKD |
395 | } |
396 | ||
77900a2f | 397 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
ab4eb8b0 | 398 | return 0; |
92105bb7 | 399 | } |
6c366e32 | 400 | EXPORT_SYMBOL_GPL(omap_dm_timer_trigger); |
92105bb7 | 401 | |
ab4eb8b0 | 402 | int omap_dm_timer_start(struct omap_dm_timer *timer) |
77900a2f TT |
403 | { |
404 | u32 l; | |
92105bb7 | 405 | |
ab4eb8b0 TKD |
406 | if (unlikely(!timer)) |
407 | return -EINVAL; | |
408 | ||
b481113a TKD |
409 | omap_dm_timer_enable(timer); |
410 | ||
1c2d076b | 411 | if (!(timer->capability & OMAP_TIMER_ALWON)) { |
0b30ec1c JH |
412 | if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) != |
413 | timer->ctx_loss_count) | |
b481113a TKD |
414 | omap_timer_restore_context(timer); |
415 | } | |
416 | ||
77900a2f TT |
417 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
418 | if (!(l & OMAP_TIMER_CTRL_ST)) { | |
419 | l |= OMAP_TIMER_CTRL_ST; | |
420 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | |
421 | } | |
b481113a TKD |
422 | |
423 | /* Save the context */ | |
424 | timer->context.tclr = l; | |
ab4eb8b0 | 425 | return 0; |
77900a2f | 426 | } |
6c366e32 | 427 | EXPORT_SYMBOL_GPL(omap_dm_timer_start); |
92105bb7 | 428 | |
ab4eb8b0 | 429 | int omap_dm_timer_stop(struct omap_dm_timer *timer) |
92105bb7 | 430 | { |
caf64f2f | 431 | unsigned long rate = 0; |
92105bb7 | 432 | |
ab4eb8b0 TKD |
433 | if (unlikely(!timer)) |
434 | return -EINVAL; | |
435 | ||
6615975b | 436 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) |
3392cdd3 | 437 | rate = clk_get_rate(timer->fclk); |
caf64f2f | 438 | |
ee17f114 | 439 | __omap_dm_timer_stop(timer, timer->posted, rate); |
ab4eb8b0 | 440 | |
0b30ec1c | 441 | if (!(timer->capability & OMAP_TIMER_ALWON)) |
dffc9dae | 442 | timer->ctx_loss_count = |
0b30ec1c | 443 | omap_pm_get_dev_context_loss_count(&timer->pdev->dev); |
dffc9dae TKD |
444 | |
445 | /* | |
446 | * Since the register values are computed and written within | |
447 | * __omap_dm_timer_stop, we need to use read to retrieve the | |
448 | * context. | |
449 | */ | |
450 | timer->context.tclr = | |
451 | omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); | |
452 | timer->context.tisr = __raw_readl(timer->irq_stat); | |
453 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 454 | return 0; |
92105bb7 | 455 | } |
6c366e32 | 456 | EXPORT_SYMBOL_GPL(omap_dm_timer_stop); |
92105bb7 | 457 | |
f248076c | 458 | int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) |
92105bb7 | 459 | { |
3392cdd3 | 460 | int ret; |
2b2d3523 JH |
461 | char *parent_name = NULL; |
462 | struct clk *fclk, *parent; | |
ab4eb8b0 TKD |
463 | struct dmtimer_platform_data *pdata; |
464 | ||
465 | if (unlikely(!timer)) | |
466 | return -EINVAL; | |
467 | ||
468 | pdata = timer->pdev->dev.platform_data; | |
3392cdd3 | 469 | |
77900a2f | 470 | if (source < 0 || source >= 3) |
f248076c | 471 | return -EINVAL; |
77900a2f | 472 | |
2b2d3523 JH |
473 | /* |
474 | * FIXME: Used for OMAP1 devices only because they do not currently | |
475 | * use the clock framework to set the parent clock. To be removed | |
476 | * once OMAP1 migrated to using clock framework for dmtimers | |
477 | */ | |
9725f445 | 478 | if (pdata && pdata->set_timer_src) |
2b2d3523 JH |
479 | return pdata->set_timer_src(timer->pdev, source); |
480 | ||
481 | fclk = clk_get(&timer->pdev->dev, "fck"); | |
482 | if (IS_ERR_OR_NULL(fclk)) { | |
483 | pr_err("%s: fck not found\n", __func__); | |
484 | return -EINVAL; | |
485 | } | |
486 | ||
487 | switch (source) { | |
488 | case OMAP_TIMER_SRC_SYS_CLK: | |
c59b537d | 489 | parent_name = "timer_sys_ck"; |
2b2d3523 JH |
490 | break; |
491 | ||
492 | case OMAP_TIMER_SRC_32_KHZ: | |
c59b537d | 493 | parent_name = "timer_32k_ck"; |
2b2d3523 JH |
494 | break; |
495 | ||
496 | case OMAP_TIMER_SRC_EXT_CLK: | |
c59b537d | 497 | parent_name = "timer_ext_ck"; |
2b2d3523 JH |
498 | break; |
499 | } | |
500 | ||
501 | parent = clk_get(&timer->pdev->dev, parent_name); | |
502 | if (IS_ERR_OR_NULL(parent)) { | |
503 | pr_err("%s: %s not found\n", __func__, parent_name); | |
504 | ret = -EINVAL; | |
505 | goto out; | |
506 | } | |
507 | ||
508 | ret = clk_set_parent(fclk, parent); | |
509 | if (IS_ERR_VALUE(ret)) | |
510 | pr_err("%s: failed to set %s as parent\n", __func__, | |
511 | parent_name); | |
512 | ||
513 | clk_put(parent); | |
514 | out: | |
515 | clk_put(fclk); | |
3392cdd3 TKD |
516 | |
517 | return ret; | |
92105bb7 | 518 | } |
6c366e32 | 519 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); |
92105bb7 | 520 | |
ab4eb8b0 | 521 | int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, |
77900a2f | 522 | unsigned int load) |
92105bb7 TL |
523 | { |
524 | u32 l; | |
77900a2f | 525 | |
ab4eb8b0 TKD |
526 | if (unlikely(!timer)) |
527 | return -EINVAL; | |
528 | ||
b481113a | 529 | omap_dm_timer_enable(timer); |
92105bb7 | 530 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
531 | if (autoreload) |
532 | l |= OMAP_TIMER_CTRL_AR; | |
533 | else | |
534 | l &= ~OMAP_TIMER_CTRL_AR; | |
92105bb7 | 535 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
77900a2f | 536 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); |
0f0d0807 | 537 | |
77900a2f | 538 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
b481113a TKD |
539 | /* Save the context */ |
540 | timer->context.tclr = l; | |
541 | timer->context.tldr = load; | |
542 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 543 | return 0; |
92105bb7 | 544 | } |
6c366e32 | 545 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_load); |
92105bb7 | 546 | |
3fddd09e | 547 | /* Optimized set_load which removes costly spin wait in timer_start */ |
ab4eb8b0 | 548 | int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, |
3fddd09e RW |
549 | unsigned int load) |
550 | { | |
551 | u32 l; | |
552 | ||
ab4eb8b0 TKD |
553 | if (unlikely(!timer)) |
554 | return -EINVAL; | |
555 | ||
b481113a TKD |
556 | omap_dm_timer_enable(timer); |
557 | ||
1c2d076b | 558 | if (!(timer->capability & OMAP_TIMER_ALWON)) { |
0b30ec1c JH |
559 | if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) != |
560 | timer->ctx_loss_count) | |
b481113a TKD |
561 | omap_timer_restore_context(timer); |
562 | } | |
563 | ||
3fddd09e | 564 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
64ce2907 | 565 | if (autoreload) { |
3fddd09e | 566 | l |= OMAP_TIMER_CTRL_AR; |
64ce2907 PW |
567 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); |
568 | } else { | |
3fddd09e | 569 | l &= ~OMAP_TIMER_CTRL_AR; |
64ce2907 | 570 | } |
3fddd09e RW |
571 | l |= OMAP_TIMER_CTRL_ST; |
572 | ||
ee17f114 | 573 | __omap_dm_timer_load_start(timer, l, load, timer->posted); |
b481113a TKD |
574 | |
575 | /* Save the context */ | |
576 | timer->context.tclr = l; | |
577 | timer->context.tldr = load; | |
578 | timer->context.tcrr = load; | |
ab4eb8b0 | 579 | return 0; |
3fddd09e | 580 | } |
6c366e32 | 581 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start); |
3fddd09e | 582 | |
ab4eb8b0 | 583 | int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, |
77900a2f | 584 | unsigned int match) |
92105bb7 TL |
585 | { |
586 | u32 l; | |
587 | ||
ab4eb8b0 TKD |
588 | if (unlikely(!timer)) |
589 | return -EINVAL; | |
590 | ||
b481113a | 591 | omap_dm_timer_enable(timer); |
92105bb7 | 592 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
83379c81 | 593 | if (enable) |
77900a2f TT |
594 | l |= OMAP_TIMER_CTRL_CE; |
595 | else | |
596 | l &= ~OMAP_TIMER_CTRL_CE; | |
92105bb7 | 597 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
77900a2f | 598 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); |
b481113a TKD |
599 | |
600 | /* Save the context */ | |
601 | timer->context.tclr = l; | |
602 | timer->context.tmar = match; | |
603 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 604 | return 0; |
92105bb7 | 605 | } |
6c366e32 | 606 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_match); |
92105bb7 | 607 | |
ab4eb8b0 | 608 | int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, |
77900a2f | 609 | int toggle, int trigger) |
92105bb7 TL |
610 | { |
611 | u32 l; | |
612 | ||
ab4eb8b0 TKD |
613 | if (unlikely(!timer)) |
614 | return -EINVAL; | |
615 | ||
b481113a | 616 | omap_dm_timer_enable(timer); |
92105bb7 | 617 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
618 | l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | |
619 | OMAP_TIMER_CTRL_PT | (0x03 << 10)); | |
620 | if (def_on) | |
621 | l |= OMAP_TIMER_CTRL_SCPWM; | |
622 | if (toggle) | |
623 | l |= OMAP_TIMER_CTRL_PT; | |
624 | l |= trigger << 10; | |
92105bb7 | 625 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
626 | |
627 | /* Save the context */ | |
628 | timer->context.tclr = l; | |
629 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 630 | return 0; |
92105bb7 | 631 | } |
6c366e32 | 632 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm); |
92105bb7 | 633 | |
ab4eb8b0 | 634 | int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler) |
92105bb7 TL |
635 | { |
636 | u32 l; | |
637 | ||
ab4eb8b0 TKD |
638 | if (unlikely(!timer)) |
639 | return -EINVAL; | |
640 | ||
b481113a | 641 | omap_dm_timer_enable(timer); |
92105bb7 | 642 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
643 | l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); |
644 | if (prescaler >= 0x00 && prescaler <= 0x07) { | |
645 | l |= OMAP_TIMER_CTRL_PRE; | |
646 | l |= prescaler << 2; | |
647 | } | |
92105bb7 | 648 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
649 | |
650 | /* Save the context */ | |
651 | timer->context.tclr = l; | |
652 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 653 | return 0; |
92105bb7 | 654 | } |
6c366e32 | 655 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler); |
92105bb7 | 656 | |
ab4eb8b0 | 657 | int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, |
77900a2f | 658 | unsigned int value) |
92105bb7 | 659 | { |
ab4eb8b0 TKD |
660 | if (unlikely(!timer)) |
661 | return -EINVAL; | |
662 | ||
b481113a | 663 | omap_dm_timer_enable(timer); |
ee17f114 | 664 | __omap_dm_timer_int_enable(timer, value); |
b481113a TKD |
665 | |
666 | /* Save the context */ | |
667 | timer->context.tier = value; | |
668 | timer->context.twer = value; | |
669 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 670 | return 0; |
92105bb7 | 671 | } |
6c366e32 | 672 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable); |
92105bb7 | 673 | |
77900a2f | 674 | unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) |
92105bb7 | 675 | { |
fa4bb626 TT |
676 | unsigned int l; |
677 | ||
ab4eb8b0 TKD |
678 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
679 | pr_err("%s: timer not available or enabled.\n", __func__); | |
b481113a TKD |
680 | return 0; |
681 | } | |
682 | ||
ee17f114 | 683 | l = __raw_readl(timer->irq_stat); |
fa4bb626 TT |
684 | |
685 | return l; | |
92105bb7 | 686 | } |
6c366e32 | 687 | EXPORT_SYMBOL_GPL(omap_dm_timer_read_status); |
92105bb7 | 688 | |
ab4eb8b0 | 689 | int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) |
92105bb7 | 690 | { |
ab4eb8b0 TKD |
691 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) |
692 | return -EINVAL; | |
693 | ||
ee17f114 | 694 | __omap_dm_timer_write_status(timer, value); |
b481113a TKD |
695 | /* Save the context */ |
696 | timer->context.tisr = value; | |
ab4eb8b0 | 697 | return 0; |
92105bb7 | 698 | } |
6c366e32 | 699 | EXPORT_SYMBOL_GPL(omap_dm_timer_write_status); |
92105bb7 | 700 | |
77900a2f | 701 | unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) |
92105bb7 | 702 | { |
ab4eb8b0 TKD |
703 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
704 | pr_err("%s: timer not iavailable or enabled.\n", __func__); | |
b481113a TKD |
705 | return 0; |
706 | } | |
707 | ||
ee17f114 | 708 | return __omap_dm_timer_read_counter(timer, timer->posted); |
92105bb7 | 709 | } |
6c366e32 | 710 | EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter); |
92105bb7 | 711 | |
ab4eb8b0 | 712 | int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) |
83379c81 | 713 | { |
ab4eb8b0 TKD |
714 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
715 | pr_err("%s: timer not available or enabled.\n", __func__); | |
716 | return -EINVAL; | |
b481113a TKD |
717 | } |
718 | ||
fa4bb626 | 719 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); |
b481113a TKD |
720 | |
721 | /* Save the context */ | |
722 | timer->context.tcrr = value; | |
ab4eb8b0 | 723 | return 0; |
83379c81 | 724 | } |
6c366e32 | 725 | EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter); |
83379c81 | 726 | |
77900a2f | 727 | int omap_dm_timers_active(void) |
92105bb7 | 728 | { |
3392cdd3 | 729 | struct omap_dm_timer *timer; |
12583a70 | 730 | |
3392cdd3 | 731 | list_for_each_entry(timer, &omap_timer_list, node) { |
ffe07cea | 732 | if (!timer->reserved) |
12583a70 TT |
733 | continue; |
734 | ||
77900a2f | 735 | if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & |
fa4bb626 | 736 | OMAP_TIMER_CTRL_ST) { |
77900a2f | 737 | return 1; |
fa4bb626 | 738 | } |
77900a2f TT |
739 | } |
740 | return 0; | |
741 | } | |
6c366e32 | 742 | EXPORT_SYMBOL_GPL(omap_dm_timers_active); |
92105bb7 | 743 | |
df28472a TKD |
744 | /** |
745 | * omap_dm_timer_probe - probe function called for every registered device | |
746 | * @pdev: pointer to current timer platform device | |
747 | * | |
748 | * Called by driver framework at the end of device registration for all | |
749 | * timer devices. | |
750 | */ | |
751 | static int __devinit omap_dm_timer_probe(struct platform_device *pdev) | |
752 | { | |
df28472a TKD |
753 | unsigned long flags; |
754 | struct omap_dm_timer *timer; | |
74dd9ec6 TKD |
755 | struct resource *mem, *irq; |
756 | struct device *dev = &pdev->dev; | |
df28472a TKD |
757 | struct dmtimer_platform_data *pdata = pdev->dev.platform_data; |
758 | ||
9725f445 | 759 | if (!pdata && !dev->of_node) { |
74dd9ec6 | 760 | dev_err(dev, "%s: no platform data.\n", __func__); |
df28472a TKD |
761 | return -ENODEV; |
762 | } | |
763 | ||
764 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
765 | if (unlikely(!irq)) { | |
74dd9ec6 | 766 | dev_err(dev, "%s: no IRQ resource.\n", __func__); |
df28472a TKD |
767 | return -ENODEV; |
768 | } | |
769 | ||
770 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
771 | if (unlikely(!mem)) { | |
74dd9ec6 | 772 | dev_err(dev, "%s: no memory resource.\n", __func__); |
df28472a TKD |
773 | return -ENODEV; |
774 | } | |
775 | ||
74dd9ec6 | 776 | timer = devm_kzalloc(dev, sizeof(struct omap_dm_timer), GFP_KERNEL); |
df28472a | 777 | if (!timer) { |
74dd9ec6 TKD |
778 | dev_err(dev, "%s: memory alloc failed!\n", __func__); |
779 | return -ENOMEM; | |
df28472a TKD |
780 | } |
781 | ||
74dd9ec6 | 782 | timer->io_base = devm_request_and_ioremap(dev, mem); |
df28472a | 783 | if (!timer->io_base) { |
74dd9ec6 TKD |
784 | dev_err(dev, "%s: region already claimed.\n", __func__); |
785 | return -ENOMEM; | |
df28472a TKD |
786 | } |
787 | ||
9725f445 JH |
788 | if (dev->of_node) { |
789 | if (of_find_property(dev->of_node, "ti,timer-alwon", NULL)) | |
790 | timer->capability |= OMAP_TIMER_ALWON; | |
791 | if (of_find_property(dev->of_node, "ti,timer-dsp", NULL)) | |
792 | timer->capability |= OMAP_TIMER_HAS_DSP_IRQ; | |
793 | if (of_find_property(dev->of_node, "ti,timer-pwm", NULL)) | |
794 | timer->capability |= OMAP_TIMER_HAS_PWM; | |
795 | if (of_find_property(dev->of_node, "ti,timer-secure", NULL)) | |
796 | timer->capability |= OMAP_TIMER_SECURE; | |
797 | } else { | |
798 | timer->id = pdev->id; | |
799 | timer->capability = pdata->timer_capability; | |
800 | timer->reserved = omap_dm_timer_reserved_systimer(timer->id); | |
801 | } | |
802 | ||
df28472a TKD |
803 | timer->irq = irq->start; |
804 | timer->pdev = pdev; | |
df28472a | 805 | |
ffe07cea | 806 | /* Skip pm_runtime_enable for OMAP1 */ |
6615975b | 807 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { |
74dd9ec6 TKD |
808 | pm_runtime_enable(dev); |
809 | pm_runtime_irq_safe(dev); | |
ffe07cea TKD |
810 | } |
811 | ||
0dad9fae | 812 | if (!timer->reserved) { |
74dd9ec6 | 813 | pm_runtime_get_sync(dev); |
0dad9fae | 814 | __omap_dm_timer_init_regs(timer); |
74dd9ec6 | 815 | pm_runtime_put(dev); |
0dad9fae TL |
816 | } |
817 | ||
df28472a TKD |
818 | /* add the timer element to the list */ |
819 | spin_lock_irqsave(&dm_timer_lock, flags); | |
820 | list_add_tail(&timer->node, &omap_timer_list); | |
821 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
822 | ||
74dd9ec6 | 823 | dev_dbg(dev, "Device Probed.\n"); |
df28472a TKD |
824 | |
825 | return 0; | |
df28472a TKD |
826 | } |
827 | ||
828 | /** | |
829 | * omap_dm_timer_remove - cleanup a registered timer device | |
830 | * @pdev: pointer to current timer platform device | |
831 | * | |
832 | * Called by driver framework whenever a timer device is unregistered. | |
833 | * In addition to freeing platform resources it also deletes the timer | |
834 | * entry from the local list. | |
835 | */ | |
836 | static int __devexit omap_dm_timer_remove(struct platform_device *pdev) | |
837 | { | |
838 | struct omap_dm_timer *timer; | |
839 | unsigned long flags; | |
840 | int ret = -EINVAL; | |
841 | ||
842 | spin_lock_irqsave(&dm_timer_lock, flags); | |
843 | list_for_each_entry(timer, &omap_timer_list, node) | |
9725f445 JH |
844 | if (!strcmp(dev_name(&timer->pdev->dev), |
845 | dev_name(&pdev->dev))) { | |
df28472a | 846 | list_del(&timer->node); |
df28472a TKD |
847 | ret = 0; |
848 | break; | |
849 | } | |
850 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
851 | ||
852 | return ret; | |
853 | } | |
854 | ||
9725f445 JH |
855 | static const struct of_device_id omap_timer_match[] = { |
856 | { .compatible = "ti,omap2-timer", }, | |
857 | {}, | |
858 | }; | |
859 | MODULE_DEVICE_TABLE(of, omap_timer_match); | |
860 | ||
df28472a TKD |
861 | static struct platform_driver omap_dm_timer_driver = { |
862 | .probe = omap_dm_timer_probe, | |
4c23c8da | 863 | .remove = __devexit_p(omap_dm_timer_remove), |
df28472a TKD |
864 | .driver = { |
865 | .name = "omap_timer", | |
9725f445 | 866 | .of_match_table = of_match_ptr(omap_timer_match), |
df28472a TKD |
867 | }, |
868 | }; | |
869 | ||
870 | static int __init omap_dm_timer_driver_init(void) | |
871 | { | |
872 | return platform_driver_register(&omap_dm_timer_driver); | |
873 | } | |
874 | ||
875 | static void __exit omap_dm_timer_driver_exit(void) | |
876 | { | |
877 | platform_driver_unregister(&omap_dm_timer_driver); | |
878 | } | |
879 | ||
880 | early_platform_init("earlytimer", &omap_dm_timer_driver); | |
881 | module_init(omap_dm_timer_driver_init); | |
882 | module_exit(omap_dm_timer_driver_exit); | |
883 | ||
884 | MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver"); | |
885 | MODULE_LICENSE("GPL"); | |
886 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
887 | MODULE_AUTHOR("Texas Instruments Inc"); |