Commit | Line | Data |
---|---|---|
92105bb7 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/dmtimer.c | |
3 | * | |
4 | * OMAP Dual-Mode Timers | |
5 | * | |
97933d6c TKD |
6 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ |
7 | * Tarun Kanti DebBarma <tarun.kanti@ti.com> | |
8 | * Thara Gopinath <thara@ti.com> | |
9 | * | |
10 | * dmtimer adaptation to platform_driver. | |
11 | * | |
92105bb7 | 12 | * Copyright (C) 2005 Nokia Corporation |
77900a2f TT |
13 | * OMAP2 support by Juha Yrjola |
14 | * API improvements and OMAP2 clock framework support by Timo Teras | |
92105bb7 | 15 | * |
44169075 SS |
16 | * Copyright (C) 2009 Texas Instruments |
17 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
18 | * | |
92105bb7 TL |
19 | * This program is free software; you can redistribute it and/or modify it |
20 | * under the terms of the GNU General Public License as published by the | |
21 | * Free Software Foundation; either version 2 of the License, or (at your | |
22 | * option) any later version. | |
23 | * | |
24 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
25 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
26 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
27 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
28 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License along | |
34 | * with this program; if not, write to the Free Software Foundation, Inc., | |
35 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
36 | */ | |
37 | ||
b1538832 | 38 | #include <linux/clk.h> |
869dec15 | 39 | #include <linux/module.h> |
fced80c7 | 40 | #include <linux/io.h> |
74dd9ec6 | 41 | #include <linux/device.h> |
3392cdd3 | 42 | #include <linux/err.h> |
ffe07cea | 43 | #include <linux/pm_runtime.h> |
9725f445 JH |
44 | #include <linux/of.h> |
45 | #include <linux/of_device.h> | |
40fc3bb5 JH |
46 | #include <linux/platform_device.h> |
47 | #include <linux/platform_data/dmtimer-omap.h> | |
44169075 | 48 | |
3392cdd3 | 49 | #include <plat/dmtimer.h> |
2c799cef | 50 | |
b7b4ff76 | 51 | static u32 omap_reserved_systimers; |
df28472a | 52 | static LIST_HEAD(omap_timer_list); |
3392cdd3 | 53 | static DEFINE_SPINLOCK(dm_timer_lock); |
92105bb7 | 54 | |
3392cdd3 TKD |
55 | /** |
56 | * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode | |
57 | * @timer: timer pointer over which read operation to perform | |
58 | * @reg: lowest byte holds the register offset | |
59 | * | |
60 | * The posted mode bit is encoded in reg. Note that in posted mode write | |
61 | * pending bit must be checked. Otherwise a read of a non completed write | |
62 | * will produce an error. | |
0f0d0807 RW |
63 | */ |
64 | static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) | |
77900a2f | 65 | { |
ee17f114 TL |
66 | WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
67 | return __omap_dm_timer_read(timer, reg, timer->posted); | |
77900a2f | 68 | } |
92105bb7 | 69 | |
3392cdd3 TKD |
70 | /** |
71 | * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode | |
72 | * @timer: timer pointer over which write operation is to perform | |
73 | * @reg: lowest byte holds the register offset | |
74 | * @value: data to write into the register | |
75 | * | |
76 | * The posted mode bit is encoded in reg. Note that in posted mode the write | |
77 | * pending bit must be checked. Otherwise a write on a register which has a | |
78 | * pending write will be lost. | |
0f0d0807 RW |
79 | */ |
80 | static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, | |
81 | u32 value) | |
92105bb7 | 82 | { |
ee17f114 TL |
83 | WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
84 | __omap_dm_timer_write(timer, reg, value, timer->posted); | |
92105bb7 TL |
85 | } |
86 | ||
b481113a TKD |
87 | static void omap_timer_restore_context(struct omap_dm_timer *timer) |
88 | { | |
b481113a TKD |
89 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, |
90 | timer->context.twer); | |
91 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, | |
92 | timer->context.tcrr); | |
93 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, | |
94 | timer->context.tldr); | |
95 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, | |
96 | timer->context.tmar); | |
97 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, | |
98 | timer->context.tsicr); | |
99 | __raw_writel(timer->context.tier, timer->irq_ena); | |
100 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, | |
101 | timer->context.tclr); | |
102 | } | |
103 | ||
ae6672cb | 104 | static int omap_dm_timer_reset(struct omap_dm_timer *timer) |
92105bb7 | 105 | { |
ae6672cb | 106 | u32 l, timeout = 100000; |
77900a2f | 107 | |
ae6672cb JH |
108 | if (timer->revision != 1) |
109 | return -EINVAL; | |
ee17f114 | 110 | |
ae6672cb JH |
111 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); |
112 | ||
113 | do { | |
114 | l = __omap_dm_timer_read(timer, | |
115 | OMAP_TIMER_V1_SYS_STAT_OFFSET, 0); | |
116 | } while (!l && timeout--); | |
117 | ||
118 | if (!timeout) { | |
119 | dev_err(&timer->pdev->dev, "Timer failed to reset\n"); | |
120 | return -ETIMEDOUT; | |
77900a2f | 121 | } |
92105bb7 | 122 | |
ae6672cb JH |
123 | /* Configure timer for smart-idle mode */ |
124 | l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0); | |
125 | l |= 0x2 << 0x3; | |
126 | __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0); | |
127 | ||
128 | timer->posted = 0; | |
129 | ||
130 | return 0; | |
77900a2f TT |
131 | } |
132 | ||
b0cadb3c | 133 | static int omap_dm_timer_prepare(struct omap_dm_timer *timer) |
77900a2f | 134 | { |
ae6672cb JH |
135 | int rc; |
136 | ||
bca45808 JH |
137 | /* |
138 | * FIXME: OMAP1 devices do not use the clock framework for dmtimers so | |
139 | * do not call clk_get() for these devices. | |
140 | */ | |
141 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { | |
142 | timer->fclk = clk_get(&timer->pdev->dev, "fck"); | |
86287958 | 143 | if (WARN_ON_ONCE(IS_ERR(timer->fclk))) { |
bca45808 JH |
144 | dev_err(&timer->pdev->dev, ": No fclk handle.\n"); |
145 | return -EINVAL; | |
146 | } | |
3392cdd3 TKD |
147 | } |
148 | ||
7b44cf2c JH |
149 | omap_dm_timer_enable(timer); |
150 | ||
ae6672cb JH |
151 | if (timer->capability & OMAP_TIMER_NEEDS_RESET) { |
152 | rc = omap_dm_timer_reset(timer); | |
153 | if (rc) { | |
154 | omap_dm_timer_disable(timer); | |
155 | return rc; | |
156 | } | |
157 | } | |
3392cdd3 | 158 | |
7b44cf2c JH |
159 | __omap_dm_timer_enable_posted(timer); |
160 | omap_dm_timer_disable(timer); | |
3392cdd3 | 161 | |
7b44cf2c | 162 | return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); |
77900a2f TT |
163 | } |
164 | ||
b7b4ff76 JH |
165 | static inline u32 omap_dm_timer_reserved_systimer(int id) |
166 | { | |
167 | return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0; | |
168 | } | |
169 | ||
170 | int omap_dm_timer_reserve_systimer(int id) | |
171 | { | |
172 | if (omap_dm_timer_reserved_systimer(id)) | |
173 | return -ENODEV; | |
174 | ||
175 | omap_reserved_systimers |= (1 << (id - 1)); | |
176 | ||
177 | return 0; | |
178 | } | |
179 | ||
77900a2f TT |
180 | struct omap_dm_timer *omap_dm_timer_request(void) |
181 | { | |
3392cdd3 | 182 | struct omap_dm_timer *timer = NULL, *t; |
77900a2f | 183 | unsigned long flags; |
3392cdd3 | 184 | int ret = 0; |
77900a2f TT |
185 | |
186 | spin_lock_irqsave(&dm_timer_lock, flags); | |
3392cdd3 TKD |
187 | list_for_each_entry(t, &omap_timer_list, node) { |
188 | if (t->reserved) | |
77900a2f TT |
189 | continue; |
190 | ||
3392cdd3 | 191 | timer = t; |
83379c81 | 192 | timer->reserved = 1; |
77900a2f TT |
193 | break; |
194 | } | |
c5491d1a | 195 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
3392cdd3 TKD |
196 | |
197 | if (timer) { | |
198 | ret = omap_dm_timer_prepare(timer); | |
199 | if (ret) { | |
200 | timer->reserved = 0; | |
201 | timer = NULL; | |
202 | } | |
203 | } | |
77900a2f | 204 | |
3392cdd3 TKD |
205 | if (!timer) |
206 | pr_debug("%s: timer request failed!\n", __func__); | |
83379c81 | 207 | |
77900a2f TT |
208 | return timer; |
209 | } | |
6c366e32 | 210 | EXPORT_SYMBOL_GPL(omap_dm_timer_request); |
77900a2f TT |
211 | |
212 | struct omap_dm_timer *omap_dm_timer_request_specific(int id) | |
92105bb7 | 213 | { |
3392cdd3 | 214 | struct omap_dm_timer *timer = NULL, *t; |
77900a2f | 215 | unsigned long flags; |
3392cdd3 | 216 | int ret = 0; |
92105bb7 | 217 | |
9725f445 JH |
218 | /* Requesting timer by ID is not supported when device tree is used */ |
219 | if (of_have_populated_dt()) { | |
220 | pr_warn("%s: Please use omap_dm_timer_request_by_cap()\n", | |
221 | __func__); | |
222 | return NULL; | |
223 | } | |
224 | ||
77900a2f | 225 | spin_lock_irqsave(&dm_timer_lock, flags); |
3392cdd3 TKD |
226 | list_for_each_entry(t, &omap_timer_list, node) { |
227 | if (t->pdev->id == id && !t->reserved) { | |
228 | timer = t; | |
229 | timer->reserved = 1; | |
230 | break; | |
231 | } | |
77900a2f | 232 | } |
c5491d1a | 233 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
92105bb7 | 234 | |
3392cdd3 TKD |
235 | if (timer) { |
236 | ret = omap_dm_timer_prepare(timer); | |
237 | if (ret) { | |
238 | timer->reserved = 0; | |
239 | timer = NULL; | |
240 | } | |
241 | } | |
77900a2f | 242 | |
3392cdd3 TKD |
243 | if (!timer) |
244 | pr_debug("%s: timer%d request failed!\n", __func__, id); | |
83379c81 | 245 | |
77900a2f | 246 | return timer; |
92105bb7 | 247 | } |
6c366e32 | 248 | EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific); |
92105bb7 | 249 | |
373fe0bd JH |
250 | /** |
251 | * omap_dm_timer_request_by_cap - Request a timer by capability | |
252 | * @cap: Bit mask of capabilities to match | |
253 | * | |
254 | * Find a timer based upon capabilities bit mask. Callers of this function | |
255 | * should use the definitions found in the plat/dmtimer.h file under the | |
256 | * comment "timer capabilities used in hwmod database". Returns pointer to | |
257 | * timer handle on success and a NULL pointer on failure. | |
258 | */ | |
259 | struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap) | |
260 | { | |
261 | struct omap_dm_timer *timer = NULL, *t; | |
262 | unsigned long flags; | |
263 | ||
264 | if (!cap) | |
265 | return NULL; | |
266 | ||
267 | spin_lock_irqsave(&dm_timer_lock, flags); | |
268 | list_for_each_entry(t, &omap_timer_list, node) { | |
269 | if ((!t->reserved) && ((t->capability & cap) == cap)) { | |
270 | /* | |
271 | * If timer is not NULL, we have already found one timer | |
272 | * but it was not an exact match because it had more | |
273 | * capabilites that what was required. Therefore, | |
274 | * unreserve the last timer found and see if this one | |
275 | * is a better match. | |
276 | */ | |
277 | if (timer) | |
278 | timer->reserved = 0; | |
279 | ||
280 | timer = t; | |
281 | timer->reserved = 1; | |
282 | ||
283 | /* Exit loop early if we find an exact match */ | |
284 | if (t->capability == cap) | |
285 | break; | |
286 | } | |
287 | } | |
288 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
289 | ||
290 | if (timer && omap_dm_timer_prepare(timer)) { | |
291 | timer->reserved = 0; | |
292 | timer = NULL; | |
293 | } | |
294 | ||
295 | if (!timer) | |
296 | pr_debug("%s: timer request failed!\n", __func__); | |
297 | ||
298 | return timer; | |
299 | } | |
300 | EXPORT_SYMBOL_GPL(omap_dm_timer_request_by_cap); | |
301 | ||
ab4eb8b0 | 302 | int omap_dm_timer_free(struct omap_dm_timer *timer) |
77900a2f | 303 | { |
ab4eb8b0 TKD |
304 | if (unlikely(!timer)) |
305 | return -EINVAL; | |
306 | ||
3392cdd3 | 307 | clk_put(timer->fclk); |
fa4bb626 | 308 | |
77900a2f TT |
309 | WARN_ON(!timer->reserved); |
310 | timer->reserved = 0; | |
ab4eb8b0 | 311 | return 0; |
77900a2f | 312 | } |
6c366e32 | 313 | EXPORT_SYMBOL_GPL(omap_dm_timer_free); |
77900a2f | 314 | |
12583a70 TT |
315 | void omap_dm_timer_enable(struct omap_dm_timer *timer) |
316 | { | |
ffe07cea | 317 | pm_runtime_get_sync(&timer->pdev->dev); |
12583a70 | 318 | } |
6c366e32 | 319 | EXPORT_SYMBOL_GPL(omap_dm_timer_enable); |
12583a70 TT |
320 | |
321 | void omap_dm_timer_disable(struct omap_dm_timer *timer) | |
322 | { | |
54f32a35 | 323 | pm_runtime_put_sync(&timer->pdev->dev); |
12583a70 | 324 | } |
6c366e32 | 325 | EXPORT_SYMBOL_GPL(omap_dm_timer_disable); |
12583a70 | 326 | |
77900a2f TT |
327 | int omap_dm_timer_get_irq(struct omap_dm_timer *timer) |
328 | { | |
ab4eb8b0 TKD |
329 | if (timer) |
330 | return timer->irq; | |
331 | return -EINVAL; | |
77900a2f | 332 | } |
6c366e32 | 333 | EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq); |
77900a2f TT |
334 | |
335 | #if defined(CONFIG_ARCH_OMAP1) | |
7136f8d8 | 336 | #include <mach/hardware.h> |
a569c6ec TL |
337 | /** |
338 | * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR | |
339 | * @inputmask: current value of idlect mask | |
340 | */ | |
341 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) | |
342 | { | |
3392cdd3 TKD |
343 | int i = 0; |
344 | struct omap_dm_timer *timer = NULL; | |
345 | unsigned long flags; | |
a569c6ec TL |
346 | |
347 | /* If ARMXOR cannot be idled this function call is unnecessary */ | |
348 | if (!(inputmask & (1 << 1))) | |
349 | return inputmask; | |
350 | ||
351 | /* If any active timer is using ARMXOR return modified mask */ | |
3392cdd3 TKD |
352 | spin_lock_irqsave(&dm_timer_lock, flags); |
353 | list_for_each_entry(timer, &omap_timer_list, node) { | |
77900a2f TT |
354 | u32 l; |
355 | ||
3392cdd3 | 356 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
357 | if (l & OMAP_TIMER_CTRL_ST) { |
358 | if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0) | |
a569c6ec TL |
359 | inputmask &= ~(1 << 1); |
360 | else | |
361 | inputmask &= ~(1 << 2); | |
362 | } | |
3392cdd3 | 363 | i++; |
77900a2f | 364 | } |
3392cdd3 | 365 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
a569c6ec TL |
366 | |
367 | return inputmask; | |
368 | } | |
6c366e32 | 369 | EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); |
a569c6ec | 370 | |
140455fa | 371 | #else |
a569c6ec | 372 | |
77900a2f | 373 | struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) |
92105bb7 | 374 | { |
86287958 | 375 | if (timer && !IS_ERR(timer->fclk)) |
ab4eb8b0 TKD |
376 | return timer->fclk; |
377 | return NULL; | |
77900a2f | 378 | } |
6c366e32 | 379 | EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk); |
92105bb7 | 380 | |
77900a2f TT |
381 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) |
382 | { | |
383 | BUG(); | |
2121880e DB |
384 | |
385 | return 0; | |
92105bb7 | 386 | } |
6c366e32 | 387 | EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); |
92105bb7 | 388 | |
77900a2f | 389 | #endif |
92105bb7 | 390 | |
ab4eb8b0 | 391 | int omap_dm_timer_trigger(struct omap_dm_timer *timer) |
92105bb7 | 392 | { |
ab4eb8b0 TKD |
393 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
394 | pr_err("%s: timer not available or enabled.\n", __func__); | |
395 | return -EINVAL; | |
b481113a TKD |
396 | } |
397 | ||
77900a2f | 398 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
ab4eb8b0 | 399 | return 0; |
92105bb7 | 400 | } |
6c366e32 | 401 | EXPORT_SYMBOL_GPL(omap_dm_timer_trigger); |
92105bb7 | 402 | |
ab4eb8b0 | 403 | int omap_dm_timer_start(struct omap_dm_timer *timer) |
77900a2f TT |
404 | { |
405 | u32 l; | |
92105bb7 | 406 | |
ab4eb8b0 TKD |
407 | if (unlikely(!timer)) |
408 | return -EINVAL; | |
409 | ||
b481113a TKD |
410 | omap_dm_timer_enable(timer); |
411 | ||
1c2d076b | 412 | if (!(timer->capability & OMAP_TIMER_ALWON)) { |
6e740f9a TL |
413 | if (timer->get_context_loss_count && |
414 | timer->get_context_loss_count(&timer->pdev->dev) != | |
0b30ec1c | 415 | timer->ctx_loss_count) |
b481113a TKD |
416 | omap_timer_restore_context(timer); |
417 | } | |
418 | ||
77900a2f TT |
419 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
420 | if (!(l & OMAP_TIMER_CTRL_ST)) { | |
421 | l |= OMAP_TIMER_CTRL_ST; | |
422 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | |
423 | } | |
b481113a TKD |
424 | |
425 | /* Save the context */ | |
426 | timer->context.tclr = l; | |
ab4eb8b0 | 427 | return 0; |
77900a2f | 428 | } |
6c366e32 | 429 | EXPORT_SYMBOL_GPL(omap_dm_timer_start); |
92105bb7 | 430 | |
ab4eb8b0 | 431 | int omap_dm_timer_stop(struct omap_dm_timer *timer) |
92105bb7 | 432 | { |
caf64f2f | 433 | unsigned long rate = 0; |
92105bb7 | 434 | |
ab4eb8b0 TKD |
435 | if (unlikely(!timer)) |
436 | return -EINVAL; | |
437 | ||
6615975b | 438 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) |
3392cdd3 | 439 | rate = clk_get_rate(timer->fclk); |
caf64f2f | 440 | |
ee17f114 | 441 | __omap_dm_timer_stop(timer, timer->posted, rate); |
ab4eb8b0 | 442 | |
6e740f9a TL |
443 | if (!(timer->capability & OMAP_TIMER_ALWON)) { |
444 | if (timer->get_context_loss_count) | |
445 | timer->ctx_loss_count = | |
446 | timer->get_context_loss_count(&timer->pdev->dev); | |
447 | } | |
dffc9dae TKD |
448 | |
449 | /* | |
450 | * Since the register values are computed and written within | |
451 | * __omap_dm_timer_stop, we need to use read to retrieve the | |
452 | * context. | |
453 | */ | |
454 | timer->context.tclr = | |
455 | omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); | |
dffc9dae | 456 | omap_dm_timer_disable(timer); |
ab4eb8b0 | 457 | return 0; |
92105bb7 | 458 | } |
6c366e32 | 459 | EXPORT_SYMBOL_GPL(omap_dm_timer_stop); |
92105bb7 | 460 | |
f248076c | 461 | int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) |
92105bb7 | 462 | { |
3392cdd3 | 463 | int ret; |
2b2d3523 | 464 | char *parent_name = NULL; |
d7aba554 | 465 | struct clk *parent; |
ab4eb8b0 TKD |
466 | struct dmtimer_platform_data *pdata; |
467 | ||
468 | if (unlikely(!timer)) | |
469 | return -EINVAL; | |
470 | ||
471 | pdata = timer->pdev->dev.platform_data; | |
3392cdd3 | 472 | |
77900a2f | 473 | if (source < 0 || source >= 3) |
f248076c | 474 | return -EINVAL; |
77900a2f | 475 | |
2b2d3523 JH |
476 | /* |
477 | * FIXME: Used for OMAP1 devices only because they do not currently | |
478 | * use the clock framework to set the parent clock. To be removed | |
479 | * once OMAP1 migrated to using clock framework for dmtimers | |
480 | */ | |
9725f445 | 481 | if (pdata && pdata->set_timer_src) |
2b2d3523 JH |
482 | return pdata->set_timer_src(timer->pdev, source); |
483 | ||
86287958 | 484 | if (IS_ERR(timer->fclk)) |
2b2d3523 | 485 | return -EINVAL; |
2b2d3523 JH |
486 | |
487 | switch (source) { | |
488 | case OMAP_TIMER_SRC_SYS_CLK: | |
c59b537d | 489 | parent_name = "timer_sys_ck"; |
2b2d3523 JH |
490 | break; |
491 | ||
492 | case OMAP_TIMER_SRC_32_KHZ: | |
c59b537d | 493 | parent_name = "timer_32k_ck"; |
2b2d3523 JH |
494 | break; |
495 | ||
496 | case OMAP_TIMER_SRC_EXT_CLK: | |
c59b537d | 497 | parent_name = "timer_ext_ck"; |
2b2d3523 JH |
498 | break; |
499 | } | |
500 | ||
501 | parent = clk_get(&timer->pdev->dev, parent_name); | |
86287958 | 502 | if (IS_ERR(parent)) { |
2b2d3523 | 503 | pr_err("%s: %s not found\n", __func__, parent_name); |
d7aba554 | 504 | return -EINVAL; |
2b2d3523 JH |
505 | } |
506 | ||
d7aba554 | 507 | ret = clk_set_parent(timer->fclk, parent); |
c48cd659 | 508 | if (ret < 0) |
2b2d3523 JH |
509 | pr_err("%s: failed to set %s as parent\n", __func__, |
510 | parent_name); | |
511 | ||
512 | clk_put(parent); | |
3392cdd3 TKD |
513 | |
514 | return ret; | |
92105bb7 | 515 | } |
6c366e32 | 516 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); |
92105bb7 | 517 | |
ab4eb8b0 | 518 | int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, |
77900a2f | 519 | unsigned int load) |
92105bb7 TL |
520 | { |
521 | u32 l; | |
77900a2f | 522 | |
ab4eb8b0 TKD |
523 | if (unlikely(!timer)) |
524 | return -EINVAL; | |
525 | ||
b481113a | 526 | omap_dm_timer_enable(timer); |
92105bb7 | 527 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
528 | if (autoreload) |
529 | l |= OMAP_TIMER_CTRL_AR; | |
530 | else | |
531 | l &= ~OMAP_TIMER_CTRL_AR; | |
92105bb7 | 532 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
77900a2f | 533 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); |
0f0d0807 | 534 | |
77900a2f | 535 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
b481113a TKD |
536 | /* Save the context */ |
537 | timer->context.tclr = l; | |
538 | timer->context.tldr = load; | |
539 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 540 | return 0; |
92105bb7 | 541 | } |
6c366e32 | 542 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_load); |
92105bb7 | 543 | |
3fddd09e | 544 | /* Optimized set_load which removes costly spin wait in timer_start */ |
ab4eb8b0 | 545 | int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, |
3fddd09e RW |
546 | unsigned int load) |
547 | { | |
548 | u32 l; | |
549 | ||
ab4eb8b0 TKD |
550 | if (unlikely(!timer)) |
551 | return -EINVAL; | |
552 | ||
b481113a TKD |
553 | omap_dm_timer_enable(timer); |
554 | ||
1c2d076b | 555 | if (!(timer->capability & OMAP_TIMER_ALWON)) { |
6e740f9a TL |
556 | if (timer->get_context_loss_count && |
557 | timer->get_context_loss_count(&timer->pdev->dev) != | |
0b30ec1c | 558 | timer->ctx_loss_count) |
b481113a TKD |
559 | omap_timer_restore_context(timer); |
560 | } | |
561 | ||
3fddd09e | 562 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
64ce2907 | 563 | if (autoreload) { |
3fddd09e | 564 | l |= OMAP_TIMER_CTRL_AR; |
64ce2907 PW |
565 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); |
566 | } else { | |
3fddd09e | 567 | l &= ~OMAP_TIMER_CTRL_AR; |
64ce2907 | 568 | } |
3fddd09e RW |
569 | l |= OMAP_TIMER_CTRL_ST; |
570 | ||
ee17f114 | 571 | __omap_dm_timer_load_start(timer, l, load, timer->posted); |
b481113a TKD |
572 | |
573 | /* Save the context */ | |
574 | timer->context.tclr = l; | |
575 | timer->context.tldr = load; | |
576 | timer->context.tcrr = load; | |
ab4eb8b0 | 577 | return 0; |
3fddd09e | 578 | } |
6c366e32 | 579 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start); |
3fddd09e | 580 | |
ab4eb8b0 | 581 | int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, |
77900a2f | 582 | unsigned int match) |
92105bb7 TL |
583 | { |
584 | u32 l; | |
585 | ||
ab4eb8b0 TKD |
586 | if (unlikely(!timer)) |
587 | return -EINVAL; | |
588 | ||
b481113a | 589 | omap_dm_timer_enable(timer); |
92105bb7 | 590 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
83379c81 | 591 | if (enable) |
77900a2f TT |
592 | l |= OMAP_TIMER_CTRL_CE; |
593 | else | |
594 | l &= ~OMAP_TIMER_CTRL_CE; | |
77900a2f | 595 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); |
991ad16a | 596 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
597 | |
598 | /* Save the context */ | |
599 | timer->context.tclr = l; | |
600 | timer->context.tmar = match; | |
601 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 602 | return 0; |
92105bb7 | 603 | } |
6c366e32 | 604 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_match); |
92105bb7 | 605 | |
ab4eb8b0 | 606 | int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, |
77900a2f | 607 | int toggle, int trigger) |
92105bb7 TL |
608 | { |
609 | u32 l; | |
610 | ||
ab4eb8b0 TKD |
611 | if (unlikely(!timer)) |
612 | return -EINVAL; | |
613 | ||
b481113a | 614 | omap_dm_timer_enable(timer); |
92105bb7 | 615 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
616 | l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | |
617 | OMAP_TIMER_CTRL_PT | (0x03 << 10)); | |
618 | if (def_on) | |
619 | l |= OMAP_TIMER_CTRL_SCPWM; | |
620 | if (toggle) | |
621 | l |= OMAP_TIMER_CTRL_PT; | |
622 | l |= trigger << 10; | |
92105bb7 | 623 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
624 | |
625 | /* Save the context */ | |
626 | timer->context.tclr = l; | |
627 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 628 | return 0; |
92105bb7 | 629 | } |
6c366e32 | 630 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm); |
92105bb7 | 631 | |
ab4eb8b0 | 632 | int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler) |
92105bb7 TL |
633 | { |
634 | u32 l; | |
635 | ||
ab4eb8b0 TKD |
636 | if (unlikely(!timer)) |
637 | return -EINVAL; | |
638 | ||
b481113a | 639 | omap_dm_timer_enable(timer); |
92105bb7 | 640 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
641 | l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); |
642 | if (prescaler >= 0x00 && prescaler <= 0x07) { | |
643 | l |= OMAP_TIMER_CTRL_PRE; | |
644 | l |= prescaler << 2; | |
645 | } | |
92105bb7 | 646 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
647 | |
648 | /* Save the context */ | |
649 | timer->context.tclr = l; | |
650 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 651 | return 0; |
92105bb7 | 652 | } |
6c366e32 | 653 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler); |
92105bb7 | 654 | |
ab4eb8b0 | 655 | int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, |
77900a2f | 656 | unsigned int value) |
92105bb7 | 657 | { |
ab4eb8b0 TKD |
658 | if (unlikely(!timer)) |
659 | return -EINVAL; | |
660 | ||
b481113a | 661 | omap_dm_timer_enable(timer); |
ee17f114 | 662 | __omap_dm_timer_int_enable(timer, value); |
b481113a TKD |
663 | |
664 | /* Save the context */ | |
665 | timer->context.tier = value; | |
666 | timer->context.twer = value; | |
667 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 668 | return 0; |
92105bb7 | 669 | } |
6c366e32 | 670 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable); |
92105bb7 | 671 | |
4249d96c JH |
672 | /** |
673 | * omap_dm_timer_set_int_disable - disable timer interrupts | |
674 | * @timer: pointer to timer handle | |
675 | * @mask: bit mask of interrupts to be disabled | |
676 | * | |
677 | * Disables the specified timer interrupts for a timer. | |
678 | */ | |
679 | int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask) | |
680 | { | |
681 | u32 l = mask; | |
682 | ||
683 | if (unlikely(!timer)) | |
684 | return -EINVAL; | |
685 | ||
686 | omap_dm_timer_enable(timer); | |
687 | ||
688 | if (timer->revision == 1) | |
689 | l = __raw_readl(timer->irq_ena) & ~mask; | |
690 | ||
691 | __raw_writel(l, timer->irq_dis); | |
692 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; | |
693 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l); | |
694 | ||
695 | /* Save the context */ | |
696 | timer->context.tier &= ~mask; | |
697 | timer->context.twer &= ~mask; | |
698 | omap_dm_timer_disable(timer); | |
699 | return 0; | |
700 | } | |
701 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_disable); | |
702 | ||
77900a2f | 703 | unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) |
92105bb7 | 704 | { |
fa4bb626 TT |
705 | unsigned int l; |
706 | ||
ab4eb8b0 TKD |
707 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
708 | pr_err("%s: timer not available or enabled.\n", __func__); | |
b481113a TKD |
709 | return 0; |
710 | } | |
711 | ||
ee17f114 | 712 | l = __raw_readl(timer->irq_stat); |
fa4bb626 TT |
713 | |
714 | return l; | |
92105bb7 | 715 | } |
6c366e32 | 716 | EXPORT_SYMBOL_GPL(omap_dm_timer_read_status); |
92105bb7 | 717 | |
ab4eb8b0 | 718 | int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) |
92105bb7 | 719 | { |
ab4eb8b0 TKD |
720 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) |
721 | return -EINVAL; | |
722 | ||
ee17f114 | 723 | __omap_dm_timer_write_status(timer, value); |
1eaff710 | 724 | |
ab4eb8b0 | 725 | return 0; |
92105bb7 | 726 | } |
6c366e32 | 727 | EXPORT_SYMBOL_GPL(omap_dm_timer_write_status); |
92105bb7 | 728 | |
77900a2f | 729 | unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) |
92105bb7 | 730 | { |
ab4eb8b0 TKD |
731 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
732 | pr_err("%s: timer not iavailable or enabled.\n", __func__); | |
b481113a TKD |
733 | return 0; |
734 | } | |
735 | ||
ee17f114 | 736 | return __omap_dm_timer_read_counter(timer, timer->posted); |
92105bb7 | 737 | } |
6c366e32 | 738 | EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter); |
92105bb7 | 739 | |
ab4eb8b0 | 740 | int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) |
83379c81 | 741 | { |
ab4eb8b0 TKD |
742 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
743 | pr_err("%s: timer not available or enabled.\n", __func__); | |
744 | return -EINVAL; | |
b481113a TKD |
745 | } |
746 | ||
fa4bb626 | 747 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); |
b481113a TKD |
748 | |
749 | /* Save the context */ | |
750 | timer->context.tcrr = value; | |
ab4eb8b0 | 751 | return 0; |
83379c81 | 752 | } |
6c366e32 | 753 | EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter); |
83379c81 | 754 | |
77900a2f | 755 | int omap_dm_timers_active(void) |
92105bb7 | 756 | { |
3392cdd3 | 757 | struct omap_dm_timer *timer; |
12583a70 | 758 | |
3392cdd3 | 759 | list_for_each_entry(timer, &omap_timer_list, node) { |
ffe07cea | 760 | if (!timer->reserved) |
12583a70 TT |
761 | continue; |
762 | ||
77900a2f | 763 | if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & |
fa4bb626 | 764 | OMAP_TIMER_CTRL_ST) { |
77900a2f | 765 | return 1; |
fa4bb626 | 766 | } |
77900a2f TT |
767 | } |
768 | return 0; | |
769 | } | |
6c366e32 | 770 | EXPORT_SYMBOL_GPL(omap_dm_timers_active); |
92105bb7 | 771 | |
df28472a TKD |
772 | /** |
773 | * omap_dm_timer_probe - probe function called for every registered device | |
774 | * @pdev: pointer to current timer platform device | |
775 | * | |
776 | * Called by driver framework at the end of device registration for all | |
777 | * timer devices. | |
778 | */ | |
351a102d | 779 | static int omap_dm_timer_probe(struct platform_device *pdev) |
df28472a | 780 | { |
df28472a TKD |
781 | unsigned long flags; |
782 | struct omap_dm_timer *timer; | |
74dd9ec6 TKD |
783 | struct resource *mem, *irq; |
784 | struct device *dev = &pdev->dev; | |
df28472a TKD |
785 | struct dmtimer_platform_data *pdata = pdev->dev.platform_data; |
786 | ||
9725f445 | 787 | if (!pdata && !dev->of_node) { |
74dd9ec6 | 788 | dev_err(dev, "%s: no platform data.\n", __func__); |
df28472a TKD |
789 | return -ENODEV; |
790 | } | |
791 | ||
792 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
793 | if (unlikely(!irq)) { | |
74dd9ec6 | 794 | dev_err(dev, "%s: no IRQ resource.\n", __func__); |
df28472a TKD |
795 | return -ENODEV; |
796 | } | |
797 | ||
798 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
799 | if (unlikely(!mem)) { | |
74dd9ec6 | 800 | dev_err(dev, "%s: no memory resource.\n", __func__); |
df28472a TKD |
801 | return -ENODEV; |
802 | } | |
803 | ||
74dd9ec6 | 804 | timer = devm_kzalloc(dev, sizeof(struct omap_dm_timer), GFP_KERNEL); |
df28472a | 805 | if (!timer) { |
74dd9ec6 TKD |
806 | dev_err(dev, "%s: memory alloc failed!\n", __func__); |
807 | return -ENOMEM; | |
df28472a TKD |
808 | } |
809 | ||
86287958 | 810 | timer->fclk = ERR_PTR(-ENODEV); |
74dd9ec6 | 811 | timer->io_base = devm_request_and_ioremap(dev, mem); |
df28472a | 812 | if (!timer->io_base) { |
74dd9ec6 TKD |
813 | dev_err(dev, "%s: region already claimed.\n", __func__); |
814 | return -ENOMEM; | |
df28472a TKD |
815 | } |
816 | ||
9725f445 JH |
817 | if (dev->of_node) { |
818 | if (of_find_property(dev->of_node, "ti,timer-alwon", NULL)) | |
819 | timer->capability |= OMAP_TIMER_ALWON; | |
820 | if (of_find_property(dev->of_node, "ti,timer-dsp", NULL)) | |
821 | timer->capability |= OMAP_TIMER_HAS_DSP_IRQ; | |
822 | if (of_find_property(dev->of_node, "ti,timer-pwm", NULL)) | |
823 | timer->capability |= OMAP_TIMER_HAS_PWM; | |
824 | if (of_find_property(dev->of_node, "ti,timer-secure", NULL)) | |
825 | timer->capability |= OMAP_TIMER_SECURE; | |
826 | } else { | |
827 | timer->id = pdev->id; | |
bfd6d021 | 828 | timer->errata = pdata->timer_errata; |
9725f445 JH |
829 | timer->capability = pdata->timer_capability; |
830 | timer->reserved = omap_dm_timer_reserved_systimer(timer->id); | |
f56f52e0 | 831 | timer->get_context_loss_count = pdata->get_context_loss_count; |
9725f445 JH |
832 | } |
833 | ||
df28472a TKD |
834 | timer->irq = irq->start; |
835 | timer->pdev = pdev; | |
df28472a | 836 | |
ffe07cea | 837 | /* Skip pm_runtime_enable for OMAP1 */ |
6615975b | 838 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { |
74dd9ec6 TKD |
839 | pm_runtime_enable(dev); |
840 | pm_runtime_irq_safe(dev); | |
ffe07cea TKD |
841 | } |
842 | ||
0dad9fae | 843 | if (!timer->reserved) { |
74dd9ec6 | 844 | pm_runtime_get_sync(dev); |
0dad9fae | 845 | __omap_dm_timer_init_regs(timer); |
74dd9ec6 | 846 | pm_runtime_put(dev); |
0dad9fae TL |
847 | } |
848 | ||
df28472a TKD |
849 | /* add the timer element to the list */ |
850 | spin_lock_irqsave(&dm_timer_lock, flags); | |
851 | list_add_tail(&timer->node, &omap_timer_list); | |
852 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
853 | ||
74dd9ec6 | 854 | dev_dbg(dev, "Device Probed.\n"); |
df28472a TKD |
855 | |
856 | return 0; | |
df28472a TKD |
857 | } |
858 | ||
859 | /** | |
860 | * omap_dm_timer_remove - cleanup a registered timer device | |
861 | * @pdev: pointer to current timer platform device | |
862 | * | |
863 | * Called by driver framework whenever a timer device is unregistered. | |
864 | * In addition to freeing platform resources it also deletes the timer | |
865 | * entry from the local list. | |
866 | */ | |
351a102d | 867 | static int omap_dm_timer_remove(struct platform_device *pdev) |
df28472a TKD |
868 | { |
869 | struct omap_dm_timer *timer; | |
870 | unsigned long flags; | |
871 | int ret = -EINVAL; | |
872 | ||
873 | spin_lock_irqsave(&dm_timer_lock, flags); | |
874 | list_for_each_entry(timer, &omap_timer_list, node) | |
9725f445 JH |
875 | if (!strcmp(dev_name(&timer->pdev->dev), |
876 | dev_name(&pdev->dev))) { | |
df28472a | 877 | list_del(&timer->node); |
df28472a TKD |
878 | ret = 0; |
879 | break; | |
880 | } | |
881 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
882 | ||
883 | return ret; | |
884 | } | |
885 | ||
9725f445 JH |
886 | static const struct of_device_id omap_timer_match[] = { |
887 | { .compatible = "ti,omap2-timer", }, | |
888 | {}, | |
889 | }; | |
890 | MODULE_DEVICE_TABLE(of, omap_timer_match); | |
891 | ||
df28472a TKD |
892 | static struct platform_driver omap_dm_timer_driver = { |
893 | .probe = omap_dm_timer_probe, | |
351a102d | 894 | .remove = omap_dm_timer_remove, |
df28472a TKD |
895 | .driver = { |
896 | .name = "omap_timer", | |
9725f445 | 897 | .of_match_table = of_match_ptr(omap_timer_match), |
df28472a TKD |
898 | }, |
899 | }; | |
900 | ||
df28472a | 901 | early_platform_init("earlytimer", &omap_dm_timer_driver); |
e4e9f7ea | 902 | module_platform_driver(omap_dm_timer_driver); |
df28472a TKD |
903 | |
904 | MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver"); | |
905 | MODULE_LICENSE("GPL"); | |
906 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
907 | MODULE_AUTHOR("Texas Instruments Inc"); |