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ARM: OMAP: Fix clockevent support for hrtimers
[deliverable/linux.git] / arch / arm / plat-omap / gpio.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
92105bb7 6 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4
TL		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
5e1c5ff4
TL		 14#include <linux/init.h>
15#include <linux/module.h>
5e1c5ff4 16#include <linux/interrupt.h>
92105bb7
TL		 17#include <linux/sysdev.h>
18#include <linux/err.h>
f8ce2547 19#include <linux/clk.h>
5e1c5ff4
TL		 20
21#include <asm/hardware.h>
22#include <asm/irq.h>
23#include <asm/arch/irqs.h>
24#include <asm/arch/gpio.h>
25#include <asm/mach/irq.h>
26
27#include <asm/io.h>
28
29/*
30 * OMAP1510 GPIO registers
31 */
92105bb7 32#define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
5e1c5ff4
TL		 33#define OMAP1510_GPIO_DATA_INPUT 0x00
34#define OMAP1510_GPIO_DATA_OUTPUT 0x04
35#define OMAP1510_GPIO_DIR_CONTROL 0x08
36#define OMAP1510_GPIO_INT_CONTROL 0x0c
37#define OMAP1510_GPIO_INT_MASK 0x10
38#define OMAP1510_GPIO_INT_STATUS 0x14
39#define OMAP1510_GPIO_PIN_CONTROL 0x18
40
41#define OMAP1510_IH_GPIO_BASE 64
42
43/*
44 * OMAP1610 specific GPIO registers
45 */
92105bb7
TL		 46#define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
47#define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
48#define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
49#define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
5e1c5ff4
TL		 50#define OMAP1610_GPIO_REVISION 0x0000
51#define OMAP1610_GPIO_SYSCONFIG 0x0010
52#define OMAP1610_GPIO_SYSSTATUS 0x0014
53#define OMAP1610_GPIO_IRQSTATUS1 0x0018
54#define OMAP1610_GPIO_IRQENABLE1 0x001c
92105bb7 55#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
5e1c5ff4
TL		 56#define OMAP1610_GPIO_DATAIN 0x002c
57#define OMAP1610_GPIO_DATAOUT 0x0030
58#define OMAP1610_GPIO_DIRECTION 0x0034
59#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
60#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
61#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
92105bb7 62#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
5e1c5ff4
TL		 63#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
64#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
92105bb7 65#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
5e1c5ff4
TL		 66#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
67
68/*
69 * OMAP730 specific GPIO registers
70 */
92105bb7
TL		 71#define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
72#define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
73#define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
74#define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
75#define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
76#define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
5e1c5ff4
TL		 77#define OMAP730_GPIO_DATA_INPUT 0x00
78#define OMAP730_GPIO_DATA_OUTPUT 0x04
79#define OMAP730_GPIO_DIR_CONTROL 0x08
80#define OMAP730_GPIO_INT_CONTROL 0x0c
81#define OMAP730_GPIO_INT_MASK 0x10
82#define OMAP730_GPIO_INT_STATUS 0x14
83
92105bb7
TL		 84/*
85 * omap24xx specific GPIO registers
86 */
56a25641
SMK		 87#define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000
88#define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000
89#define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000
90#define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000
91
92#define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000
93#define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000
94#define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000
95#define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000
96#define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000
97
92105bb7
TL		 98#define OMAP24XX_GPIO_REVISION 0x0000
99#define OMAP24XX_GPIO_SYSCONFIG 0x0010
100#define OMAP24XX_GPIO_SYSSTATUS 0x0014
101#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
bee7930f
HD		 102#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
103#define OMAP24XX_GPIO_IRQENABLE2 0x002c
92105bb7
TL		 104#define OMAP24XX_GPIO_IRQENABLE1 0x001c
105#define OMAP24XX_GPIO_CTRL 0x0030
106#define OMAP24XX_GPIO_OE 0x0034
107#define OMAP24XX_GPIO_DATAIN 0x0038
108#define OMAP24XX_GPIO_DATAOUT 0x003c
109#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
110#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
111#define OMAP24XX_GPIO_RISINGDETECT 0x0048
112#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
5eb3bb9c
KH		 113#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
114#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
92105bb7
TL		 115#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
116#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
117#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
118#define OMAP24XX_GPIO_SETWKUENA 0x0084
119#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
120#define OMAP24XX_GPIO_SETDATAOUT 0x0094
121
5492fb1a
SMK		 122/*
123 * omap34xx specific GPIO registers
124 */
125
126#define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000
127#define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000
128#define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000
129#define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000
130#define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000
131#define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000
132
133
5e1c5ff4 134struct gpio_bank {
92105bb7 135 void __iomem *base;
5e1c5ff4
TL		 136 u16 irq;
137 u16 virtual_irq_start;
92105bb7 138 int method;
5e1c5ff4 139 u32 reserved_map;
5492fb1a 140#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 141 u32 suspend_wakeup;
142 u32 saved_wakeup;
3ac4fa99 143#endif
5492fb1a 144#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 145 u32 non_wakeup_gpios;
146 u32 enabled_non_wakeup_gpios;
147
148 u32 saved_datain;
149 u32 saved_fallingdetect;
150 u32 saved_risingdetect;
151#endif
5e1c5ff4
TL		 152 spinlock_t lock;
153};
154
155#define METHOD_MPUIO 0
156#define METHOD_GPIO_1510 1
157#define METHOD_GPIO_1610 2
158#define METHOD_GPIO_730 3
92105bb7 159#define METHOD_GPIO_24XX 4
5e1c5ff4 160
92105bb7 161#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 162static struct gpio_bank gpio_bank_1610[5] = {
163 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
164 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
165 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
166 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
167 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
168};
169#endif
170
1a8bfa1e 171#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 172static struct gpio_bank gpio_bank_1510[2] = {
173 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
174 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
175};
176#endif
177
178#ifdef CONFIG_ARCH_OMAP730
179static struct gpio_bank gpio_bank_730[7] = {
180 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
181 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
182 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
183 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
184 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
185 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
186 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
187};
188#endif
189
92105bb7 190#ifdef CONFIG_ARCH_OMAP24XX
56a25641
SMK		 191
192static struct gpio_bank gpio_bank_242x[4] = {
193 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
194 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
195 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
196 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
92105bb7 197};
56a25641
SMK		 198
199static struct gpio_bank gpio_bank_243x[5] = {
200 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
201 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
202 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
203 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
205};
206
92105bb7
TL		 207#endif
208
5492fb1a
SMK		 209#ifdef CONFIG_ARCH_OMAP34XX
210static struct gpio_bank gpio_bank_34xx[6] = {
211 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
212 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
213 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
214 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
217};
218
219#endif
220
5e1c5ff4
TL		 221static struct gpio_bank *gpio_bank;
222static int gpio_bank_count;
223
224static inline struct gpio_bank *get_gpio_bank(int gpio)
225{
6e60e79a 226 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 227 if (OMAP_GPIO_IS_MPUIO(gpio))
228 return &gpio_bank[0];
229 return &gpio_bank[1];
230 }
5e1c5ff4
TL		 231 if (cpu_is_omap16xx()) {
232 if (OMAP_GPIO_IS_MPUIO(gpio))
233 return &gpio_bank[0];
234 return &gpio_bank[1 + (gpio >> 4)];
235 }
5e1c5ff4
TL		 236 if (cpu_is_omap730()) {
237 if (OMAP_GPIO_IS_MPUIO(gpio))
238 return &gpio_bank[0];
239 return &gpio_bank[1 + (gpio >> 5)];
240 }
92105bb7
TL		 241 if (cpu_is_omap24xx())
242 return &gpio_bank[gpio >> 5];
5492fb1a
SMK		 243 if (cpu_is_omap34xx())
244 return &gpio_bank[gpio >> 5];
5e1c5ff4
TL		 245}
246
247static inline int get_gpio_index(int gpio)
248{
249 if (cpu_is_omap730())
250 return gpio & 0x1f;
92105bb7
TL		 251 if (cpu_is_omap24xx())
252 return gpio & 0x1f;
5492fb1a
SMK		 253 if (cpu_is_omap34xx())
254 return gpio & 0x1f;
92105bb7 255 return gpio & 0x0f;
5e1c5ff4
TL		 256}
257
258static inline int gpio_valid(int gpio)
259{
260 if (gpio < 0)
261 return -1;
d11ac979 262 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
193e68be 263 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
5e1c5ff4
TL		 264 return -1;
265 return 0;
266 }
6e60e79a 267 if (cpu_is_omap15xx() && gpio < 16)
5e1c5ff4 268 return 0;
5e1c5ff4
TL		 269 if ((cpu_is_omap16xx()) && gpio < 64)
270 return 0;
5e1c5ff4
TL		 271 if (cpu_is_omap730() && gpio < 192)
272 return 0;
92105bb7
TL		 273 if (cpu_is_omap24xx() && gpio < 128)
274 return 0;
5492fb1a
SMK		 275 if (cpu_is_omap34xx() && gpio < 160)
276 return 0;
5e1c5ff4
TL		 277 return -1;
278}
279
280static int check_gpio(int gpio)
281{
282 if (unlikely(gpio_valid(gpio)) < 0) {
283 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
284 dump_stack();
285 return -1;
286 }
287 return 0;
288}
289
290static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
291{
92105bb7 292 void __iomem *reg = bank->base;
5e1c5ff4
TL		 293 u32 l;
294
295 switch (bank->method) {
e5c56ed3 296#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 297 case METHOD_MPUIO:
298 reg += OMAP_MPUIO_IO_CNTL;
299 break;
e5c56ed3
DB		 300#endif
301#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 302 case METHOD_GPIO_1510:
303 reg += OMAP1510_GPIO_DIR_CONTROL;
304 break;
e5c56ed3
DB		 305#endif
306#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 307 case METHOD_GPIO_1610:
308 reg += OMAP1610_GPIO_DIRECTION;
309 break;
e5c56ed3
DB		 310#endif
311#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 312 case METHOD_GPIO_730:
313 reg += OMAP730_GPIO_DIR_CONTROL;
314 break;
e5c56ed3 315#endif
5492fb1a 316#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 317 case METHOD_GPIO_24XX:
318 reg += OMAP24XX_GPIO_OE;
319 break;
e5c56ed3
DB		 320#endif
321 default:
322 WARN_ON(1);
323 return;
5e1c5ff4
TL		 324 }
325 l = __raw_readl(reg);
326 if (is_input)
327 l |= 1 << gpio;
328 else
329 l &= ~(1 << gpio);
330 __raw_writel(l, reg);
331}
332
333void omap_set_gpio_direction(int gpio, int is_input)
334{
335 struct gpio_bank *bank;
a6472533 336 unsigned long flags;
5e1c5ff4
TL		 337
338 if (check_gpio(gpio) < 0)
339 return;
340 bank = get_gpio_bank(gpio);
a6472533 341 spin_lock_irqsave(&bank->lock, flags);
5e1c5ff4 342 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
a6472533 343 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 344}
345
346static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
347{
92105bb7 348 void __iomem *reg = bank->base;
5e1c5ff4
TL		 349 u32 l = 0;
350
351 switch (bank->method) {
e5c56ed3 352#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 353 case METHOD_MPUIO:
354 reg += OMAP_MPUIO_OUTPUT;
355 l = __raw_readl(reg);
356 if (enable)
357 l |= 1 << gpio;
358 else
359 l &= ~(1 << gpio);
360 break;
e5c56ed3
DB		 361#endif
362#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 363 case METHOD_GPIO_1510:
364 reg += OMAP1510_GPIO_DATA_OUTPUT;
365 l = __raw_readl(reg);
366 if (enable)
367 l |= 1 << gpio;
368 else
369 l &= ~(1 << gpio);
370 break;
e5c56ed3
DB		 371#endif
372#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 373 case METHOD_GPIO_1610:
374 if (enable)
375 reg += OMAP1610_GPIO_SET_DATAOUT;
376 else
377 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
378 l = 1 << gpio;
379 break;
e5c56ed3
DB		 380#endif
381#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 382 case METHOD_GPIO_730:
383 reg += OMAP730_GPIO_DATA_OUTPUT;
384 l = __raw_readl(reg);
385 if (enable)
386 l |= 1 << gpio;
387 else
388 l &= ~(1 << gpio);
389 break;
e5c56ed3 390#endif
5492fb1a 391#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 392 case METHOD_GPIO_24XX:
393 if (enable)
394 reg += OMAP24XX_GPIO_SETDATAOUT;
395 else
396 reg += OMAP24XX_GPIO_CLEARDATAOUT;
397 l = 1 << gpio;
398 break;
e5c56ed3 399#endif
5e1c5ff4 400 default:
e5c56ed3 401 WARN_ON(1);
5e1c5ff4
TL		 402 return;
403 }
404 __raw_writel(l, reg);
405}
406
407void omap_set_gpio_dataout(int gpio, int enable)
408{
409 struct gpio_bank *bank;
a6472533 410 unsigned long flags;
5e1c5ff4
TL		 411
412 if (check_gpio(gpio) < 0)
413 return;
414 bank = get_gpio_bank(gpio);
a6472533 415 spin_lock_irqsave(&bank->lock, flags);
5e1c5ff4 416 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
a6472533 417 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 418}
419
420int omap_get_gpio_datain(int gpio)
421{
422 struct gpio_bank *bank;
92105bb7 423 void __iomem *reg;
5e1c5ff4
TL		 424
425 if (check_gpio(gpio) < 0)
e5c56ed3 426 return -EINVAL;
5e1c5ff4
TL		 427 bank = get_gpio_bank(gpio);
428 reg = bank->base;
429 switch (bank->method) {
e5c56ed3 430#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 431 case METHOD_MPUIO:
432 reg += OMAP_MPUIO_INPUT_LATCH;
433 break;
e5c56ed3
DB		 434#endif
435#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 436 case METHOD_GPIO_1510:
437 reg += OMAP1510_GPIO_DATA_INPUT;
438 break;
e5c56ed3
DB		 439#endif
440#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 441 case METHOD_GPIO_1610:
442 reg += OMAP1610_GPIO_DATAIN;
443 break;
e5c56ed3
DB		 444#endif
445#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 446 case METHOD_GPIO_730:
447 reg += OMAP730_GPIO_DATA_INPUT;
448 break;
e5c56ed3 449#endif
5492fb1a 450#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 451 case METHOD_GPIO_24XX:
452 reg += OMAP24XX_GPIO_DATAIN;
453 break;
e5c56ed3 454#endif
5e1c5ff4 455 default:
e5c56ed3 456 return -EINVAL;
5e1c5ff4 457 }
92105bb7
TL		 458 return (__raw_readl(reg)
459 & (1 << get_gpio_index(gpio))) != 0;
5e1c5ff4
TL		 460}
461
92105bb7
TL		 462#define MOD_REG_BIT(reg, bit_mask, set) \
463do { \
464 int l = __raw_readl(base + reg); \
465 if (set) l |= bit_mask; \
466 else l &= ~bit_mask; \
467 __raw_writel(l, base + reg); \
468} while(0)
469
5eb3bb9c
KH		 470void omap_set_gpio_debounce(int gpio, int enable)
471{
472 struct gpio_bank *bank;
473 void __iomem *reg;
474 u32 val, l = 1 << get_gpio_index(gpio);
475
476 if (cpu_class_is_omap1())
477 return;
478
479 bank = get_gpio_bank(gpio);
480 reg = bank->base;
481
482 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
483 val = __raw_readl(reg);
484
485 if (enable)
486 val |= l;
487 else
488 val &= ~l;
489
490 __raw_writel(val, reg);
491}
492EXPORT_SYMBOL(omap_set_gpio_debounce);
493
494void omap_set_gpio_debounce_time(int gpio, int enc_time)
495{
496 struct gpio_bank *bank;
497 void __iomem *reg;
498
499 if (cpu_class_is_omap1())
500 return;
501
502 bank = get_gpio_bank(gpio);
503 reg = bank->base;
504
505 enc_time &= 0xff;
506 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
507 __raw_writel(enc_time, reg);
508}
509EXPORT_SYMBOL(omap_set_gpio_debounce_time);
510
5492fb1a 511#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
5eb3bb9c
KH		 512static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
513 int trigger)
5e1c5ff4 514{
3ac4fa99 515 void __iomem *base = bank->base;
92105bb7
TL		 516 u32 gpio_bit = 1 << gpio;
517
518 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
6e60e79a 519 trigger & __IRQT_LOWLVL);
92105bb7 520 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
6e60e79a 521 trigger & __IRQT_HIGHLVL);
92105bb7 522 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
6e60e79a 523 trigger & __IRQT_RISEDGE);
92105bb7 524 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
6e60e79a 525 trigger & __IRQT_FALEDGE);
5eb3bb9c 526
3ac4fa99
JY		 527 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
528 if (trigger != 0)
5eb3bb9c
KH		 529 __raw_writel(1 << gpio, bank->base
530 + OMAP24XX_GPIO_SETWKUENA);
3ac4fa99 531 else
5eb3bb9c
KH		 532 __raw_writel(1 << gpio, bank->base
533 + OMAP24XX_GPIO_CLEARWKUENA);
3ac4fa99
JY		 534 } else {
535 if (trigger != 0)
536 bank->enabled_non_wakeup_gpios |= gpio_bit;
537 else
538 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
539 }
5eb3bb9c
KH		 540
541 /*
542 * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only
543 * level triggering requested.
544 */
92105bb7 545}
3ac4fa99 546#endif
92105bb7
TL		 547
548static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
549{
550 void __iomem *reg = bank->base;
551 u32 l = 0;
5e1c5ff4
TL		 552
553 switch (bank->method) {
e5c56ed3 554#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 555 case METHOD_MPUIO:
556 reg += OMAP_MPUIO_GPIO_INT_EDGE;
557 l = __raw_readl(reg);
6e60e79a 558 if (trigger & __IRQT_RISEDGE)
5e1c5ff4 559 l |= 1 << gpio;
6e60e79a 560 else if (trigger & __IRQT_FALEDGE)
5e1c5ff4 561 l &= ~(1 << gpio);
92105bb7
TL		 562 else
563 goto bad;
5e1c5ff4 564 break;
e5c56ed3
DB		 565#endif
566#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 567 case METHOD_GPIO_1510:
568 reg += OMAP1510_GPIO_INT_CONTROL;
569 l = __raw_readl(reg);
6e60e79a 570 if (trigger & __IRQT_RISEDGE)
5e1c5ff4 571 l |= 1 << gpio;
6e60e79a 572 else if (trigger & __IRQT_FALEDGE)
5e1c5ff4 573 l &= ~(1 << gpio);
92105bb7
TL		 574 else
575 goto bad;
5e1c5ff4 576 break;
e5c56ed3 577#endif
3ac4fa99 578#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 579 case METHOD_GPIO_1610:
5e1c5ff4
TL		 580 if (gpio & 0x08)
581 reg += OMAP1610_GPIO_EDGE_CTRL2;
582 else
583 reg += OMAP1610_GPIO_EDGE_CTRL1;
584 gpio &= 0x07;
585 l = __raw_readl(reg);
586 l &= ~(3 << (gpio << 1));
6e60e79a
TL		 587 if (trigger & __IRQT_RISEDGE)
588 l |= 2 << (gpio << 1);
589 if (trigger & __IRQT_FALEDGE)
590 l |= 1 << (gpio << 1);
3ac4fa99
JY		 591 if (trigger)
592 /* Enable wake-up during idle for dynamic tick */
593 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
594 else
595 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 596 break;
3ac4fa99
JY		 597#endif
598#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 599 case METHOD_GPIO_730:
600 reg += OMAP730_GPIO_INT_CONTROL;
601 l = __raw_readl(reg);
6e60e79a 602 if (trigger & __IRQT_RISEDGE)
5e1c5ff4 603 l |= 1 << gpio;
6e60e79a 604 else if (trigger & __IRQT_FALEDGE)
5e1c5ff4 605 l &= ~(1 << gpio);
92105bb7
TL		 606 else
607 goto bad;
608 break;
3ac4fa99 609#endif
5492fb1a 610#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 611 case METHOD_GPIO_24XX:
3ac4fa99 612 set_24xx_gpio_triggering(bank, gpio, trigger);
5e1c5ff4 613 break;
3ac4fa99 614#endif
5e1c5ff4 615 default:
92105bb7 616 goto bad;
5e1c5ff4 617 }
92105bb7
TL		 618 __raw_writel(l, reg);
619 return 0;
620bad:
621 return -EINVAL;
5e1c5ff4
TL		 622}
623
92105bb7 624static int gpio_irq_type(unsigned irq, unsigned type)
5e1c5ff4
TL		 625{
626 struct gpio_bank *bank;
92105bb7
TL		 627 unsigned gpio;
628 int retval;
a6472533 629 unsigned long flags;
92105bb7 630
5492fb1a 631 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
92105bb7
TL		 632 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
633 else
634 gpio = irq - IH_GPIO_BASE;
5e1c5ff4
TL		 635
636 if (check_gpio(gpio) < 0)
92105bb7
TL		 637 return -EINVAL;
638
e5c56ed3 639 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 640 return -EINVAL;
e5c56ed3
DB		 641
642 /* OMAP1 allows only only edge triggering */
5492fb1a 643 if (!cpu_class_is_omap2()
e5c56ed3 644 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 645 return -EINVAL;
646
58781016 647 bank = get_irq_chip_data(irq);
a6472533 648 spin_lock_irqsave(&bank->lock, flags);
92105bb7 649 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
b9772a22
DB		 650 if (retval == 0) {
651 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
652 irq_desc[irq].status |= type;
653 }
a6472533 654 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 655 return retval;
5e1c5ff4
TL		 656}
657
658static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
659{
92105bb7 660 void __iomem *reg = bank->base;
5e1c5ff4
TL		 661
662 switch (bank->method) {
e5c56ed3 663#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 664 case METHOD_MPUIO:
665 /* MPUIO irqstatus is reset by reading the status register,
666 * so do nothing here */
667 return;
e5c56ed3
DB		 668#endif
669#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 670 case METHOD_GPIO_1510:
671 reg += OMAP1510_GPIO_INT_STATUS;
672 break;
e5c56ed3
DB		 673#endif
674#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 675 case METHOD_GPIO_1610:
676 reg += OMAP1610_GPIO_IRQSTATUS1;
677 break;
e5c56ed3
DB		 678#endif
679#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 680 case METHOD_GPIO_730:
681 reg += OMAP730_GPIO_INT_STATUS;
682 break;
e5c56ed3 683#endif
5492fb1a 684#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 685 case METHOD_GPIO_24XX:
686 reg += OMAP24XX_GPIO_IRQSTATUS1;
687 break;
e5c56ed3 688#endif
5e1c5ff4 689 default:
e5c56ed3 690 WARN_ON(1);
5e1c5ff4
TL		 691 return;
692 }
693 __raw_writel(gpio_mask, reg);
bee7930f
HD		 694
695 /* Workaround for clearing DSP GPIO interrupts to allow retention */
5492fb1a
SMK		 696#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
697 if (cpu_is_omap24xx() || cpu_is_omap34xx())
bee7930f 698 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
5492fb1a 699#endif
5e1c5ff4
TL		 700}
701
702static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
703{
704 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
705}
706
ea6dedd7
ID		 707static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
708{
709 void __iomem *reg = bank->base;
99c47707
ID		 710 int inv = 0;
711 u32 l;
712 u32 mask;
ea6dedd7
ID		 713
714 switch (bank->method) {
e5c56ed3 715#ifdef CONFIG_ARCH_OMAP1
ea6dedd7
ID		 716 case METHOD_MPUIO:
717 reg += OMAP_MPUIO_GPIO_MASKIT;
99c47707
ID		 718 mask = 0xffff;
719 inv = 1;
ea6dedd7 720 break;
e5c56ed3
DB		 721#endif
722#ifdef CONFIG_ARCH_OMAP15XX
ea6dedd7
ID		 723 case METHOD_GPIO_1510:
724 reg += OMAP1510_GPIO_INT_MASK;
99c47707
ID		 725 mask = 0xffff;
726 inv = 1;
ea6dedd7 727 break;
e5c56ed3
DB		 728#endif
729#ifdef CONFIG_ARCH_OMAP16XX
ea6dedd7
ID		 730 case METHOD_GPIO_1610:
731 reg += OMAP1610_GPIO_IRQENABLE1;
99c47707 732 mask = 0xffff;
ea6dedd7 733 break;
e5c56ed3
DB		 734#endif
735#ifdef CONFIG_ARCH_OMAP730
ea6dedd7
ID		 736 case METHOD_GPIO_730:
737 reg += OMAP730_GPIO_INT_MASK;
99c47707
ID		 738 mask = 0xffffffff;
739 inv = 1;
ea6dedd7 740 break;
e5c56ed3 741#endif
5492fb1a 742#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
ea6dedd7
ID		 743 case METHOD_GPIO_24XX:
744 reg += OMAP24XX_GPIO_IRQENABLE1;
99c47707 745 mask = 0xffffffff;
ea6dedd7 746 break;
e5c56ed3 747#endif
ea6dedd7 748 default:
e5c56ed3 749 WARN_ON(1);
ea6dedd7
ID		 750 return 0;
751 }
752
99c47707
ID		 753 l = __raw_readl(reg);
754 if (inv)
755 l = ~l;
756 l &= mask;
757 return l;
ea6dedd7
ID		 758}
759
5e1c5ff4
TL		 760static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
761{
92105bb7 762 void __iomem *reg = bank->base;
5e1c5ff4
TL		 763 u32 l;
764
765 switch (bank->method) {
e5c56ed3 766#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 767 case METHOD_MPUIO:
768 reg += OMAP_MPUIO_GPIO_MASKIT;
769 l = __raw_readl(reg);
770 if (enable)
771 l &= ~(gpio_mask);
772 else
773 l |= gpio_mask;
774 break;
e5c56ed3
DB		 775#endif
776#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 777 case METHOD_GPIO_1510:
778 reg += OMAP1510_GPIO_INT_MASK;
779 l = __raw_readl(reg);
780 if (enable)
781 l &= ~(gpio_mask);
782 else
783 l |= gpio_mask;
784 break;
e5c56ed3
DB		 785#endif
786#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 787 case METHOD_GPIO_1610:
788 if (enable)
789 reg += OMAP1610_GPIO_SET_IRQENABLE1;
790 else
791 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
792 l = gpio_mask;
793 break;
e5c56ed3
DB		 794#endif
795#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 796 case METHOD_GPIO_730:
797 reg += OMAP730_GPIO_INT_MASK;
798 l = __raw_readl(reg);
799 if (enable)
800 l &= ~(gpio_mask);
801 else
802 l |= gpio_mask;
803 break;
e5c56ed3 804#endif
5492fb1a 805#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 806 case METHOD_GPIO_24XX:
807 if (enable)
808 reg += OMAP24XX_GPIO_SETIRQENABLE1;
809 else
810 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
811 l = gpio_mask;
812 break;
e5c56ed3 813#endif
5e1c5ff4 814 default:
e5c56ed3 815 WARN_ON(1);
5e1c5ff4
TL		 816 return;
817 }
818 __raw_writel(l, reg);
819}
820
821static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
822{
823 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
824}
825
92105bb7
TL		 826/*
827 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
828 * 1510 does not seem to have a wake-up register. If JTAG is connected
829 * to the target, system will wake up always on GPIO events. While
830 * system is running all registered GPIO interrupts need to have wake-up
831 * enabled. When system is suspended, only selected GPIO interrupts need
832 * to have wake-up enabled.
833 */
834static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
835{
a6472533
DB		 836 unsigned long flags;
837
92105bb7 838 switch (bank->method) {
3ac4fa99 839#ifdef CONFIG_ARCH_OMAP16XX
11a78b79 840 case METHOD_MPUIO:
92105bb7 841 case METHOD_GPIO_1610:
a6472533 842 spin_lock_irqsave(&bank->lock, flags);
11a78b79 843 if (enable) {
92105bb7 844 bank->suspend_wakeup |= (1 << gpio);
11a78b79
DB		 845 enable_irq_wake(bank->irq);
846 } else {
847 disable_irq_wake(bank->irq);
92105bb7 848 bank->suspend_wakeup &= ~(1 << gpio);
11a78b79 849 }
a6472533 850 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 851 return 0;
3ac4fa99 852#endif
5492fb1a 853#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99 854 case METHOD_GPIO_24XX:
11a78b79
DB		 855 if (bank->non_wakeup_gpios & (1 << gpio)) {
856 printk(KERN_ERR "Unable to modify wakeup on "
857 "non-wakeup GPIO%d\n",
858 (bank - gpio_bank) * 32 + gpio);
859 return -EINVAL;
860 }
a6472533 861 spin_lock_irqsave(&bank->lock, flags);
3ac4fa99 862 if (enable) {
3ac4fa99 863 bank->suspend_wakeup |= (1 << gpio);
11a78b79
DB		 864 enable_irq_wake(bank->irq);
865 } else {
866 disable_irq_wake(bank->irq);
3ac4fa99 867 bank->suspend_wakeup &= ~(1 << gpio);
11a78b79 868 }
a6472533 869 spin_unlock_irqrestore(&bank->lock, flags);
3ac4fa99
JY		 870 return 0;
871#endif
92105bb7
TL		 872 default:
873 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
874 bank->method);
875 return -EINVAL;
876 }
877}
878
4196dd6b
TL		 879static void _reset_gpio(struct gpio_bank *bank, int gpio)
880{
881 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
882 _set_gpio_irqenable(bank, gpio, 0);
883 _clear_gpio_irqstatus(bank, gpio);
884 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
885}
886
92105bb7
TL		 887/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
888static int gpio_wake_enable(unsigned int irq, unsigned int enable)
889{
890 unsigned int gpio = irq - IH_GPIO_BASE;
891 struct gpio_bank *bank;
892 int retval;
893
894 if (check_gpio(gpio) < 0)
895 return -ENODEV;
58781016 896 bank = get_irq_chip_data(irq);
92105bb7 897 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
92105bb7
TL		 898
899 return retval;
900}
901
5e1c5ff4
TL		 902int omap_request_gpio(int gpio)
903{
904 struct gpio_bank *bank;
a6472533 905 unsigned long flags;
5e1c5ff4
TL		 906
907 if (check_gpio(gpio) < 0)
908 return -EINVAL;
909
910 bank = get_gpio_bank(gpio);
a6472533 911 spin_lock_irqsave(&bank->lock, flags);
5e1c5ff4
TL		 912 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
913 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
914 dump_stack();
a6472533 915 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 916 return -1;
917 }
918 bank->reserved_map |= (1 << get_gpio_index(gpio));
92105bb7 919
4196dd6b
TL		 920 /* Set trigger to none. You need to enable the desired trigger with
921 * request_irq() or set_irq_type().
922 */
92105bb7
TL		 923 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
924
1a8bfa1e 925#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 926 if (bank->method == METHOD_GPIO_1510) {
92105bb7 927 void __iomem *reg;
5e1c5ff4 928
92105bb7 929 /* Claim the pin for MPU */
5e1c5ff4
TL		 930 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
931 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
932 }
933#endif
a6472533 934 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 935
936 return 0;
937}
938
939void omap_free_gpio(int gpio)
940{
941 struct gpio_bank *bank;
a6472533 942 unsigned long flags;
5e1c5ff4
TL		 943
944 if (check_gpio(gpio) < 0)
945 return;
946 bank = get_gpio_bank(gpio);
a6472533 947 spin_lock_irqsave(&bank->lock, flags);
5e1c5ff4
TL		 948 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
949 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
950 dump_stack();
a6472533 951 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 952 return;
953 }
92105bb7
TL		 954#ifdef CONFIG_ARCH_OMAP16XX
955 if (bank->method == METHOD_GPIO_1610) {
956 /* Disable wake-up during idle for dynamic tick */
957 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
958 __raw_writel(1 << get_gpio_index(gpio), reg);
959 }
960#endif
5492fb1a 961#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 962 if (bank->method == METHOD_GPIO_24XX) {
963 /* Disable wake-up during idle for dynamic tick */
964 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
965 __raw_writel(1 << get_gpio_index(gpio), reg);
966 }
967#endif
5e1c5ff4 968 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
4196dd6b 969 _reset_gpio(bank, gpio);
a6472533 970 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 971}
972
973/*
974 * We need to unmask the GPIO bank interrupt as soon as possible to
975 * avoid missing GPIO interrupts for other lines in the bank.
976 * Then we need to mask-read-clear-unmask the triggered GPIO lines
977 * in the bank to avoid missing nested interrupts for a GPIO line.
978 * If we wait to unmask individual GPIO lines in the bank after the
979 * line's interrupt handler has been run, we may miss some nested
980 * interrupts.
981 */
10dd5ce2 982static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 983{
92105bb7 984 void __iomem *isr_reg = NULL;
5e1c5ff4
TL		 985 u32 isr;
986 unsigned int gpio_irq;
987 struct gpio_bank *bank;
ea6dedd7
ID		 988 u32 retrigger = 0;
989 int unmasked = 0;
5e1c5ff4
TL		 990
991 desc->chip->ack(irq);
992
418ca1f0 993 bank = get_irq_data(irq);
e5c56ed3 994#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 995 if (bank->method == METHOD_MPUIO)
996 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
e5c56ed3 997#endif
1a8bfa1e 998#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 999 if (bank->method == METHOD_GPIO_1510)
1000 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1001#endif
1002#if defined(CONFIG_ARCH_OMAP16XX)
1003 if (bank->method == METHOD_GPIO_1610)
1004 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1005#endif
1006#ifdef CONFIG_ARCH_OMAP730
1007 if (bank->method == METHOD_GPIO_730)
1008 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1009#endif
5492fb1a 1010#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 1011 if (bank->method == METHOD_GPIO_24XX)
1012 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1013#endif
92105bb7 1014 while(1) {
6e60e79a 1015 u32 isr_saved, level_mask = 0;
ea6dedd7 1016 u32 enabled;
6e60e79a 1017
ea6dedd7
ID		 1018 enabled = _get_gpio_irqbank_mask(bank);
1019 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 1020
1021 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1022 isr &= 0x0000ffff;
1023
5492fb1a 1024 if (cpu_class_is_omap2()) {
6e60e79a
TL		 1025 level_mask =
1026 __raw_readl(bank->base +
1027 OMAP24XX_GPIO_LEVELDETECT0) |
1028 __raw_readl(bank->base +
1029 OMAP24XX_GPIO_LEVELDETECT1);
ea6dedd7
ID		 1030 level_mask &= enabled;
1031 }
6e60e79a
TL		 1032
1033 /* clear edge sensitive interrupts before handler(s) are
1034 called so that we don't miss any interrupt occurred while
1035 executing them */
1036 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1037 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1038 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1039
1040 /* if there is only edge sensitive GPIO pin interrupts
1041 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 1042 if (!level_mask && !unmasked) {
1043 unmasked = 1;
6e60e79a 1044 desc->chip->unmask(irq);
ea6dedd7 1045 }
92105bb7 1046
ea6dedd7
ID		 1047 isr |= retrigger;
1048 retrigger = 0;
92105bb7
TL		 1049 if (!isr)
1050 break;
1051
1052 gpio_irq = bank->virtual_irq_start;
1053 for (; isr != 0; isr >>= 1, gpio_irq++) {
10dd5ce2 1054 struct irq_desc *d;
ea6dedd7 1055 int irq_mask;
92105bb7
TL		 1056 if (!(isr & 1))
1057 continue;
1058 d = irq_desc + gpio_irq;
ea6dedd7
ID		 1059 /* Don't run the handler if it's already running
1060 * or was disabled lazely.
1061 */
29454dde
TG		 1062 if (unlikely((d->depth ||
1063 (d->status & IRQ_INPROGRESS)))) {
ea6dedd7
ID		 1064 irq_mask = 1 <<
1065 (gpio_irq - bank->virtual_irq_start);
1066 /* The unmasking will be done by
1067 * enable_irq in case it is disabled or
1068 * after returning from the handler if
1069 * it's already running.
1070 */
1071 _enable_gpio_irqbank(bank, irq_mask, 0);
29454dde 1072 if (!d->depth) {
ea6dedd7
ID		 1073 /* Level triggered interrupts
1074 * won't ever be reentered
1075 */
1076 BUG_ON(level_mask & irq_mask);
29454dde 1077 d->status |= IRQ_PENDING;
ea6dedd7
ID		 1078 }
1079 continue;
1080 }
29454dde 1081
0cd61b68 1082 desc_handle_irq(gpio_irq, d);
29454dde
TG		 1083
1084 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
ea6dedd7
ID		 1085 irq_mask = 1 <<
1086 (gpio_irq - bank->virtual_irq_start);
29454dde 1087 d->status &= ~IRQ_PENDING;
ea6dedd7
ID		 1088 _enable_gpio_irqbank(bank, irq_mask, 1);
1089 retrigger |= irq_mask;
1090 }
92105bb7 1091 }
6e60e79a 1092
5492fb1a 1093 if (cpu_class_is_omap2()) {
6e60e79a
TL		 1094 /* clear level sensitive interrupts after handler(s) */
1095 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
1096 _clear_gpio_irqbank(bank, isr_saved & level_mask);
1097 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
1098 }
1099
1a8bfa1e 1100 }
ea6dedd7
ID		 1101 /* if bank has any level sensitive GPIO pin interrupt
1102 configured, we must unmask the bank interrupt only after
1103 handler(s) are executed in order to avoid spurious bank
1104 interrupt */
1105 if (!unmasked)
1106 desc->chip->unmask(irq);
1107
5e1c5ff4
TL		 1108}
1109
4196dd6b
TL		 1110static void gpio_irq_shutdown(unsigned int irq)
1111{
1112 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1113 struct gpio_bank *bank = get_irq_chip_data(irq);
4196dd6b
TL		 1114
1115 _reset_gpio(bank, gpio);
1116}
1117
5e1c5ff4
TL		 1118static void gpio_ack_irq(unsigned int irq)
1119{
1120 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1121 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1122
1123 _clear_gpio_irqstatus(bank, gpio);
1124}
1125
1126static void gpio_mask_irq(unsigned int irq)
1127{
1128 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1129 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1130
1131 _set_gpio_irqenable(bank, gpio, 0);
1132}
1133
1134static void gpio_unmask_irq(unsigned int irq)
1135{
1136 unsigned int gpio = irq - IH_GPIO_BASE;
92105bb7 1137 unsigned int gpio_idx = get_gpio_index(gpio);
58781016 1138 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4 1139
92105bb7 1140 _set_gpio_irqenable(bank, gpio_idx, 1);
5e1c5ff4
TL		 1141}
1142
e5c56ed3
DB		 1143static struct irq_chip gpio_irq_chip = {
1144 .name = "GPIO",
1145 .shutdown = gpio_irq_shutdown,
1146 .ack = gpio_ack_irq,
1147 .mask = gpio_mask_irq,
1148 .unmask = gpio_unmask_irq,
1149 .set_type = gpio_irq_type,
1150 .set_wake = gpio_wake_enable,
1151};
1152
1153/*---------------------------------------------------------------------*/
1154
1155#ifdef CONFIG_ARCH_OMAP1
1156
1157/* MPUIO uses the always-on 32k clock */
1158
5e1c5ff4
TL		 1159static void mpuio_ack_irq(unsigned int irq)
1160{
1161 /* The ISR is reset automatically, so do nothing here. */
1162}
1163
1164static void mpuio_mask_irq(unsigned int irq)
1165{
1166 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1167 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1168
1169 _set_gpio_irqenable(bank, gpio, 0);
1170}
1171
1172static void mpuio_unmask_irq(unsigned int irq)
1173{
1174 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1175 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1176
1177 _set_gpio_irqenable(bank, gpio, 1);
1178}
1179
e5c56ed3
DB		 1180static struct irq_chip mpuio_irq_chip = {
1181 .name = "MPUIO",
1182 .ack = mpuio_ack_irq,
1183 .mask = mpuio_mask_irq,
1184 .unmask = mpuio_unmask_irq,
92105bb7 1185 .set_type = gpio_irq_type,
11a78b79
DB		 1186#ifdef CONFIG_ARCH_OMAP16XX
1187 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1188 .set_wake = gpio_wake_enable,
1189#endif
5e1c5ff4
TL		 1190};
1191
e5c56ed3
DB		 1192
1193#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1194
11a78b79
DB		 1195
1196#ifdef CONFIG_ARCH_OMAP16XX
1197
1198#include <linux/platform_device.h>
1199
1200static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1201{
1202 struct gpio_bank *bank = platform_get_drvdata(pdev);
1203 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1204 unsigned long flags;
11a78b79 1205
a6472533 1206 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 1207 bank->saved_wakeup = __raw_readl(mask_reg);
1208 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 1209 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1210
1211 return 0;
1212}
1213
1214static int omap_mpuio_resume_early(struct platform_device *pdev)
1215{
1216 struct gpio_bank *bank = platform_get_drvdata(pdev);
1217 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1218 unsigned long flags;
11a78b79 1219
a6472533 1220 spin_lock_irqsave(&bank->lock, flags);
11a78b79 1221 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 1222 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1223
1224 return 0;
1225}
1226
1227/* use platform_driver for this, now that there's no longer any
1228 * point to sys_device (other than not disturbing old code).
1229 */
1230static struct platform_driver omap_mpuio_driver = {
1231 .suspend_late = omap_mpuio_suspend_late,
1232 .resume_early = omap_mpuio_resume_early,
1233 .driver = {
1234 .name = "mpuio",
1235 },
1236};
1237
1238static struct platform_device omap_mpuio_device = {
1239 .name = "mpuio",
1240 .id = -1,
1241 .dev = {
1242 .driver = &omap_mpuio_driver.driver,
1243 }
1244 /* could list the /proc/iomem resources */
1245};
1246
1247static inline void mpuio_init(void)
1248{
fcf126d8
DB		 1249 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1250
11a78b79
DB		 1251 if (platform_driver_register(&omap_mpuio_driver) == 0)
1252 (void) platform_device_register(&omap_mpuio_device);
1253}
1254
1255#else
1256static inline void mpuio_init(void) {}
1257#endif /* 16xx */
1258
e5c56ed3
DB		 1259#else
1260
1261extern struct irq_chip mpuio_irq_chip;
1262
1263#define bank_is_mpuio(bank) 0
11a78b79 1264static inline void mpuio_init(void) {}
e5c56ed3
DB		 1265
1266#endif
1267
1268/*---------------------------------------------------------------------*/
5e1c5ff4 1269
1a8bfa1e 1270static int initialized;
5492fb1a 1271#if !defined(CONFIG_ARCH_OMAP3)
1a8bfa1e 1272static struct clk * gpio_ick;
5492fb1a
SMK		 1273#endif
1274
1275#if defined(CONFIG_ARCH_OMAP2)
1a8bfa1e 1276static struct clk * gpio_fck;
5492fb1a 1277#endif
5e1c5ff4 1278
5492fb1a 1279#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1280static struct clk * gpio5_ick;
1281static struct clk * gpio5_fck;
1282#endif
1283
5492fb1a
SMK		 1284#if defined(CONFIG_ARCH_OMAP3)
1285static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
1286static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1287#endif
1288
8ba55c5c
DB		 1289/* This lock class tells lockdep that GPIO irqs are in a different
1290 * category than their parents, so it won't report false recursion.
1291 */
1292static struct lock_class_key gpio_lock_class;
1293
5e1c5ff4
TL		 1294static int __init _omap_gpio_init(void)
1295{
1296 int i;
1297 struct gpio_bank *bank;
5492fb1a
SMK		 1298#if defined(CONFIG_ARCH_OMAP3)
1299 char clk_name[11];
1300#endif
5e1c5ff4
TL		 1301
1302 initialized = 1;
1303
5492fb1a 1304#if defined(CONFIG_ARCH_OMAP1)
6e60e79a 1305 if (cpu_is_omap15xx()) {
1a8bfa1e
TL		 1306 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1307 if (IS_ERR(gpio_ick))
92105bb7
TL		 1308 printk("Could not get arm_gpio_ck\n");
1309 else
30ff720b 1310 clk_enable(gpio_ick);
1a8bfa1e 1311 }
5492fb1a
SMK		 1312#endif
1313#if defined(CONFIG_ARCH_OMAP2)
1314 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 1315 gpio_ick = clk_get(NULL, "gpios_ick");
1316 if (IS_ERR(gpio_ick))
1317 printk("Could not get gpios_ick\n");
1318 else
30ff720b 1319 clk_enable(gpio_ick);
1a8bfa1e 1320 gpio_fck = clk_get(NULL, "gpios_fck");
1630b52d 1321 if (IS_ERR(gpio_fck))
1a8bfa1e
TL		 1322 printk("Could not get gpios_fck\n");
1323 else
30ff720b 1324 clk_enable(gpio_fck);
56a25641
SMK		 1325
1326 /*
5492fb1a 1327 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
56a25641 1328 */
5492fb1a 1329#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1330 if (cpu_is_omap2430()) {
1331 gpio5_ick = clk_get(NULL, "gpio5_ick");
1332 if (IS_ERR(gpio5_ick))
1333 printk("Could not get gpio5_ick\n");
1334 else
1335 clk_enable(gpio5_ick);
1336 gpio5_fck = clk_get(NULL, "gpio5_fck");
1337 if (IS_ERR(gpio5_fck))
1338 printk("Could not get gpio5_fck\n");
1339 else
1340 clk_enable(gpio5_fck);
1341 }
1342#endif
5492fb1a
SMK		 1343 }
1344#endif
1345
1346#if defined(CONFIG_ARCH_OMAP3)
1347 if (cpu_is_omap34xx()) {
1348 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1349 sprintf(clk_name, "gpio%d_ick", i + 1);
1350 gpio_iclks[i] = clk_get(NULL, clk_name);
1351 if (IS_ERR(gpio_iclks[i]))
1352 printk(KERN_ERR "Could not get %s\n", clk_name);
1353 else
1354 clk_enable(gpio_iclks[i]);
1355 sprintf(clk_name, "gpio%d_fck", i + 1);
1356 gpio_fclks[i] = clk_get(NULL, clk_name);
1357 if (IS_ERR(gpio_fclks[i]))
1358 printk(KERN_ERR "Could not get %s\n", clk_name);
1359 else
1360 clk_enable(gpio_fclks[i]);
1361 }
1362 }
1363#endif
1364
92105bb7 1365
1a8bfa1e 1366#ifdef CONFIG_ARCH_OMAP15XX
6e60e79a 1367 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 1368 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1369 gpio_bank_count = 2;
1370 gpio_bank = gpio_bank_1510;
1371 }
1372#endif
1373#if defined(CONFIG_ARCH_OMAP16XX)
1374 if (cpu_is_omap16xx()) {
92105bb7 1375 u32 rev;
5e1c5ff4
TL		 1376
1377 gpio_bank_count = 5;
1378 gpio_bank = gpio_bank_1610;
1379 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1380 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1381 (rev >> 4) & 0x0f, rev & 0x0f);
1382 }
1383#endif
1384#ifdef CONFIG_ARCH_OMAP730
1385 if (cpu_is_omap730()) {
1386 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1387 gpio_bank_count = 7;
1388 gpio_bank = gpio_bank_730;
1389 }
92105bb7 1390#endif
56a25641 1391
92105bb7 1392#ifdef CONFIG_ARCH_OMAP24XX
56a25641 1393 if (cpu_is_omap242x()) {
92105bb7
TL		 1394 int rev;
1395
1396 gpio_bank_count = 4;
56a25641
SMK		 1397 gpio_bank = gpio_bank_242x;
1398 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1399 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1400 (rev >> 4) & 0x0f, rev & 0x0f);
1401 }
1402 if (cpu_is_omap243x()) {
1403 int rev;
1404
1405 gpio_bank_count = 5;
1406 gpio_bank = gpio_bank_243x;
92105bb7 1407 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
56a25641 1408 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
92105bb7
TL		 1409 (rev >> 4) & 0x0f, rev & 0x0f);
1410 }
5492fb1a
SMK		 1411#endif
1412#ifdef CONFIG_ARCH_OMAP34XX
1413 if (cpu_is_omap34xx()) {
1414 int rev;
1415
1416 gpio_bank_count = OMAP34XX_NR_GPIOS;
1417 gpio_bank = gpio_bank_34xx;
1418 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1419 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1420 (rev >> 4) & 0x0f, rev & 0x0f);
1421 }
5e1c5ff4
TL		 1422#endif
1423 for (i = 0; i < gpio_bank_count; i++) {
1424 int j, gpio_count = 16;
1425
1426 bank = &gpio_bank[i];
1427 bank->reserved_map = 0;
1428 bank->base = IO_ADDRESS(bank->base);
1429 spin_lock_init(&bank->lock);
e5c56ed3 1430 if (bank_is_mpuio(bank))
5e1c5ff4 1431 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
d11ac979 1432 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
5e1c5ff4
TL		 1433 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1434 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1435 }
d11ac979 1436 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
5e1c5ff4
TL		 1437 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1438 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
92105bb7 1439 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
5e1c5ff4 1440 }
d11ac979 1441 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
5e1c5ff4
TL		 1442 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1443 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1444
1445 gpio_count = 32; /* 730 has 32-bit GPIOs */
1446 }
d11ac979 1447
5492fb1a 1448#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 1449 if (bank->method == METHOD_GPIO_24XX) {
3ac4fa99
JY		 1450 static const u32 non_wakeup_gpios[] = {
1451 0xe203ffc0, 0x08700040
1452 };
1453
92105bb7
TL		 1454 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1455 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
14f1c3bf
JY		 1456 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1457
1458 /* Initialize interface clock ungated, module enabled */
1459 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
3ac4fa99
JY		 1460 if (i < ARRAY_SIZE(non_wakeup_gpios))
1461 bank->non_wakeup_gpios = non_wakeup_gpios[i];
92105bb7
TL		 1462 gpio_count = 32;
1463 }
5e1c5ff4
TL		 1464#endif
1465 for (j = bank->virtual_irq_start;
1466 j < bank->virtual_irq_start + gpio_count; j++) {
8ba55c5c 1467 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
58781016 1468 set_irq_chip_data(j, bank);
e5c56ed3 1469 if (bank_is_mpuio(bank))
5e1c5ff4
TL		 1470 set_irq_chip(j, &mpuio_irq_chip);
1471 else
1472 set_irq_chip(j, &gpio_irq_chip);
10dd5ce2 1473 set_irq_handler(j, handle_simple_irq);
5e1c5ff4
TL		 1474 set_irq_flags(j, IRQF_VALID);
1475 }
1476 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1477 set_irq_data(bank->irq, bank);
1478 }
1479
1480 /* Enable system clock for GPIO module.
1481 * The CAM_CLK_CTRL *is* really the right place. */
92105bb7 1482 if (cpu_is_omap16xx())
5e1c5ff4
TL		 1483 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1484
14f1c3bf
JY		 1485 /* Enable autoidle for the OCP interface */
1486 if (cpu_is_omap24xx())
1487 omap_writel(1 << 0, 0x48019010);
5492fb1a
SMK		 1488 if (cpu_is_omap34xx())
1489 omap_writel(1 << 0, 0x48306814);
d11ac979 1490
5e1c5ff4
TL		 1491 return 0;
1492}
1493
5492fb1a 1494#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 1495static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1496{
1497 int i;
1498
5492fb1a 1499 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1500 return 0;
1501
1502 for (i = 0; i < gpio_bank_count; i++) {
1503 struct gpio_bank *bank = &gpio_bank[i];
1504 void __iomem *wake_status;
1505 void __iomem *wake_clear;
1506 void __iomem *wake_set;
a6472533 1507 unsigned long flags;
92105bb7
TL		 1508
1509 switch (bank->method) {
e5c56ed3 1510#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1511 case METHOD_GPIO_1610:
1512 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1513 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1514 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1515 break;
e5c56ed3 1516#endif
5492fb1a 1517#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 1518 case METHOD_GPIO_24XX:
1519 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1520 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1521 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1522 break;
e5c56ed3 1523#endif
92105bb7
TL		 1524 default:
1525 continue;
1526 }
1527
a6472533 1528 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1529 bank->saved_wakeup = __raw_readl(wake_status);
1530 __raw_writel(0xffffffff, wake_clear);
1531 __raw_writel(bank->suspend_wakeup, wake_set);
a6472533 1532 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1533 }
1534
1535 return 0;
1536}
1537
1538static int omap_gpio_resume(struct sys_device *dev)
1539{
1540 int i;
1541
1542 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1543 return 0;
1544
1545 for (i = 0; i < gpio_bank_count; i++) {
1546 struct gpio_bank *bank = &gpio_bank[i];
1547 void __iomem *wake_clear;
1548 void __iomem *wake_set;
a6472533 1549 unsigned long flags;
92105bb7
TL		 1550
1551 switch (bank->method) {
e5c56ed3 1552#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1553 case METHOD_GPIO_1610:
1554 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1555 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1556 break;
e5c56ed3 1557#endif
5492fb1a 1558#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 1559 case METHOD_GPIO_24XX:
0d9356cb
TL		 1560 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1561 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 1562 break;
e5c56ed3 1563#endif
92105bb7
TL		 1564 default:
1565 continue;
1566 }
1567
a6472533 1568 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1569 __raw_writel(0xffffffff, wake_clear);
1570 __raw_writel(bank->saved_wakeup, wake_set);
a6472533 1571 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1572 }
1573
1574 return 0;
1575}
1576
1577static struct sysdev_class omap_gpio_sysclass = {
af5ca3f4 1578 .name = "gpio",
92105bb7
TL		 1579 .suspend = omap_gpio_suspend,
1580 .resume = omap_gpio_resume,
1581};
1582
1583static struct sys_device omap_gpio_device = {
1584 .id = 0,
1585 .cls = &omap_gpio_sysclass,
1586};
3ac4fa99
JY		 1587
1588#endif
1589
5492fb1a 1590#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1591
1592static int workaround_enabled;
1593
1594void omap2_gpio_prepare_for_retention(void)
1595{
1596 int i, c = 0;
1597
1598 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1599 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1600 for (i = 0; i < gpio_bank_count; i++) {
1601 struct gpio_bank *bank = &gpio_bank[i];
1602 u32 l1, l2;
1603
1604 if (!(bank->enabled_non_wakeup_gpios))
1605 continue;
5492fb1a 1606#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1607 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1608 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1609 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1610#endif
3ac4fa99
JY		 1611 bank->saved_fallingdetect = l1;
1612 bank->saved_risingdetect = l2;
1613 l1 &= ~bank->enabled_non_wakeup_gpios;
1614 l2 &= ~bank->enabled_non_wakeup_gpios;
5492fb1a 1615#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1616 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1617 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1618#endif
3ac4fa99
JY		 1619 c++;
1620 }
1621 if (!c) {
1622 workaround_enabled = 0;
1623 return;
1624 }
1625 workaround_enabled = 1;
1626}
1627
1628void omap2_gpio_resume_after_retention(void)
1629{
1630 int i;
1631
1632 if (!workaround_enabled)
1633 return;
1634 for (i = 0; i < gpio_bank_count; i++) {
1635 struct gpio_bank *bank = &gpio_bank[i];
1636 u32 l;
1637
1638 if (!(bank->enabled_non_wakeup_gpios))
1639 continue;
5492fb1a 1640#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1641 __raw_writel(bank->saved_fallingdetect,
1642 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1643 __raw_writel(bank->saved_risingdetect,
1644 bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1645#endif
3ac4fa99
JY		 1646 /* Check if any of the non-wakeup interrupt GPIOs have changed
1647 * state. If so, generate an IRQ by software. This is
1648 * horribly racy, but it's the best we can do to work around
1649 * this silicon bug. */
5492fb1a 1650#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99 1651 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
5492fb1a 1652#endif
3ac4fa99
JY		 1653 l ^= bank->saved_datain;
1654 l &= bank->non_wakeup_gpios;
1655 if (l) {
1656 u32 old0, old1;
5492fb1a 1657#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1658 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1659 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1660 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1661 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1662 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1663 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
5492fb1a 1664#endif
3ac4fa99
JY		 1665 }
1666 }
1667
1668}
1669
92105bb7
TL		 1670#endif
1671
5e1c5ff4
TL		 1672/*
1673 * This may get called early from board specific init
1a8bfa1e 1674 * for boards that have interrupts routed via FPGA.
5e1c5ff4 1675 */
277d58ef 1676int __init omap_gpio_init(void)
5e1c5ff4
TL		 1677{
1678 if (!initialized)
1679 return _omap_gpio_init();
1680 else
1681 return 0;
1682}
1683
92105bb7
TL		 1684static int __init omap_gpio_sysinit(void)
1685{
1686 int ret = 0;
1687
1688 if (!initialized)
1689 ret = _omap_gpio_init();
1690
11a78b79
DB		 1691 mpuio_init();
1692
5492fb1a
SMK		 1693#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1694 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
92105bb7
TL		 1695 if (ret == 0) {
1696 ret = sysdev_class_register(&omap_gpio_sysclass);
1697 if (ret == 0)
1698 ret = sysdev_register(&omap_gpio_device);
1699 }
1700 }
1701#endif
1702
1703 return ret;
1704}
1705
5e1c5ff4
TL		 1706EXPORT_SYMBOL(omap_request_gpio);
1707EXPORT_SYMBOL(omap_free_gpio);
1708EXPORT_SYMBOL(omap_set_gpio_direction);
1709EXPORT_SYMBOL(omap_set_gpio_dataout);
1710EXPORT_SYMBOL(omap_get_gpio_datain);
5e1c5ff4 1711
92105bb7 1712arch_initcall(omap_gpio_sysinit);
b9772a22
DB		 1713
1714
1715#ifdef CONFIG_DEBUG_FS
1716
1717#include <linux/debugfs.h>
1718#include <linux/seq_file.h>
1719
1720static int gpio_is_input(struct gpio_bank *bank, int mask)
1721{
1722 void __iomem *reg = bank->base;
1723
1724 switch (bank->method) {
1725 case METHOD_MPUIO:
1726 reg += OMAP_MPUIO_IO_CNTL;
1727 break;
1728 case METHOD_GPIO_1510:
1729 reg += OMAP1510_GPIO_DIR_CONTROL;
1730 break;
1731 case METHOD_GPIO_1610:
1732 reg += OMAP1610_GPIO_DIRECTION;
1733 break;
1734 case METHOD_GPIO_730:
1735 reg += OMAP730_GPIO_DIR_CONTROL;
1736 break;
1737 case METHOD_GPIO_24XX:
1738 reg += OMAP24XX_GPIO_OE;
1739 break;
1740 }
1741 return __raw_readl(reg) & mask;
1742}
1743
1744
1745static int dbg_gpio_show(struct seq_file *s, void *unused)
1746{
1747 unsigned i, j, gpio;
1748
1749 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1750 struct gpio_bank *bank = gpio_bank + i;
1751 unsigned bankwidth = 16;
1752 u32 mask = 1;
1753
e5c56ed3 1754 if (bank_is_mpuio(bank))
b9772a22 1755 gpio = OMAP_MPUIO(0);
5492fb1a 1756 else if (cpu_class_is_omap2() || cpu_is_omap730())
b9772a22
DB		 1757 bankwidth = 32;
1758
1759 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1760 unsigned irq, value, is_in, irqstat;
1761
1762 if (!(bank->reserved_map & mask))
1763 continue;
1764
1765 irq = bank->virtual_irq_start + j;
1766 value = omap_get_gpio_datain(gpio);
1767 is_in = gpio_is_input(bank, mask);
1768
e5c56ed3 1769 if (bank_is_mpuio(bank))
b9772a22
DB		 1770 seq_printf(s, "MPUIO %2d: ", j);
1771 else
1772 seq_printf(s, "GPIO %3d: ", gpio);
1773 seq_printf(s, "%s %s",
1774 is_in ? "in " : "out",
1775 value ? "hi" : "lo");
1776
1777 irqstat = irq_desc[irq].status;
1778 if (is_in && ((bank->suspend_wakeup & mask)
1779 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1780 char *trigger = NULL;
1781
1782 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1783 case IRQ_TYPE_EDGE_FALLING:
1784 trigger = "falling";
1785 break;
1786 case IRQ_TYPE_EDGE_RISING:
1787 trigger = "rising";
1788 break;
1789 case IRQ_TYPE_EDGE_BOTH:
1790 trigger = "bothedge";
1791 break;
1792 case IRQ_TYPE_LEVEL_LOW:
1793 trigger = "low";
1794 break;
1795 case IRQ_TYPE_LEVEL_HIGH:
1796 trigger = "high";
1797 break;
1798 case IRQ_TYPE_NONE:
1799 trigger = "(unspecified)";
1800 break;
1801 }
1802 seq_printf(s, ", irq-%d %s%s",
1803 irq, trigger,
1804 (bank->suspend_wakeup & mask)
1805 ? " wakeup" : "");
1806 }
1807 seq_printf(s, "\n");
1808 }
1809
e5c56ed3 1810 if (bank_is_mpuio(bank)) {
b9772a22
DB		 1811 seq_printf(s, "\n");
1812 gpio = 0;
1813 }
1814 }
1815 return 0;
1816}
1817
1818static int dbg_gpio_open(struct inode *inode, struct file *file)
1819{
e5c56ed3 1820 return single_open(file, dbg_gpio_show, &inode->i_private);
b9772a22
DB		 1821}
1822
1823static const struct file_operations debug_fops = {
1824 .open = dbg_gpio_open,
1825 .read = seq_read,
1826 .llseek = seq_lseek,
1827 .release = single_release,
1828};
1829
1830static int __init omap_gpio_debuginit(void)
1831{
e5c56ed3
DB		 1832 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1833 NULL, NULL, &debug_fops);
b9772a22
DB		 1834 return 0;
1835}
1836late_initcall(omap_gpio_debuginit);
1837#endif
Linux kernel - Deliverables
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