Commit | Line | Data |
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5e1c5ff4 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/gpio.c | |
3 | * | |
4 | * Support functions for OMAP GPIO | |
5 | * | |
92105bb7 | 6 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 7 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 TL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
5e1c5ff4 TL |
14 | #include <linux/init.h> |
15 | #include <linux/module.h> | |
5e1c5ff4 | 16 | #include <linux/interrupt.h> |
92105bb7 TL |
17 | #include <linux/sysdev.h> |
18 | #include <linux/err.h> | |
f8ce2547 | 19 | #include <linux/clk.h> |
fced80c7 | 20 | #include <linux/io.h> |
5e1c5ff4 | 21 | |
a09e64fb | 22 | #include <mach/hardware.h> |
5e1c5ff4 | 23 | #include <asm/irq.h> |
a09e64fb RK |
24 | #include <mach/irqs.h> |
25 | #include <mach/gpio.h> | |
5e1c5ff4 TL |
26 | #include <asm/mach/irq.h> |
27 | ||
5e1c5ff4 TL |
28 | /* |
29 | * OMAP1510 GPIO registers | |
30 | */ | |
7c7095aa | 31 | #define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000) |
5e1c5ff4 TL |
32 | #define OMAP1510_GPIO_DATA_INPUT 0x00 |
33 | #define OMAP1510_GPIO_DATA_OUTPUT 0x04 | |
34 | #define OMAP1510_GPIO_DIR_CONTROL 0x08 | |
35 | #define OMAP1510_GPIO_INT_CONTROL 0x0c | |
36 | #define OMAP1510_GPIO_INT_MASK 0x10 | |
37 | #define OMAP1510_GPIO_INT_STATUS 0x14 | |
38 | #define OMAP1510_GPIO_PIN_CONTROL 0x18 | |
39 | ||
40 | #define OMAP1510_IH_GPIO_BASE 64 | |
41 | ||
42 | /* | |
43 | * OMAP1610 specific GPIO registers | |
44 | */ | |
7c7095aa RK |
45 | #define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400) |
46 | #define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00) | |
47 | #define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400) | |
48 | #define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00) | |
5e1c5ff4 TL |
49 | #define OMAP1610_GPIO_REVISION 0x0000 |
50 | #define OMAP1610_GPIO_SYSCONFIG 0x0010 | |
51 | #define OMAP1610_GPIO_SYSSTATUS 0x0014 | |
52 | #define OMAP1610_GPIO_IRQSTATUS1 0x0018 | |
53 | #define OMAP1610_GPIO_IRQENABLE1 0x001c | |
92105bb7 | 54 | #define OMAP1610_GPIO_WAKEUPENABLE 0x0028 |
5e1c5ff4 TL |
55 | #define OMAP1610_GPIO_DATAIN 0x002c |
56 | #define OMAP1610_GPIO_DATAOUT 0x0030 | |
57 | #define OMAP1610_GPIO_DIRECTION 0x0034 | |
58 | #define OMAP1610_GPIO_EDGE_CTRL1 0x0038 | |
59 | #define OMAP1610_GPIO_EDGE_CTRL2 0x003c | |
60 | #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c | |
92105bb7 | 61 | #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8 |
5e1c5ff4 TL |
62 | #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0 |
63 | #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc | |
92105bb7 | 64 | #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8 |
5e1c5ff4 TL |
65 | #define OMAP1610_GPIO_SET_DATAOUT 0x00f0 |
66 | ||
67 | /* | |
68 | * OMAP730 specific GPIO registers | |
69 | */ | |
7c7095aa RK |
70 | #define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000) |
71 | #define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800) | |
72 | #define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000) | |
73 | #define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800) | |
74 | #define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000) | |
75 | #define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800) | |
5e1c5ff4 TL |
76 | #define OMAP730_GPIO_DATA_INPUT 0x00 |
77 | #define OMAP730_GPIO_DATA_OUTPUT 0x04 | |
78 | #define OMAP730_GPIO_DIR_CONTROL 0x08 | |
79 | #define OMAP730_GPIO_INT_CONTROL 0x0c | |
80 | #define OMAP730_GPIO_INT_MASK 0x10 | |
81 | #define OMAP730_GPIO_INT_STATUS 0x14 | |
82 | ||
92105bb7 TL |
83 | /* |
84 | * omap24xx specific GPIO registers | |
85 | */ | |
7c7095aa RK |
86 | #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000) |
87 | #define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000) | |
88 | #define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000) | |
89 | #define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000) | |
56a25641 | 90 | |
7c7095aa RK |
91 | #define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000) |
92 | #define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000) | |
93 | #define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000) | |
94 | #define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000) | |
95 | #define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000) | |
56a25641 | 96 | |
92105bb7 TL |
97 | #define OMAP24XX_GPIO_REVISION 0x0000 |
98 | #define OMAP24XX_GPIO_SYSCONFIG 0x0010 | |
99 | #define OMAP24XX_GPIO_SYSSTATUS 0x0014 | |
100 | #define OMAP24XX_GPIO_IRQSTATUS1 0x0018 | |
bee7930f HD |
101 | #define OMAP24XX_GPIO_IRQSTATUS2 0x0028 |
102 | #define OMAP24XX_GPIO_IRQENABLE2 0x002c | |
92105bb7 | 103 | #define OMAP24XX_GPIO_IRQENABLE1 0x001c |
723fdb78 | 104 | #define OMAP24XX_GPIO_WAKE_EN 0x0020 |
92105bb7 TL |
105 | #define OMAP24XX_GPIO_CTRL 0x0030 |
106 | #define OMAP24XX_GPIO_OE 0x0034 | |
107 | #define OMAP24XX_GPIO_DATAIN 0x0038 | |
108 | #define OMAP24XX_GPIO_DATAOUT 0x003c | |
109 | #define OMAP24XX_GPIO_LEVELDETECT0 0x0040 | |
110 | #define OMAP24XX_GPIO_LEVELDETECT1 0x0044 | |
111 | #define OMAP24XX_GPIO_RISINGDETECT 0x0048 | |
112 | #define OMAP24XX_GPIO_FALLINGDETECT 0x004c | |
5eb3bb9c KH |
113 | #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 |
114 | #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 | |
92105bb7 TL |
115 | #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 |
116 | #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 | |
117 | #define OMAP24XX_GPIO_CLEARWKUENA 0x0080 | |
118 | #define OMAP24XX_GPIO_SETWKUENA 0x0084 | |
119 | #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 | |
120 | #define OMAP24XX_GPIO_SETDATAOUT 0x0094 | |
121 | ||
5492fb1a SMK |
122 | /* |
123 | * omap34xx specific GPIO registers | |
124 | */ | |
125 | ||
7c7095aa RK |
126 | #define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000) |
127 | #define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000) | |
128 | #define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000) | |
129 | #define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000) | |
130 | #define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000) | |
131 | #define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000) | |
5492fb1a | 132 | |
7c7095aa | 133 | #define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE) |
5492fb1a | 134 | |
5e1c5ff4 | 135 | struct gpio_bank { |
92105bb7 | 136 | void __iomem *base; |
5e1c5ff4 TL |
137 | u16 irq; |
138 | u16 virtual_irq_start; | |
92105bb7 | 139 | int method; |
5492fb1a | 140 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
141 | u32 suspend_wakeup; |
142 | u32 saved_wakeup; | |
3ac4fa99 | 143 | #endif |
5492fb1a | 144 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
145 | u32 non_wakeup_gpios; |
146 | u32 enabled_non_wakeup_gpios; | |
147 | ||
148 | u32 saved_datain; | |
149 | u32 saved_fallingdetect; | |
150 | u32 saved_risingdetect; | |
151 | #endif | |
b144ff6f | 152 | u32 level_mask; |
5e1c5ff4 | 153 | spinlock_t lock; |
52e31344 | 154 | struct gpio_chip chip; |
89db9482 | 155 | struct clk *dbck; |
5e1c5ff4 TL |
156 | }; |
157 | ||
158 | #define METHOD_MPUIO 0 | |
159 | #define METHOD_GPIO_1510 1 | |
160 | #define METHOD_GPIO_1610 2 | |
161 | #define METHOD_GPIO_730 3 | |
92105bb7 | 162 | #define METHOD_GPIO_24XX 4 |
5e1c5ff4 | 163 | |
92105bb7 | 164 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 165 | static struct gpio_bank gpio_bank_1610[5] = { |
7c7095aa | 166 | { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO}, |
5e1c5ff4 TL |
167 | { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 }, |
168 | { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 }, | |
169 | { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 }, | |
170 | { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 }, | |
171 | }; | |
172 | #endif | |
173 | ||
1a8bfa1e | 174 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 175 | static struct gpio_bank gpio_bank_1510[2] = { |
7c7095aa | 176 | { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, |
5e1c5ff4 TL |
177 | { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 } |
178 | }; | |
179 | #endif | |
180 | ||
181 | #ifdef CONFIG_ARCH_OMAP730 | |
182 | static struct gpio_bank gpio_bank_730[7] = { | |
7c7095aa | 183 | { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, |
5e1c5ff4 TL |
184 | { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 }, |
185 | { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 }, | |
186 | { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 }, | |
187 | { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 }, | |
188 | { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 }, | |
189 | { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 }, | |
190 | }; | |
191 | #endif | |
192 | ||
92105bb7 | 193 | #ifdef CONFIG_ARCH_OMAP24XX |
56a25641 SMK |
194 | |
195 | static struct gpio_bank gpio_bank_242x[4] = { | |
196 | { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, | |
197 | { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, | |
198 | { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, | |
199 | { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, | |
92105bb7 | 200 | }; |
56a25641 SMK |
201 | |
202 | static struct gpio_bank gpio_bank_243x[5] = { | |
203 | { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, | |
204 | { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, | |
205 | { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, | |
206 | { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, | |
207 | { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX }, | |
208 | }; | |
209 | ||
92105bb7 TL |
210 | #endif |
211 | ||
5492fb1a SMK |
212 | #ifdef CONFIG_ARCH_OMAP34XX |
213 | static struct gpio_bank gpio_bank_34xx[6] = { | |
214 | { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, | |
215 | { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, | |
216 | { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, | |
217 | { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, | |
218 | { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX }, | |
219 | { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX }, | |
220 | }; | |
221 | ||
222 | #endif | |
223 | ||
5e1c5ff4 TL |
224 | static struct gpio_bank *gpio_bank; |
225 | static int gpio_bank_count; | |
226 | ||
227 | static inline struct gpio_bank *get_gpio_bank(int gpio) | |
228 | { | |
6e60e79a | 229 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
230 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
231 | return &gpio_bank[0]; | |
232 | return &gpio_bank[1]; | |
233 | } | |
5e1c5ff4 TL |
234 | if (cpu_is_omap16xx()) { |
235 | if (OMAP_GPIO_IS_MPUIO(gpio)) | |
236 | return &gpio_bank[0]; | |
237 | return &gpio_bank[1 + (gpio >> 4)]; | |
238 | } | |
5e1c5ff4 TL |
239 | if (cpu_is_omap730()) { |
240 | if (OMAP_GPIO_IS_MPUIO(gpio)) | |
241 | return &gpio_bank[0]; | |
242 | return &gpio_bank[1 + (gpio >> 5)]; | |
243 | } | |
92105bb7 TL |
244 | if (cpu_is_omap24xx()) |
245 | return &gpio_bank[gpio >> 5]; | |
5492fb1a SMK |
246 | if (cpu_is_omap34xx()) |
247 | return &gpio_bank[gpio >> 5]; | |
e031ab23 DB |
248 | BUG(); |
249 | return NULL; | |
5e1c5ff4 TL |
250 | } |
251 | ||
252 | static inline int get_gpio_index(int gpio) | |
253 | { | |
254 | if (cpu_is_omap730()) | |
255 | return gpio & 0x1f; | |
92105bb7 TL |
256 | if (cpu_is_omap24xx()) |
257 | return gpio & 0x1f; | |
5492fb1a SMK |
258 | if (cpu_is_omap34xx()) |
259 | return gpio & 0x1f; | |
92105bb7 | 260 | return gpio & 0x0f; |
5e1c5ff4 TL |
261 | } |
262 | ||
263 | static inline int gpio_valid(int gpio) | |
264 | { | |
265 | if (gpio < 0) | |
266 | return -1; | |
d11ac979 | 267 | if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) { |
193e68be | 268 | if (gpio >= OMAP_MAX_GPIO_LINES + 16) |
5e1c5ff4 TL |
269 | return -1; |
270 | return 0; | |
271 | } | |
6e60e79a | 272 | if (cpu_is_omap15xx() && gpio < 16) |
5e1c5ff4 | 273 | return 0; |
5e1c5ff4 TL |
274 | if ((cpu_is_omap16xx()) && gpio < 64) |
275 | return 0; | |
5e1c5ff4 TL |
276 | if (cpu_is_omap730() && gpio < 192) |
277 | return 0; | |
92105bb7 TL |
278 | if (cpu_is_omap24xx() && gpio < 128) |
279 | return 0; | |
5492fb1a SMK |
280 | if (cpu_is_omap34xx() && gpio < 160) |
281 | return 0; | |
5e1c5ff4 TL |
282 | return -1; |
283 | } | |
284 | ||
285 | static int check_gpio(int gpio) | |
286 | { | |
287 | if (unlikely(gpio_valid(gpio)) < 0) { | |
288 | printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio); | |
289 | dump_stack(); | |
290 | return -1; | |
291 | } | |
292 | return 0; | |
293 | } | |
294 | ||
295 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |
296 | { | |
92105bb7 | 297 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
298 | u32 l; |
299 | ||
300 | switch (bank->method) { | |
e5c56ed3 | 301 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
302 | case METHOD_MPUIO: |
303 | reg += OMAP_MPUIO_IO_CNTL; | |
304 | break; | |
e5c56ed3 DB |
305 | #endif |
306 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
307 | case METHOD_GPIO_1510: |
308 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
309 | break; | |
e5c56ed3 DB |
310 | #endif |
311 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
312 | case METHOD_GPIO_1610: |
313 | reg += OMAP1610_GPIO_DIRECTION; | |
314 | break; | |
e5c56ed3 DB |
315 | #endif |
316 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
317 | case METHOD_GPIO_730: |
318 | reg += OMAP730_GPIO_DIR_CONTROL; | |
319 | break; | |
e5c56ed3 | 320 | #endif |
5492fb1a | 321 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
322 | case METHOD_GPIO_24XX: |
323 | reg += OMAP24XX_GPIO_OE; | |
324 | break; | |
e5c56ed3 DB |
325 | #endif |
326 | default: | |
327 | WARN_ON(1); | |
328 | return; | |
5e1c5ff4 TL |
329 | } |
330 | l = __raw_readl(reg); | |
331 | if (is_input) | |
332 | l |= 1 << gpio; | |
333 | else | |
334 | l &= ~(1 << gpio); | |
335 | __raw_writel(l, reg); | |
336 | } | |
337 | ||
5e1c5ff4 TL |
338 | static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) |
339 | { | |
92105bb7 | 340 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
341 | u32 l = 0; |
342 | ||
343 | switch (bank->method) { | |
e5c56ed3 | 344 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
345 | case METHOD_MPUIO: |
346 | reg += OMAP_MPUIO_OUTPUT; | |
347 | l = __raw_readl(reg); | |
348 | if (enable) | |
349 | l |= 1 << gpio; | |
350 | else | |
351 | l &= ~(1 << gpio); | |
352 | break; | |
e5c56ed3 DB |
353 | #endif |
354 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
355 | case METHOD_GPIO_1510: |
356 | reg += OMAP1510_GPIO_DATA_OUTPUT; | |
357 | l = __raw_readl(reg); | |
358 | if (enable) | |
359 | l |= 1 << gpio; | |
360 | else | |
361 | l &= ~(1 << gpio); | |
362 | break; | |
e5c56ed3 DB |
363 | #endif |
364 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
365 | case METHOD_GPIO_1610: |
366 | if (enable) | |
367 | reg += OMAP1610_GPIO_SET_DATAOUT; | |
368 | else | |
369 | reg += OMAP1610_GPIO_CLEAR_DATAOUT; | |
370 | l = 1 << gpio; | |
371 | break; | |
e5c56ed3 DB |
372 | #endif |
373 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
374 | case METHOD_GPIO_730: |
375 | reg += OMAP730_GPIO_DATA_OUTPUT; | |
376 | l = __raw_readl(reg); | |
377 | if (enable) | |
378 | l |= 1 << gpio; | |
379 | else | |
380 | l &= ~(1 << gpio); | |
381 | break; | |
e5c56ed3 | 382 | #endif |
5492fb1a | 383 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
384 | case METHOD_GPIO_24XX: |
385 | if (enable) | |
386 | reg += OMAP24XX_GPIO_SETDATAOUT; | |
387 | else | |
388 | reg += OMAP24XX_GPIO_CLEARDATAOUT; | |
389 | l = 1 << gpio; | |
390 | break; | |
e5c56ed3 | 391 | #endif |
5e1c5ff4 | 392 | default: |
e5c56ed3 | 393 | WARN_ON(1); |
5e1c5ff4 TL |
394 | return; |
395 | } | |
396 | __raw_writel(l, reg); | |
397 | } | |
398 | ||
0b84b5ca | 399 | static int __omap_get_gpio_datain(int gpio) |
5e1c5ff4 TL |
400 | { |
401 | struct gpio_bank *bank; | |
92105bb7 | 402 | void __iomem *reg; |
5e1c5ff4 TL |
403 | |
404 | if (check_gpio(gpio) < 0) | |
e5c56ed3 | 405 | return -EINVAL; |
5e1c5ff4 TL |
406 | bank = get_gpio_bank(gpio); |
407 | reg = bank->base; | |
408 | switch (bank->method) { | |
e5c56ed3 | 409 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
410 | case METHOD_MPUIO: |
411 | reg += OMAP_MPUIO_INPUT_LATCH; | |
412 | break; | |
e5c56ed3 DB |
413 | #endif |
414 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
415 | case METHOD_GPIO_1510: |
416 | reg += OMAP1510_GPIO_DATA_INPUT; | |
417 | break; | |
e5c56ed3 DB |
418 | #endif |
419 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
420 | case METHOD_GPIO_1610: |
421 | reg += OMAP1610_GPIO_DATAIN; | |
422 | break; | |
e5c56ed3 DB |
423 | #endif |
424 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
425 | case METHOD_GPIO_730: |
426 | reg += OMAP730_GPIO_DATA_INPUT; | |
427 | break; | |
e5c56ed3 | 428 | #endif |
5492fb1a | 429 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
430 | case METHOD_GPIO_24XX: |
431 | reg += OMAP24XX_GPIO_DATAIN; | |
432 | break; | |
e5c56ed3 | 433 | #endif |
5e1c5ff4 | 434 | default: |
e5c56ed3 | 435 | return -EINVAL; |
5e1c5ff4 | 436 | } |
92105bb7 TL |
437 | return (__raw_readl(reg) |
438 | & (1 << get_gpio_index(gpio))) != 0; | |
5e1c5ff4 TL |
439 | } |
440 | ||
92105bb7 TL |
441 | #define MOD_REG_BIT(reg, bit_mask, set) \ |
442 | do { \ | |
443 | int l = __raw_readl(base + reg); \ | |
444 | if (set) l |= bit_mask; \ | |
445 | else l &= ~bit_mask; \ | |
446 | __raw_writel(l, base + reg); \ | |
447 | } while(0) | |
448 | ||
5eb3bb9c KH |
449 | void omap_set_gpio_debounce(int gpio, int enable) |
450 | { | |
451 | struct gpio_bank *bank; | |
452 | void __iomem *reg; | |
e031ab23 | 453 | unsigned long flags; |
5eb3bb9c KH |
454 | u32 val, l = 1 << get_gpio_index(gpio); |
455 | ||
456 | if (cpu_class_is_omap1()) | |
457 | return; | |
458 | ||
459 | bank = get_gpio_bank(gpio); | |
460 | reg = bank->base; | |
5eb3bb9c | 461 | reg += OMAP24XX_GPIO_DEBOUNCE_EN; |
e031ab23 DB |
462 | |
463 | spin_lock_irqsave(&bank->lock, flags); | |
5eb3bb9c KH |
464 | val = __raw_readl(reg); |
465 | ||
89db9482 | 466 | if (enable && !(val & l)) |
5eb3bb9c | 467 | val |= l; |
e031ab23 | 468 | else if (!enable && (val & l)) |
5eb3bb9c | 469 | val &= ~l; |
89db9482 | 470 | else |
e031ab23 | 471 | goto done; |
89db9482 | 472 | |
e031ab23 DB |
473 | if (cpu_is_omap34xx()) { |
474 | if (enable) | |
475 | clk_enable(bank->dbck); | |
476 | else | |
477 | clk_disable(bank->dbck); | |
478 | } | |
5eb3bb9c KH |
479 | |
480 | __raw_writel(val, reg); | |
e031ab23 DB |
481 | done: |
482 | spin_unlock_irqrestore(&bank->lock, flags); | |
5eb3bb9c KH |
483 | } |
484 | EXPORT_SYMBOL(omap_set_gpio_debounce); | |
485 | ||
486 | void omap_set_gpio_debounce_time(int gpio, int enc_time) | |
487 | { | |
488 | struct gpio_bank *bank; | |
489 | void __iomem *reg; | |
490 | ||
491 | if (cpu_class_is_omap1()) | |
492 | return; | |
493 | ||
494 | bank = get_gpio_bank(gpio); | |
495 | reg = bank->base; | |
496 | ||
497 | enc_time &= 0xff; | |
498 | reg += OMAP24XX_GPIO_DEBOUNCE_VAL; | |
499 | __raw_writel(enc_time, reg); | |
500 | } | |
501 | EXPORT_SYMBOL(omap_set_gpio_debounce_time); | |
502 | ||
5492fb1a | 503 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
5eb3bb9c KH |
504 | static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, |
505 | int trigger) | |
5e1c5ff4 | 506 | { |
3ac4fa99 | 507 | void __iomem *base = bank->base; |
92105bb7 TL |
508 | u32 gpio_bit = 1 << gpio; |
509 | ||
510 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, | |
6cab4860 | 511 | trigger & IRQ_TYPE_LEVEL_LOW); |
92105bb7 | 512 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, |
6cab4860 | 513 | trigger & IRQ_TYPE_LEVEL_HIGH); |
92105bb7 | 514 | MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, |
6cab4860 | 515 | trigger & IRQ_TYPE_EDGE_RISING); |
92105bb7 | 516 | MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, |
6cab4860 | 517 | trigger & IRQ_TYPE_EDGE_FALLING); |
5eb3bb9c | 518 | |
3ac4fa99 JY |
519 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { |
520 | if (trigger != 0) | |
5eb3bb9c KH |
521 | __raw_writel(1 << gpio, bank->base |
522 | + OMAP24XX_GPIO_SETWKUENA); | |
3ac4fa99 | 523 | else |
5eb3bb9c KH |
524 | __raw_writel(1 << gpio, bank->base |
525 | + OMAP24XX_GPIO_CLEARWKUENA); | |
3ac4fa99 JY |
526 | } else { |
527 | if (trigger != 0) | |
528 | bank->enabled_non_wakeup_gpios |= gpio_bit; | |
529 | else | |
530 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
531 | } | |
5eb3bb9c | 532 | |
b144ff6f KH |
533 | bank->level_mask = |
534 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) | | |
535 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
92105bb7 | 536 | } |
3ac4fa99 | 537 | #endif |
92105bb7 TL |
538 | |
539 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) | |
540 | { | |
541 | void __iomem *reg = bank->base; | |
542 | u32 l = 0; | |
5e1c5ff4 TL |
543 | |
544 | switch (bank->method) { | |
e5c56ed3 | 545 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
546 | case METHOD_MPUIO: |
547 | reg += OMAP_MPUIO_GPIO_INT_EDGE; | |
548 | l = __raw_readl(reg); | |
6cab4860 | 549 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 550 | l |= 1 << gpio; |
6cab4860 | 551 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 552 | l &= ~(1 << gpio); |
92105bb7 TL |
553 | else |
554 | goto bad; | |
5e1c5ff4 | 555 | break; |
e5c56ed3 DB |
556 | #endif |
557 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
558 | case METHOD_GPIO_1510: |
559 | reg += OMAP1510_GPIO_INT_CONTROL; | |
560 | l = __raw_readl(reg); | |
6cab4860 | 561 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 562 | l |= 1 << gpio; |
6cab4860 | 563 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 564 | l &= ~(1 << gpio); |
92105bb7 TL |
565 | else |
566 | goto bad; | |
5e1c5ff4 | 567 | break; |
e5c56ed3 | 568 | #endif |
3ac4fa99 | 569 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 570 | case METHOD_GPIO_1610: |
5e1c5ff4 TL |
571 | if (gpio & 0x08) |
572 | reg += OMAP1610_GPIO_EDGE_CTRL2; | |
573 | else | |
574 | reg += OMAP1610_GPIO_EDGE_CTRL1; | |
575 | gpio &= 0x07; | |
576 | l = __raw_readl(reg); | |
577 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 578 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 579 | l |= 2 << (gpio << 1); |
6cab4860 | 580 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 581 | l |= 1 << (gpio << 1); |
3ac4fa99 JY |
582 | if (trigger) |
583 | /* Enable wake-up during idle for dynamic tick */ | |
584 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA); | |
585 | else | |
586 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); | |
5e1c5ff4 | 587 | break; |
3ac4fa99 JY |
588 | #endif |
589 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
590 | case METHOD_GPIO_730: |
591 | reg += OMAP730_GPIO_INT_CONTROL; | |
592 | l = __raw_readl(reg); | |
6cab4860 | 593 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 594 | l |= 1 << gpio; |
6cab4860 | 595 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 596 | l &= ~(1 << gpio); |
92105bb7 TL |
597 | else |
598 | goto bad; | |
599 | break; | |
3ac4fa99 | 600 | #endif |
5492fb1a | 601 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 | 602 | case METHOD_GPIO_24XX: |
3ac4fa99 | 603 | set_24xx_gpio_triggering(bank, gpio, trigger); |
5e1c5ff4 | 604 | break; |
3ac4fa99 | 605 | #endif |
5e1c5ff4 | 606 | default: |
92105bb7 | 607 | goto bad; |
5e1c5ff4 | 608 | } |
92105bb7 TL |
609 | __raw_writel(l, reg); |
610 | return 0; | |
611 | bad: | |
612 | return -EINVAL; | |
5e1c5ff4 TL |
613 | } |
614 | ||
92105bb7 | 615 | static int gpio_irq_type(unsigned irq, unsigned type) |
5e1c5ff4 TL |
616 | { |
617 | struct gpio_bank *bank; | |
92105bb7 TL |
618 | unsigned gpio; |
619 | int retval; | |
a6472533 | 620 | unsigned long flags; |
92105bb7 | 621 | |
5492fb1a | 622 | if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE) |
92105bb7 TL |
623 | gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); |
624 | else | |
625 | gpio = irq - IH_GPIO_BASE; | |
5e1c5ff4 TL |
626 | |
627 | if (check_gpio(gpio) < 0) | |
92105bb7 TL |
628 | return -EINVAL; |
629 | ||
e5c56ed3 | 630 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 631 | return -EINVAL; |
e5c56ed3 DB |
632 | |
633 | /* OMAP1 allows only only edge triggering */ | |
5492fb1a | 634 | if (!cpu_class_is_omap2() |
e5c56ed3 | 635 | && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) |
92105bb7 TL |
636 | return -EINVAL; |
637 | ||
58781016 | 638 | bank = get_irq_chip_data(irq); |
a6472533 | 639 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 640 | retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); |
b9772a22 DB |
641 | if (retval == 0) { |
642 | irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; | |
643 | irq_desc[irq].status |= type; | |
644 | } | |
a6472533 | 645 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
646 | |
647 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
648 | __set_irq_handler_unlocked(irq, handle_level_irq); | |
649 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
650 | __set_irq_handler_unlocked(irq, handle_edge_irq); | |
651 | ||
92105bb7 | 652 | return retval; |
5e1c5ff4 TL |
653 | } |
654 | ||
655 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
656 | { | |
92105bb7 | 657 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
658 | |
659 | switch (bank->method) { | |
e5c56ed3 | 660 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
661 | case METHOD_MPUIO: |
662 | /* MPUIO irqstatus is reset by reading the status register, | |
663 | * so do nothing here */ | |
664 | return; | |
e5c56ed3 DB |
665 | #endif |
666 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
667 | case METHOD_GPIO_1510: |
668 | reg += OMAP1510_GPIO_INT_STATUS; | |
669 | break; | |
e5c56ed3 DB |
670 | #endif |
671 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
672 | case METHOD_GPIO_1610: |
673 | reg += OMAP1610_GPIO_IRQSTATUS1; | |
674 | break; | |
e5c56ed3 DB |
675 | #endif |
676 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
677 | case METHOD_GPIO_730: |
678 | reg += OMAP730_GPIO_INT_STATUS; | |
679 | break; | |
e5c56ed3 | 680 | #endif |
5492fb1a | 681 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
682 | case METHOD_GPIO_24XX: |
683 | reg += OMAP24XX_GPIO_IRQSTATUS1; | |
684 | break; | |
e5c56ed3 | 685 | #endif |
5e1c5ff4 | 686 | default: |
e5c56ed3 | 687 | WARN_ON(1); |
5e1c5ff4 TL |
688 | return; |
689 | } | |
690 | __raw_writel(gpio_mask, reg); | |
bee7930f HD |
691 | |
692 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
5492fb1a SMK |
693 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
694 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
bee7930f | 695 | __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2); |
5492fb1a | 696 | #endif |
5e1c5ff4 TL |
697 | } |
698 | ||
699 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
700 | { | |
701 | _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio)); | |
702 | } | |
703 | ||
ea6dedd7 ID |
704 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
705 | { | |
706 | void __iomem *reg = bank->base; | |
99c47707 ID |
707 | int inv = 0; |
708 | u32 l; | |
709 | u32 mask; | |
ea6dedd7 ID |
710 | |
711 | switch (bank->method) { | |
e5c56ed3 | 712 | #ifdef CONFIG_ARCH_OMAP1 |
ea6dedd7 ID |
713 | case METHOD_MPUIO: |
714 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
99c47707 ID |
715 | mask = 0xffff; |
716 | inv = 1; | |
ea6dedd7 | 717 | break; |
e5c56ed3 DB |
718 | #endif |
719 | #ifdef CONFIG_ARCH_OMAP15XX | |
ea6dedd7 ID |
720 | case METHOD_GPIO_1510: |
721 | reg += OMAP1510_GPIO_INT_MASK; | |
99c47707 ID |
722 | mask = 0xffff; |
723 | inv = 1; | |
ea6dedd7 | 724 | break; |
e5c56ed3 DB |
725 | #endif |
726 | #ifdef CONFIG_ARCH_OMAP16XX | |
ea6dedd7 ID |
727 | case METHOD_GPIO_1610: |
728 | reg += OMAP1610_GPIO_IRQENABLE1; | |
99c47707 | 729 | mask = 0xffff; |
ea6dedd7 | 730 | break; |
e5c56ed3 DB |
731 | #endif |
732 | #ifdef CONFIG_ARCH_OMAP730 | |
ea6dedd7 ID |
733 | case METHOD_GPIO_730: |
734 | reg += OMAP730_GPIO_INT_MASK; | |
99c47707 ID |
735 | mask = 0xffffffff; |
736 | inv = 1; | |
ea6dedd7 | 737 | break; |
e5c56ed3 | 738 | #endif |
5492fb1a | 739 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
ea6dedd7 ID |
740 | case METHOD_GPIO_24XX: |
741 | reg += OMAP24XX_GPIO_IRQENABLE1; | |
99c47707 | 742 | mask = 0xffffffff; |
ea6dedd7 | 743 | break; |
e5c56ed3 | 744 | #endif |
ea6dedd7 | 745 | default: |
e5c56ed3 | 746 | WARN_ON(1); |
ea6dedd7 ID |
747 | return 0; |
748 | } | |
749 | ||
99c47707 ID |
750 | l = __raw_readl(reg); |
751 | if (inv) | |
752 | l = ~l; | |
753 | l &= mask; | |
754 | return l; | |
ea6dedd7 ID |
755 | } |
756 | ||
5e1c5ff4 TL |
757 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) |
758 | { | |
92105bb7 | 759 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
760 | u32 l; |
761 | ||
762 | switch (bank->method) { | |
e5c56ed3 | 763 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
764 | case METHOD_MPUIO: |
765 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
766 | l = __raw_readl(reg); | |
767 | if (enable) | |
768 | l &= ~(gpio_mask); | |
769 | else | |
770 | l |= gpio_mask; | |
771 | break; | |
e5c56ed3 DB |
772 | #endif |
773 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
774 | case METHOD_GPIO_1510: |
775 | reg += OMAP1510_GPIO_INT_MASK; | |
776 | l = __raw_readl(reg); | |
777 | if (enable) | |
778 | l &= ~(gpio_mask); | |
779 | else | |
780 | l |= gpio_mask; | |
781 | break; | |
e5c56ed3 DB |
782 | #endif |
783 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
784 | case METHOD_GPIO_1610: |
785 | if (enable) | |
786 | reg += OMAP1610_GPIO_SET_IRQENABLE1; | |
787 | else | |
788 | reg += OMAP1610_GPIO_CLEAR_IRQENABLE1; | |
789 | l = gpio_mask; | |
790 | break; | |
e5c56ed3 DB |
791 | #endif |
792 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
793 | case METHOD_GPIO_730: |
794 | reg += OMAP730_GPIO_INT_MASK; | |
795 | l = __raw_readl(reg); | |
796 | if (enable) | |
797 | l &= ~(gpio_mask); | |
798 | else | |
799 | l |= gpio_mask; | |
800 | break; | |
e5c56ed3 | 801 | #endif |
5492fb1a | 802 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
803 | case METHOD_GPIO_24XX: |
804 | if (enable) | |
805 | reg += OMAP24XX_GPIO_SETIRQENABLE1; | |
806 | else | |
807 | reg += OMAP24XX_GPIO_CLEARIRQENABLE1; | |
808 | l = gpio_mask; | |
809 | break; | |
e5c56ed3 | 810 | #endif |
5e1c5ff4 | 811 | default: |
e5c56ed3 | 812 | WARN_ON(1); |
5e1c5ff4 TL |
813 | return; |
814 | } | |
815 | __raw_writel(l, reg); | |
816 | } | |
817 | ||
818 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
819 | { | |
820 | _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable); | |
821 | } | |
822 | ||
92105bb7 TL |
823 | /* |
824 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
825 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
826 | * to the target, system will wake up always on GPIO events. While | |
827 | * system is running all registered GPIO interrupts need to have wake-up | |
828 | * enabled. When system is suspended, only selected GPIO interrupts need | |
829 | * to have wake-up enabled. | |
830 | */ | |
831 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
832 | { | |
a6472533 DB |
833 | unsigned long flags; |
834 | ||
92105bb7 | 835 | switch (bank->method) { |
3ac4fa99 | 836 | #ifdef CONFIG_ARCH_OMAP16XX |
11a78b79 | 837 | case METHOD_MPUIO: |
92105bb7 | 838 | case METHOD_GPIO_1610: |
a6472533 | 839 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 840 | if (enable) { |
92105bb7 | 841 | bank->suspend_wakeup |= (1 << gpio); |
11a78b79 DB |
842 | enable_irq_wake(bank->irq); |
843 | } else { | |
844 | disable_irq_wake(bank->irq); | |
92105bb7 | 845 | bank->suspend_wakeup &= ~(1 << gpio); |
11a78b79 | 846 | } |
a6472533 | 847 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 848 | return 0; |
3ac4fa99 | 849 | #endif |
5492fb1a | 850 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 | 851 | case METHOD_GPIO_24XX: |
11a78b79 DB |
852 | if (bank->non_wakeup_gpios & (1 << gpio)) { |
853 | printk(KERN_ERR "Unable to modify wakeup on " | |
854 | "non-wakeup GPIO%d\n", | |
855 | (bank - gpio_bank) * 32 + gpio); | |
856 | return -EINVAL; | |
857 | } | |
a6472533 | 858 | spin_lock_irqsave(&bank->lock, flags); |
3ac4fa99 | 859 | if (enable) { |
3ac4fa99 | 860 | bank->suspend_wakeup |= (1 << gpio); |
11a78b79 DB |
861 | enable_irq_wake(bank->irq); |
862 | } else { | |
863 | disable_irq_wake(bank->irq); | |
3ac4fa99 | 864 | bank->suspend_wakeup &= ~(1 << gpio); |
11a78b79 | 865 | } |
a6472533 | 866 | spin_unlock_irqrestore(&bank->lock, flags); |
3ac4fa99 JY |
867 | return 0; |
868 | #endif | |
92105bb7 TL |
869 | default: |
870 | printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n", | |
871 | bank->method); | |
872 | return -EINVAL; | |
873 | } | |
874 | } | |
875 | ||
4196dd6b TL |
876 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
877 | { | |
878 | _set_gpio_direction(bank, get_gpio_index(gpio), 1); | |
879 | _set_gpio_irqenable(bank, gpio, 0); | |
880 | _clear_gpio_irqstatus(bank, gpio); | |
6cab4860 | 881 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); |
4196dd6b TL |
882 | } |
883 | ||
92105bb7 TL |
884 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
885 | static int gpio_wake_enable(unsigned int irq, unsigned int enable) | |
886 | { | |
887 | unsigned int gpio = irq - IH_GPIO_BASE; | |
888 | struct gpio_bank *bank; | |
889 | int retval; | |
890 | ||
891 | if (check_gpio(gpio) < 0) | |
892 | return -ENODEV; | |
58781016 | 893 | bank = get_irq_chip_data(irq); |
92105bb7 | 894 | retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); |
92105bb7 TL |
895 | |
896 | return retval; | |
897 | } | |
898 | ||
3ff164e1 | 899 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 900 | { |
3ff164e1 | 901 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 902 | unsigned long flags; |
52e31344 | 903 | |
a6472533 | 904 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 905 | |
4196dd6b TL |
906 | /* Set trigger to none. You need to enable the desired trigger with |
907 | * request_irq() or set_irq_type(). | |
908 | */ | |
3ff164e1 | 909 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
92105bb7 | 910 | |
1a8bfa1e | 911 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 912 | if (bank->method == METHOD_GPIO_1510) { |
92105bb7 | 913 | void __iomem *reg; |
5e1c5ff4 | 914 | |
92105bb7 | 915 | /* Claim the pin for MPU */ |
5e1c5ff4 | 916 | reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; |
3ff164e1 | 917 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
5e1c5ff4 TL |
918 | } |
919 | #endif | |
a6472533 | 920 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
921 | |
922 | return 0; | |
923 | } | |
924 | ||
3ff164e1 | 925 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 926 | { |
3ff164e1 | 927 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 928 | unsigned long flags; |
5e1c5ff4 | 929 | |
a6472533 | 930 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
931 | #ifdef CONFIG_ARCH_OMAP16XX |
932 | if (bank->method == METHOD_GPIO_1610) { | |
933 | /* Disable wake-up during idle for dynamic tick */ | |
934 | void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
3ff164e1 | 935 | __raw_writel(1 << offset, reg); |
92105bb7 TL |
936 | } |
937 | #endif | |
5492fb1a | 938 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
939 | if (bank->method == METHOD_GPIO_24XX) { |
940 | /* Disable wake-up during idle for dynamic tick */ | |
941 | void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; | |
3ff164e1 | 942 | __raw_writel(1 << offset, reg); |
92105bb7 TL |
943 | } |
944 | #endif | |
3ff164e1 | 945 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 946 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
947 | } |
948 | ||
949 | /* | |
950 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
951 | * avoid missing GPIO interrupts for other lines in the bank. | |
952 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
953 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
954 | * If we wait to unmask individual GPIO lines in the bank after the | |
955 | * line's interrupt handler has been run, we may miss some nested | |
956 | * interrupts. | |
957 | */ | |
10dd5ce2 | 958 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 959 | { |
92105bb7 | 960 | void __iomem *isr_reg = NULL; |
5e1c5ff4 TL |
961 | u32 isr; |
962 | unsigned int gpio_irq; | |
963 | struct gpio_bank *bank; | |
ea6dedd7 ID |
964 | u32 retrigger = 0; |
965 | int unmasked = 0; | |
5e1c5ff4 TL |
966 | |
967 | desc->chip->ack(irq); | |
968 | ||
418ca1f0 | 969 | bank = get_irq_data(irq); |
e5c56ed3 | 970 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
971 | if (bank->method == METHOD_MPUIO) |
972 | isr_reg = bank->base + OMAP_MPUIO_GPIO_INT; | |
e5c56ed3 | 973 | #endif |
1a8bfa1e | 974 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 TL |
975 | if (bank->method == METHOD_GPIO_1510) |
976 | isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS; | |
977 | #endif | |
978 | #if defined(CONFIG_ARCH_OMAP16XX) | |
979 | if (bank->method == METHOD_GPIO_1610) | |
980 | isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; | |
981 | #endif | |
982 | #ifdef CONFIG_ARCH_OMAP730 | |
983 | if (bank->method == METHOD_GPIO_730) | |
984 | isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; | |
985 | #endif | |
5492fb1a | 986 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
987 | if (bank->method == METHOD_GPIO_24XX) |
988 | isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; | |
989 | #endif | |
92105bb7 | 990 | while(1) { |
6e60e79a | 991 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 992 | u32 enabled; |
6e60e79a | 993 | |
ea6dedd7 ID |
994 | enabled = _get_gpio_irqbank_mask(bank); |
995 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a TL |
996 | |
997 | if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) | |
998 | isr &= 0x0000ffff; | |
999 | ||
5492fb1a | 1000 | if (cpu_class_is_omap2()) { |
b144ff6f | 1001 | level_mask = bank->level_mask & enabled; |
ea6dedd7 | 1002 | } |
6e60e79a TL |
1003 | |
1004 | /* clear edge sensitive interrupts before handler(s) are | |
1005 | called so that we don't miss any interrupt occurred while | |
1006 | executing them */ | |
1007 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0); | |
1008 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); | |
1009 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1); | |
1010 | ||
1011 | /* if there is only edge sensitive GPIO pin interrupts | |
1012 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
1013 | if (!level_mask && !unmasked) { |
1014 | unmasked = 1; | |
6e60e79a | 1015 | desc->chip->unmask(irq); |
ea6dedd7 | 1016 | } |
92105bb7 | 1017 | |
ea6dedd7 ID |
1018 | isr |= retrigger; |
1019 | retrigger = 0; | |
92105bb7 TL |
1020 | if (!isr) |
1021 | break; | |
1022 | ||
1023 | gpio_irq = bank->virtual_irq_start; | |
1024 | for (; isr != 0; isr >>= 1, gpio_irq++) { | |
92105bb7 TL |
1025 | if (!(isr & 1)) |
1026 | continue; | |
29454dde | 1027 | |
d8aa0251 | 1028 | generic_handle_irq(gpio_irq); |
92105bb7 | 1029 | } |
1a8bfa1e | 1030 | } |
ea6dedd7 ID |
1031 | /* if bank has any level sensitive GPIO pin interrupt |
1032 | configured, we must unmask the bank interrupt only after | |
1033 | handler(s) are executed in order to avoid spurious bank | |
1034 | interrupt */ | |
1035 | if (!unmasked) | |
1036 | desc->chip->unmask(irq); | |
1037 | ||
5e1c5ff4 TL |
1038 | } |
1039 | ||
4196dd6b TL |
1040 | static void gpio_irq_shutdown(unsigned int irq) |
1041 | { | |
1042 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1043 | struct gpio_bank *bank = get_irq_chip_data(irq); |
4196dd6b TL |
1044 | |
1045 | _reset_gpio(bank, gpio); | |
1046 | } | |
1047 | ||
5e1c5ff4 TL |
1048 | static void gpio_ack_irq(unsigned int irq) |
1049 | { | |
1050 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1051 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1052 | |
1053 | _clear_gpio_irqstatus(bank, gpio); | |
1054 | } | |
1055 | ||
1056 | static void gpio_mask_irq(unsigned int irq) | |
1057 | { | |
1058 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1059 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1060 | |
1061 | _set_gpio_irqenable(bank, gpio, 0); | |
1062 | } | |
1063 | ||
1064 | static void gpio_unmask_irq(unsigned int irq) | |
1065 | { | |
1066 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1067 | struct gpio_bank *bank = get_irq_chip_data(irq); |
b144ff6f KH |
1068 | unsigned int irq_mask = 1 << get_gpio_index(gpio); |
1069 | ||
1070 | /* For level-triggered GPIOs, the clearing must be done after | |
1071 | * the HW source is cleared, thus after the handler has run */ | |
1072 | if (bank->level_mask & irq_mask) { | |
1073 | _set_gpio_irqenable(bank, gpio, 0); | |
1074 | _clear_gpio_irqstatus(bank, gpio); | |
1075 | } | |
5e1c5ff4 | 1076 | |
4de8c75b | 1077 | _set_gpio_irqenable(bank, gpio, 1); |
5e1c5ff4 TL |
1078 | } |
1079 | ||
e5c56ed3 DB |
1080 | static struct irq_chip gpio_irq_chip = { |
1081 | .name = "GPIO", | |
1082 | .shutdown = gpio_irq_shutdown, | |
1083 | .ack = gpio_ack_irq, | |
1084 | .mask = gpio_mask_irq, | |
1085 | .unmask = gpio_unmask_irq, | |
1086 | .set_type = gpio_irq_type, | |
1087 | .set_wake = gpio_wake_enable, | |
1088 | }; | |
1089 | ||
1090 | /*---------------------------------------------------------------------*/ | |
1091 | ||
1092 | #ifdef CONFIG_ARCH_OMAP1 | |
1093 | ||
1094 | /* MPUIO uses the always-on 32k clock */ | |
1095 | ||
5e1c5ff4 TL |
1096 | static void mpuio_ack_irq(unsigned int irq) |
1097 | { | |
1098 | /* The ISR is reset automatically, so do nothing here. */ | |
1099 | } | |
1100 | ||
1101 | static void mpuio_mask_irq(unsigned int irq) | |
1102 | { | |
1103 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1104 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1105 | |
1106 | _set_gpio_irqenable(bank, gpio, 0); | |
1107 | } | |
1108 | ||
1109 | static void mpuio_unmask_irq(unsigned int irq) | |
1110 | { | |
1111 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1112 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1113 | |
1114 | _set_gpio_irqenable(bank, gpio, 1); | |
1115 | } | |
1116 | ||
e5c56ed3 DB |
1117 | static struct irq_chip mpuio_irq_chip = { |
1118 | .name = "MPUIO", | |
1119 | .ack = mpuio_ack_irq, | |
1120 | .mask = mpuio_mask_irq, | |
1121 | .unmask = mpuio_unmask_irq, | |
92105bb7 | 1122 | .set_type = gpio_irq_type, |
11a78b79 DB |
1123 | #ifdef CONFIG_ARCH_OMAP16XX |
1124 | /* REVISIT: assuming only 16xx supports MPUIO wake events */ | |
1125 | .set_wake = gpio_wake_enable, | |
1126 | #endif | |
5e1c5ff4 TL |
1127 | }; |
1128 | ||
e5c56ed3 DB |
1129 | |
1130 | #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) | |
1131 | ||
11a78b79 DB |
1132 | |
1133 | #ifdef CONFIG_ARCH_OMAP16XX | |
1134 | ||
1135 | #include <linux/platform_device.h> | |
1136 | ||
1137 | static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg) | |
1138 | { | |
1139 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1140 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
a6472533 | 1141 | unsigned long flags; |
11a78b79 | 1142 | |
a6472533 | 1143 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 DB |
1144 | bank->saved_wakeup = __raw_readl(mask_reg); |
1145 | __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); | |
a6472533 | 1146 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1147 | |
1148 | return 0; | |
1149 | } | |
1150 | ||
1151 | static int omap_mpuio_resume_early(struct platform_device *pdev) | |
1152 | { | |
1153 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1154 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
a6472533 | 1155 | unsigned long flags; |
11a78b79 | 1156 | |
a6472533 | 1157 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 1158 | __raw_writel(bank->saved_wakeup, mask_reg); |
a6472533 | 1159 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1160 | |
1161 | return 0; | |
1162 | } | |
1163 | ||
1164 | /* use platform_driver for this, now that there's no longer any | |
1165 | * point to sys_device (other than not disturbing old code). | |
1166 | */ | |
1167 | static struct platform_driver omap_mpuio_driver = { | |
1168 | .suspend_late = omap_mpuio_suspend_late, | |
1169 | .resume_early = omap_mpuio_resume_early, | |
1170 | .driver = { | |
1171 | .name = "mpuio", | |
1172 | }, | |
1173 | }; | |
1174 | ||
1175 | static struct platform_device omap_mpuio_device = { | |
1176 | .name = "mpuio", | |
1177 | .id = -1, | |
1178 | .dev = { | |
1179 | .driver = &omap_mpuio_driver.driver, | |
1180 | } | |
1181 | /* could list the /proc/iomem resources */ | |
1182 | }; | |
1183 | ||
1184 | static inline void mpuio_init(void) | |
1185 | { | |
fcf126d8 DB |
1186 | platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]); |
1187 | ||
11a78b79 DB |
1188 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
1189 | (void) platform_device_register(&omap_mpuio_device); | |
1190 | } | |
1191 | ||
1192 | #else | |
1193 | static inline void mpuio_init(void) {} | |
1194 | #endif /* 16xx */ | |
1195 | ||
e5c56ed3 DB |
1196 | #else |
1197 | ||
1198 | extern struct irq_chip mpuio_irq_chip; | |
1199 | ||
1200 | #define bank_is_mpuio(bank) 0 | |
11a78b79 | 1201 | static inline void mpuio_init(void) {} |
e5c56ed3 DB |
1202 | |
1203 | #endif | |
1204 | ||
1205 | /*---------------------------------------------------------------------*/ | |
5e1c5ff4 | 1206 | |
52e31344 DB |
1207 | /* REVISIT these are stupid implementations! replace by ones that |
1208 | * don't switch on METHOD_* and which mostly avoid spinlocks | |
1209 | */ | |
1210 | ||
1211 | static int gpio_input(struct gpio_chip *chip, unsigned offset) | |
1212 | { | |
1213 | struct gpio_bank *bank; | |
1214 | unsigned long flags; | |
1215 | ||
1216 | bank = container_of(chip, struct gpio_bank, chip); | |
1217 | spin_lock_irqsave(&bank->lock, flags); | |
1218 | _set_gpio_direction(bank, offset, 1); | |
1219 | spin_unlock_irqrestore(&bank->lock, flags); | |
1220 | return 0; | |
1221 | } | |
1222 | ||
1223 | static int gpio_get(struct gpio_chip *chip, unsigned offset) | |
1224 | { | |
0b84b5ca | 1225 | return __omap_get_gpio_datain(chip->base + offset); |
52e31344 DB |
1226 | } |
1227 | ||
1228 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
1229 | { | |
1230 | struct gpio_bank *bank; | |
1231 | unsigned long flags; | |
1232 | ||
1233 | bank = container_of(chip, struct gpio_bank, chip); | |
1234 | spin_lock_irqsave(&bank->lock, flags); | |
1235 | _set_gpio_dataout(bank, offset, value); | |
1236 | _set_gpio_direction(bank, offset, 0); | |
1237 | spin_unlock_irqrestore(&bank->lock, flags); | |
1238 | return 0; | |
1239 | } | |
1240 | ||
1241 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
1242 | { | |
1243 | struct gpio_bank *bank; | |
1244 | unsigned long flags; | |
1245 | ||
1246 | bank = container_of(chip, struct gpio_bank, chip); | |
1247 | spin_lock_irqsave(&bank->lock, flags); | |
1248 | _set_gpio_dataout(bank, offset, value); | |
1249 | spin_unlock_irqrestore(&bank->lock, flags); | |
1250 | } | |
1251 | ||
a007b709 DB |
1252 | static int gpio_2irq(struct gpio_chip *chip, unsigned offset) |
1253 | { | |
1254 | struct gpio_bank *bank; | |
1255 | ||
1256 | bank = container_of(chip, struct gpio_bank, chip); | |
1257 | return bank->virtual_irq_start + offset; | |
1258 | } | |
1259 | ||
52e31344 DB |
1260 | /*---------------------------------------------------------------------*/ |
1261 | ||
1a8bfa1e | 1262 | static int initialized; |
5492fb1a | 1263 | #if !defined(CONFIG_ARCH_OMAP3) |
1a8bfa1e | 1264 | static struct clk * gpio_ick; |
5492fb1a SMK |
1265 | #endif |
1266 | ||
1267 | #if defined(CONFIG_ARCH_OMAP2) | |
1a8bfa1e | 1268 | static struct clk * gpio_fck; |
5492fb1a | 1269 | #endif |
5e1c5ff4 | 1270 | |
5492fb1a | 1271 | #if defined(CONFIG_ARCH_OMAP2430) |
56a25641 SMK |
1272 | static struct clk * gpio5_ick; |
1273 | static struct clk * gpio5_fck; | |
1274 | #endif | |
1275 | ||
5492fb1a | 1276 | #if defined(CONFIG_ARCH_OMAP3) |
5492fb1a SMK |
1277 | static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; |
1278 | #endif | |
1279 | ||
8ba55c5c DB |
1280 | /* This lock class tells lockdep that GPIO irqs are in a different |
1281 | * category than their parents, so it won't report false recursion. | |
1282 | */ | |
1283 | static struct lock_class_key gpio_lock_class; | |
1284 | ||
5e1c5ff4 TL |
1285 | static int __init _omap_gpio_init(void) |
1286 | { | |
1287 | int i; | |
52e31344 | 1288 | int gpio = 0; |
5e1c5ff4 | 1289 | struct gpio_bank *bank; |
5492fb1a | 1290 | char clk_name[11]; |
5e1c5ff4 TL |
1291 | |
1292 | initialized = 1; | |
1293 | ||
5492fb1a | 1294 | #if defined(CONFIG_ARCH_OMAP1) |
6e60e79a | 1295 | if (cpu_is_omap15xx()) { |
1a8bfa1e TL |
1296 | gpio_ick = clk_get(NULL, "arm_gpio_ck"); |
1297 | if (IS_ERR(gpio_ick)) | |
92105bb7 TL |
1298 | printk("Could not get arm_gpio_ck\n"); |
1299 | else | |
30ff720b | 1300 | clk_enable(gpio_ick); |
1a8bfa1e | 1301 | } |
5492fb1a SMK |
1302 | #endif |
1303 | #if defined(CONFIG_ARCH_OMAP2) | |
1304 | if (cpu_class_is_omap2()) { | |
1a8bfa1e TL |
1305 | gpio_ick = clk_get(NULL, "gpios_ick"); |
1306 | if (IS_ERR(gpio_ick)) | |
1307 | printk("Could not get gpios_ick\n"); | |
1308 | else | |
30ff720b | 1309 | clk_enable(gpio_ick); |
1a8bfa1e | 1310 | gpio_fck = clk_get(NULL, "gpios_fck"); |
1630b52d | 1311 | if (IS_ERR(gpio_fck)) |
1a8bfa1e TL |
1312 | printk("Could not get gpios_fck\n"); |
1313 | else | |
30ff720b | 1314 | clk_enable(gpio_fck); |
56a25641 SMK |
1315 | |
1316 | /* | |
5492fb1a | 1317 | * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK |
56a25641 | 1318 | */ |
5492fb1a | 1319 | #if defined(CONFIG_ARCH_OMAP2430) |
56a25641 SMK |
1320 | if (cpu_is_omap2430()) { |
1321 | gpio5_ick = clk_get(NULL, "gpio5_ick"); | |
1322 | if (IS_ERR(gpio5_ick)) | |
1323 | printk("Could not get gpio5_ick\n"); | |
1324 | else | |
1325 | clk_enable(gpio5_ick); | |
1326 | gpio5_fck = clk_get(NULL, "gpio5_fck"); | |
1327 | if (IS_ERR(gpio5_fck)) | |
1328 | printk("Could not get gpio5_fck\n"); | |
1329 | else | |
1330 | clk_enable(gpio5_fck); | |
1331 | } | |
1332 | #endif | |
5492fb1a SMK |
1333 | } |
1334 | #endif | |
1335 | ||
1336 | #if defined(CONFIG_ARCH_OMAP3) | |
1337 | if (cpu_is_omap34xx()) { | |
1338 | for (i = 0; i < OMAP34XX_NR_GPIOS; i++) { | |
1339 | sprintf(clk_name, "gpio%d_ick", i + 1); | |
1340 | gpio_iclks[i] = clk_get(NULL, clk_name); | |
1341 | if (IS_ERR(gpio_iclks[i])) | |
1342 | printk(KERN_ERR "Could not get %s\n", clk_name); | |
1343 | else | |
1344 | clk_enable(gpio_iclks[i]); | |
5492fb1a SMK |
1345 | } |
1346 | } | |
1347 | #endif | |
1348 | ||
92105bb7 | 1349 | |
1a8bfa1e | 1350 | #ifdef CONFIG_ARCH_OMAP15XX |
6e60e79a | 1351 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
1352 | printk(KERN_INFO "OMAP1510 GPIO hardware\n"); |
1353 | gpio_bank_count = 2; | |
1354 | gpio_bank = gpio_bank_1510; | |
1355 | } | |
1356 | #endif | |
1357 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1358 | if (cpu_is_omap16xx()) { | |
92105bb7 | 1359 | u32 rev; |
5e1c5ff4 TL |
1360 | |
1361 | gpio_bank_count = 5; | |
1362 | gpio_bank = gpio_bank_1610; | |
7c7095aa | 1363 | rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); |
5e1c5ff4 TL |
1364 | printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", |
1365 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1366 | } | |
1367 | #endif | |
1368 | #ifdef CONFIG_ARCH_OMAP730 | |
1369 | if (cpu_is_omap730()) { | |
1370 | printk(KERN_INFO "OMAP730 GPIO hardware\n"); | |
1371 | gpio_bank_count = 7; | |
1372 | gpio_bank = gpio_bank_730; | |
1373 | } | |
92105bb7 | 1374 | #endif |
56a25641 | 1375 | |
92105bb7 | 1376 | #ifdef CONFIG_ARCH_OMAP24XX |
56a25641 | 1377 | if (cpu_is_omap242x()) { |
92105bb7 TL |
1378 | int rev; |
1379 | ||
1380 | gpio_bank_count = 4; | |
56a25641 | 1381 | gpio_bank = gpio_bank_242x; |
7c7095aa | 1382 | rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); |
56a25641 SMK |
1383 | printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n", |
1384 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1385 | } | |
1386 | if (cpu_is_omap243x()) { | |
1387 | int rev; | |
1388 | ||
1389 | gpio_bank_count = 5; | |
1390 | gpio_bank = gpio_bank_243x; | |
7c7095aa | 1391 | rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); |
56a25641 | 1392 | printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n", |
92105bb7 TL |
1393 | (rev >> 4) & 0x0f, rev & 0x0f); |
1394 | } | |
5492fb1a SMK |
1395 | #endif |
1396 | #ifdef CONFIG_ARCH_OMAP34XX | |
1397 | if (cpu_is_omap34xx()) { | |
1398 | int rev; | |
1399 | ||
1400 | gpio_bank_count = OMAP34XX_NR_GPIOS; | |
1401 | gpio_bank = gpio_bank_34xx; | |
7c7095aa | 1402 | rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); |
5492fb1a SMK |
1403 | printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n", |
1404 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1405 | } | |
5e1c5ff4 TL |
1406 | #endif |
1407 | for (i = 0; i < gpio_bank_count; i++) { | |
1408 | int j, gpio_count = 16; | |
1409 | ||
1410 | bank = &gpio_bank[i]; | |
5e1c5ff4 | 1411 | spin_lock_init(&bank->lock); |
e5c56ed3 | 1412 | if (bank_is_mpuio(bank)) |
7c7095aa | 1413 | __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT); |
d11ac979 | 1414 | if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { |
5e1c5ff4 TL |
1415 | __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); |
1416 | __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); | |
1417 | } | |
d11ac979 | 1418 | if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { |
5e1c5ff4 TL |
1419 | __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1); |
1420 | __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); | |
92105bb7 | 1421 | __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); |
5e1c5ff4 | 1422 | } |
d11ac979 | 1423 | if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) { |
5e1c5ff4 TL |
1424 | __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); |
1425 | __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); | |
1426 | ||
1427 | gpio_count = 32; /* 730 has 32-bit GPIOs */ | |
1428 | } | |
d11ac979 | 1429 | |
5492fb1a | 1430 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 | 1431 | if (bank->method == METHOD_GPIO_24XX) { |
3ac4fa99 JY |
1432 | static const u32 non_wakeup_gpios[] = { |
1433 | 0xe203ffc0, 0x08700040 | |
1434 | }; | |
1435 | ||
92105bb7 TL |
1436 | __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1); |
1437 | __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1); | |
14f1c3bf JY |
1438 | __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG); |
1439 | ||
1440 | /* Initialize interface clock ungated, module enabled */ | |
1441 | __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); | |
3ac4fa99 JY |
1442 | if (i < ARRAY_SIZE(non_wakeup_gpios)) |
1443 | bank->non_wakeup_gpios = non_wakeup_gpios[i]; | |
92105bb7 TL |
1444 | gpio_count = 32; |
1445 | } | |
5e1c5ff4 | 1446 | #endif |
52e31344 DB |
1447 | |
1448 | /* REVISIT eventually switch from OMAP-specific gpio structs | |
1449 | * over to the generic ones | |
1450 | */ | |
3ff164e1 JN |
1451 | bank->chip.request = omap_gpio_request; |
1452 | bank->chip.free = omap_gpio_free; | |
52e31344 DB |
1453 | bank->chip.direction_input = gpio_input; |
1454 | bank->chip.get = gpio_get; | |
1455 | bank->chip.direction_output = gpio_output; | |
1456 | bank->chip.set = gpio_set; | |
a007b709 | 1457 | bank->chip.to_irq = gpio_2irq; |
52e31344 DB |
1458 | if (bank_is_mpuio(bank)) { |
1459 | bank->chip.label = "mpuio"; | |
69114a47 | 1460 | #ifdef CONFIG_ARCH_OMAP16XX |
d8f388d8 DB |
1461 | bank->chip.dev = &omap_mpuio_device.dev; |
1462 | #endif | |
52e31344 DB |
1463 | bank->chip.base = OMAP_MPUIO(0); |
1464 | } else { | |
1465 | bank->chip.label = "gpio"; | |
1466 | bank->chip.base = gpio; | |
1467 | gpio += gpio_count; | |
1468 | } | |
1469 | bank->chip.ngpio = gpio_count; | |
1470 | ||
1471 | gpiochip_add(&bank->chip); | |
1472 | ||
5e1c5ff4 TL |
1473 | for (j = bank->virtual_irq_start; |
1474 | j < bank->virtual_irq_start + gpio_count; j++) { | |
8ba55c5c | 1475 | lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); |
58781016 | 1476 | set_irq_chip_data(j, bank); |
e5c56ed3 | 1477 | if (bank_is_mpuio(bank)) |
5e1c5ff4 TL |
1478 | set_irq_chip(j, &mpuio_irq_chip); |
1479 | else | |
1480 | set_irq_chip(j, &gpio_irq_chip); | |
10dd5ce2 | 1481 | set_irq_handler(j, handle_simple_irq); |
5e1c5ff4 TL |
1482 | set_irq_flags(j, IRQF_VALID); |
1483 | } | |
1484 | set_irq_chained_handler(bank->irq, gpio_irq_handler); | |
1485 | set_irq_data(bank->irq, bank); | |
89db9482 JH |
1486 | |
1487 | if (cpu_is_omap34xx()) { | |
1488 | sprintf(clk_name, "gpio%d_dbck", i + 1); | |
1489 | bank->dbck = clk_get(NULL, clk_name); | |
1490 | if (IS_ERR(bank->dbck)) | |
1491 | printk(KERN_ERR "Could not get %s\n", clk_name); | |
1492 | } | |
5e1c5ff4 TL |
1493 | } |
1494 | ||
1495 | /* Enable system clock for GPIO module. | |
1496 | * The CAM_CLK_CTRL *is* really the right place. */ | |
92105bb7 | 1497 | if (cpu_is_omap16xx()) |
5e1c5ff4 TL |
1498 | omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL); |
1499 | ||
14f1c3bf JY |
1500 | /* Enable autoidle for the OCP interface */ |
1501 | if (cpu_is_omap24xx()) | |
1502 | omap_writel(1 << 0, 0x48019010); | |
5492fb1a SMK |
1503 | if (cpu_is_omap34xx()) |
1504 | omap_writel(1 << 0, 0x48306814); | |
d11ac979 | 1505 | |
5e1c5ff4 TL |
1506 | return 0; |
1507 | } | |
1508 | ||
5492fb1a | 1509 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
1510 | static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) |
1511 | { | |
1512 | int i; | |
1513 | ||
5492fb1a | 1514 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
1515 | return 0; |
1516 | ||
1517 | for (i = 0; i < gpio_bank_count; i++) { | |
1518 | struct gpio_bank *bank = &gpio_bank[i]; | |
1519 | void __iomem *wake_status; | |
1520 | void __iomem *wake_clear; | |
1521 | void __iomem *wake_set; | |
a6472533 | 1522 | unsigned long flags; |
92105bb7 TL |
1523 | |
1524 | switch (bank->method) { | |
e5c56ed3 | 1525 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1526 | case METHOD_GPIO_1610: |
1527 | wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; | |
1528 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1529 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1530 | break; | |
e5c56ed3 | 1531 | #endif |
5492fb1a | 1532 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 | 1533 | case METHOD_GPIO_24XX: |
723fdb78 | 1534 | wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; |
92105bb7 TL |
1535 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1536 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
1537 | break; | |
e5c56ed3 | 1538 | #endif |
92105bb7 TL |
1539 | default: |
1540 | continue; | |
1541 | } | |
1542 | ||
a6472533 | 1543 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1544 | bank->saved_wakeup = __raw_readl(wake_status); |
1545 | __raw_writel(0xffffffff, wake_clear); | |
1546 | __raw_writel(bank->suspend_wakeup, wake_set); | |
a6472533 | 1547 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
1548 | } |
1549 | ||
1550 | return 0; | |
1551 | } | |
1552 | ||
1553 | static int omap_gpio_resume(struct sys_device *dev) | |
1554 | { | |
1555 | int i; | |
1556 | ||
723fdb78 | 1557 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
1558 | return 0; |
1559 | ||
1560 | for (i = 0; i < gpio_bank_count; i++) { | |
1561 | struct gpio_bank *bank = &gpio_bank[i]; | |
1562 | void __iomem *wake_clear; | |
1563 | void __iomem *wake_set; | |
a6472533 | 1564 | unsigned long flags; |
92105bb7 TL |
1565 | |
1566 | switch (bank->method) { | |
e5c56ed3 | 1567 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1568 | case METHOD_GPIO_1610: |
1569 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1570 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1571 | break; | |
e5c56ed3 | 1572 | #endif |
5492fb1a | 1573 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 | 1574 | case METHOD_GPIO_24XX: |
0d9356cb TL |
1575 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1576 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
92105bb7 | 1577 | break; |
e5c56ed3 | 1578 | #endif |
92105bb7 TL |
1579 | default: |
1580 | continue; | |
1581 | } | |
1582 | ||
a6472533 | 1583 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1584 | __raw_writel(0xffffffff, wake_clear); |
1585 | __raw_writel(bank->saved_wakeup, wake_set); | |
a6472533 | 1586 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
1587 | } |
1588 | ||
1589 | return 0; | |
1590 | } | |
1591 | ||
1592 | static struct sysdev_class omap_gpio_sysclass = { | |
af5ca3f4 | 1593 | .name = "gpio", |
92105bb7 TL |
1594 | .suspend = omap_gpio_suspend, |
1595 | .resume = omap_gpio_resume, | |
1596 | }; | |
1597 | ||
1598 | static struct sys_device omap_gpio_device = { | |
1599 | .id = 0, | |
1600 | .cls = &omap_gpio_sysclass, | |
1601 | }; | |
3ac4fa99 JY |
1602 | |
1603 | #endif | |
1604 | ||
5492fb1a | 1605 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1606 | |
1607 | static int workaround_enabled; | |
1608 | ||
1609 | void omap2_gpio_prepare_for_retention(void) | |
1610 | { | |
1611 | int i, c = 0; | |
1612 | ||
1613 | /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious | |
1614 | * IRQs will be generated. See OMAP2420 Errata item 1.101. */ | |
1615 | for (i = 0; i < gpio_bank_count; i++) { | |
1616 | struct gpio_bank *bank = &gpio_bank[i]; | |
1617 | u32 l1, l2; | |
1618 | ||
1619 | if (!(bank->enabled_non_wakeup_gpios)) | |
1620 | continue; | |
5492fb1a | 1621 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1622 | bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
1623 | l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1624 | l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
5492fb1a | 1625 | #endif |
3ac4fa99 JY |
1626 | bank->saved_fallingdetect = l1; |
1627 | bank->saved_risingdetect = l2; | |
1628 | l1 &= ~bank->enabled_non_wakeup_gpios; | |
1629 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
5492fb1a | 1630 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1631 | __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT); |
1632 | __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
5492fb1a | 1633 | #endif |
3ac4fa99 JY |
1634 | c++; |
1635 | } | |
1636 | if (!c) { | |
1637 | workaround_enabled = 0; | |
1638 | return; | |
1639 | } | |
1640 | workaround_enabled = 1; | |
1641 | } | |
1642 | ||
1643 | void omap2_gpio_resume_after_retention(void) | |
1644 | { | |
1645 | int i; | |
1646 | ||
1647 | if (!workaround_enabled) | |
1648 | return; | |
1649 | for (i = 0; i < gpio_bank_count; i++) { | |
1650 | struct gpio_bank *bank = &gpio_bank[i]; | |
1651 | u32 l; | |
1652 | ||
1653 | if (!(bank->enabled_non_wakeup_gpios)) | |
1654 | continue; | |
5492fb1a | 1655 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1656 | __raw_writel(bank->saved_fallingdetect, |
1657 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1658 | __raw_writel(bank->saved_risingdetect, | |
1659 | bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
5492fb1a | 1660 | #endif |
3ac4fa99 JY |
1661 | /* Check if any of the non-wakeup interrupt GPIOs have changed |
1662 | * state. If so, generate an IRQ by software. This is | |
1663 | * horribly racy, but it's the best we can do to work around | |
1664 | * this silicon bug. */ | |
5492fb1a | 1665 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 | 1666 | l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
5492fb1a | 1667 | #endif |
3ac4fa99 JY |
1668 | l ^= bank->saved_datain; |
1669 | l &= bank->non_wakeup_gpios; | |
1670 | if (l) { | |
1671 | u32 old0, old1; | |
5492fb1a | 1672 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1673 | old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); |
1674 | old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
1675 | __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
1676 | __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
1677 | __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
1678 | __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
5492fb1a | 1679 | #endif |
3ac4fa99 JY |
1680 | } |
1681 | } | |
1682 | ||
1683 | } | |
1684 | ||
92105bb7 TL |
1685 | #endif |
1686 | ||
5e1c5ff4 TL |
1687 | /* |
1688 | * This may get called early from board specific init | |
1a8bfa1e | 1689 | * for boards that have interrupts routed via FPGA. |
5e1c5ff4 | 1690 | */ |
277d58ef | 1691 | int __init omap_gpio_init(void) |
5e1c5ff4 TL |
1692 | { |
1693 | if (!initialized) | |
1694 | return _omap_gpio_init(); | |
1695 | else | |
1696 | return 0; | |
1697 | } | |
1698 | ||
92105bb7 TL |
1699 | static int __init omap_gpio_sysinit(void) |
1700 | { | |
1701 | int ret = 0; | |
1702 | ||
1703 | if (!initialized) | |
1704 | ret = _omap_gpio_init(); | |
1705 | ||
11a78b79 DB |
1706 | mpuio_init(); |
1707 | ||
5492fb1a SMK |
1708 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
1709 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) { | |
92105bb7 TL |
1710 | if (ret == 0) { |
1711 | ret = sysdev_class_register(&omap_gpio_sysclass); | |
1712 | if (ret == 0) | |
1713 | ret = sysdev_register(&omap_gpio_device); | |
1714 | } | |
1715 | } | |
1716 | #endif | |
1717 | ||
1718 | return ret; | |
1719 | } | |
1720 | ||
92105bb7 | 1721 | arch_initcall(omap_gpio_sysinit); |
b9772a22 DB |
1722 | |
1723 | ||
1724 | #ifdef CONFIG_DEBUG_FS | |
1725 | ||
1726 | #include <linux/debugfs.h> | |
1727 | #include <linux/seq_file.h> | |
1728 | ||
1729 | static int gpio_is_input(struct gpio_bank *bank, int mask) | |
1730 | { | |
1731 | void __iomem *reg = bank->base; | |
1732 | ||
1733 | switch (bank->method) { | |
1734 | case METHOD_MPUIO: | |
1735 | reg += OMAP_MPUIO_IO_CNTL; | |
1736 | break; | |
1737 | case METHOD_GPIO_1510: | |
1738 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
1739 | break; | |
1740 | case METHOD_GPIO_1610: | |
1741 | reg += OMAP1610_GPIO_DIRECTION; | |
1742 | break; | |
1743 | case METHOD_GPIO_730: | |
1744 | reg += OMAP730_GPIO_DIR_CONTROL; | |
1745 | break; | |
1746 | case METHOD_GPIO_24XX: | |
1747 | reg += OMAP24XX_GPIO_OE; | |
1748 | break; | |
1749 | } | |
1750 | return __raw_readl(reg) & mask; | |
1751 | } | |
1752 | ||
1753 | ||
1754 | static int dbg_gpio_show(struct seq_file *s, void *unused) | |
1755 | { | |
1756 | unsigned i, j, gpio; | |
1757 | ||
1758 | for (i = 0, gpio = 0; i < gpio_bank_count; i++) { | |
1759 | struct gpio_bank *bank = gpio_bank + i; | |
1760 | unsigned bankwidth = 16; | |
1761 | u32 mask = 1; | |
1762 | ||
e5c56ed3 | 1763 | if (bank_is_mpuio(bank)) |
b9772a22 | 1764 | gpio = OMAP_MPUIO(0); |
5492fb1a | 1765 | else if (cpu_class_is_omap2() || cpu_is_omap730()) |
b9772a22 DB |
1766 | bankwidth = 32; |
1767 | ||
1768 | for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { | |
1769 | unsigned irq, value, is_in, irqstat; | |
52e31344 | 1770 | const char *label; |
b9772a22 | 1771 | |
52e31344 DB |
1772 | label = gpiochip_is_requested(&bank->chip, j); |
1773 | if (!label) | |
b9772a22 DB |
1774 | continue; |
1775 | ||
1776 | irq = bank->virtual_irq_start + j; | |
0b84b5ca | 1777 | value = gpio_get_value(gpio); |
b9772a22 DB |
1778 | is_in = gpio_is_input(bank, mask); |
1779 | ||
e5c56ed3 | 1780 | if (bank_is_mpuio(bank)) |
52e31344 | 1781 | seq_printf(s, "MPUIO %2d ", j); |
b9772a22 | 1782 | else |
52e31344 | 1783 | seq_printf(s, "GPIO %3d ", gpio); |
21c867f1 | 1784 | seq_printf(s, "(%-20.20s): %s %s", |
52e31344 | 1785 | label, |
b9772a22 DB |
1786 | is_in ? "in " : "out", |
1787 | value ? "hi" : "lo"); | |
1788 | ||
52e31344 DB |
1789 | /* FIXME for at least omap2, show pullup/pulldown state */ |
1790 | ||
b9772a22 DB |
1791 | irqstat = irq_desc[irq].status; |
1792 | if (is_in && ((bank->suspend_wakeup & mask) | |
1793 | || irqstat & IRQ_TYPE_SENSE_MASK)) { | |
1794 | char *trigger = NULL; | |
1795 | ||
1796 | switch (irqstat & IRQ_TYPE_SENSE_MASK) { | |
1797 | case IRQ_TYPE_EDGE_FALLING: | |
1798 | trigger = "falling"; | |
1799 | break; | |
1800 | case IRQ_TYPE_EDGE_RISING: | |
1801 | trigger = "rising"; | |
1802 | break; | |
1803 | case IRQ_TYPE_EDGE_BOTH: | |
1804 | trigger = "bothedge"; | |
1805 | break; | |
1806 | case IRQ_TYPE_LEVEL_LOW: | |
1807 | trigger = "low"; | |
1808 | break; | |
1809 | case IRQ_TYPE_LEVEL_HIGH: | |
1810 | trigger = "high"; | |
1811 | break; | |
1812 | case IRQ_TYPE_NONE: | |
52e31344 | 1813 | trigger = "(?)"; |
b9772a22 DB |
1814 | break; |
1815 | } | |
52e31344 | 1816 | seq_printf(s, ", irq-%d %-8s%s", |
b9772a22 DB |
1817 | irq, trigger, |
1818 | (bank->suspend_wakeup & mask) | |
1819 | ? " wakeup" : ""); | |
1820 | } | |
1821 | seq_printf(s, "\n"); | |
1822 | } | |
1823 | ||
e5c56ed3 | 1824 | if (bank_is_mpuio(bank)) { |
b9772a22 DB |
1825 | seq_printf(s, "\n"); |
1826 | gpio = 0; | |
1827 | } | |
1828 | } | |
1829 | return 0; | |
1830 | } | |
1831 | ||
1832 | static int dbg_gpio_open(struct inode *inode, struct file *file) | |
1833 | { | |
e5c56ed3 | 1834 | return single_open(file, dbg_gpio_show, &inode->i_private); |
b9772a22 DB |
1835 | } |
1836 | ||
1837 | static const struct file_operations debug_fops = { | |
1838 | .open = dbg_gpio_open, | |
1839 | .read = seq_read, | |
1840 | .llseek = seq_lseek, | |
1841 | .release = single_release, | |
1842 | }; | |
1843 | ||
1844 | static int __init omap_gpio_debuginit(void) | |
1845 | { | |
e5c56ed3 DB |
1846 | (void) debugfs_create_file("omap_gpio", S_IRUGO, |
1847 | NULL, NULL, &debug_fops); | |
b9772a22 DB |
1848 | return 0; |
1849 | } | |
1850 | late_initcall(omap_gpio_debuginit); | |
1851 | #endif |