Commit | Line | Data |
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5e1c5ff4 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/gpio.c | |
3 | * | |
4 | * Support functions for OMAP GPIO | |
5 | * | |
92105bb7 | 6 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 7 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 | 8 | * |
44169075 SS |
9 | * Copyright (C) 2009 Texas Instruments |
10 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
11 | * | |
5e1c5ff4 TL |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
5e1c5ff4 TL |
17 | #include <linux/init.h> |
18 | #include <linux/module.h> | |
5e1c5ff4 | 19 | #include <linux/interrupt.h> |
92105bb7 TL |
20 | #include <linux/sysdev.h> |
21 | #include <linux/err.h> | |
f8ce2547 | 22 | #include <linux/clk.h> |
fced80c7 | 23 | #include <linux/io.h> |
5e1c5ff4 | 24 | |
a09e64fb | 25 | #include <mach/hardware.h> |
5e1c5ff4 | 26 | #include <asm/irq.h> |
a09e64fb RK |
27 | #include <mach/irqs.h> |
28 | #include <mach/gpio.h> | |
5e1c5ff4 TL |
29 | #include <asm/mach/irq.h> |
30 | ||
5e1c5ff4 TL |
31 | /* |
32 | * OMAP1510 GPIO registers | |
33 | */ | |
7c7095aa | 34 | #define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000) |
5e1c5ff4 TL |
35 | #define OMAP1510_GPIO_DATA_INPUT 0x00 |
36 | #define OMAP1510_GPIO_DATA_OUTPUT 0x04 | |
37 | #define OMAP1510_GPIO_DIR_CONTROL 0x08 | |
38 | #define OMAP1510_GPIO_INT_CONTROL 0x0c | |
39 | #define OMAP1510_GPIO_INT_MASK 0x10 | |
40 | #define OMAP1510_GPIO_INT_STATUS 0x14 | |
41 | #define OMAP1510_GPIO_PIN_CONTROL 0x18 | |
42 | ||
43 | #define OMAP1510_IH_GPIO_BASE 64 | |
44 | ||
45 | /* | |
46 | * OMAP1610 specific GPIO registers | |
47 | */ | |
7c7095aa RK |
48 | #define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400) |
49 | #define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00) | |
50 | #define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400) | |
51 | #define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00) | |
5e1c5ff4 TL |
52 | #define OMAP1610_GPIO_REVISION 0x0000 |
53 | #define OMAP1610_GPIO_SYSCONFIG 0x0010 | |
54 | #define OMAP1610_GPIO_SYSSTATUS 0x0014 | |
55 | #define OMAP1610_GPIO_IRQSTATUS1 0x0018 | |
56 | #define OMAP1610_GPIO_IRQENABLE1 0x001c | |
92105bb7 | 57 | #define OMAP1610_GPIO_WAKEUPENABLE 0x0028 |
5e1c5ff4 TL |
58 | #define OMAP1610_GPIO_DATAIN 0x002c |
59 | #define OMAP1610_GPIO_DATAOUT 0x0030 | |
60 | #define OMAP1610_GPIO_DIRECTION 0x0034 | |
61 | #define OMAP1610_GPIO_EDGE_CTRL1 0x0038 | |
62 | #define OMAP1610_GPIO_EDGE_CTRL2 0x003c | |
63 | #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c | |
92105bb7 | 64 | #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8 |
5e1c5ff4 TL |
65 | #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0 |
66 | #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc | |
92105bb7 | 67 | #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8 |
5e1c5ff4 TL |
68 | #define OMAP1610_GPIO_SET_DATAOUT 0x00f0 |
69 | ||
70 | /* | |
71 | * OMAP730 specific GPIO registers | |
72 | */ | |
7c7095aa RK |
73 | #define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000) |
74 | #define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800) | |
75 | #define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000) | |
76 | #define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800) | |
77 | #define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000) | |
78 | #define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800) | |
5e1c5ff4 TL |
79 | #define OMAP730_GPIO_DATA_INPUT 0x00 |
80 | #define OMAP730_GPIO_DATA_OUTPUT 0x04 | |
81 | #define OMAP730_GPIO_DIR_CONTROL 0x08 | |
82 | #define OMAP730_GPIO_INT_CONTROL 0x0c | |
83 | #define OMAP730_GPIO_INT_MASK 0x10 | |
84 | #define OMAP730_GPIO_INT_STATUS 0x14 | |
85 | ||
56739a69 ZM |
86 | /* |
87 | * OMAP850 specific GPIO registers | |
88 | */ | |
89 | #define OMAP850_GPIO1_BASE IO_ADDRESS(0xfffbc000) | |
90 | #define OMAP850_GPIO2_BASE IO_ADDRESS(0xfffbc800) | |
91 | #define OMAP850_GPIO3_BASE IO_ADDRESS(0xfffbd000) | |
92 | #define OMAP850_GPIO4_BASE IO_ADDRESS(0xfffbd800) | |
93 | #define OMAP850_GPIO5_BASE IO_ADDRESS(0xfffbe000) | |
94 | #define OMAP850_GPIO6_BASE IO_ADDRESS(0xfffbe800) | |
95 | #define OMAP850_GPIO_DATA_INPUT 0x00 | |
96 | #define OMAP850_GPIO_DATA_OUTPUT 0x04 | |
97 | #define OMAP850_GPIO_DIR_CONTROL 0x08 | |
98 | #define OMAP850_GPIO_INT_CONTROL 0x0c | |
99 | #define OMAP850_GPIO_INT_MASK 0x10 | |
100 | #define OMAP850_GPIO_INT_STATUS 0x14 | |
101 | ||
92105bb7 TL |
102 | /* |
103 | * omap24xx specific GPIO registers | |
104 | */ | |
7c7095aa RK |
105 | #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000) |
106 | #define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000) | |
107 | #define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000) | |
108 | #define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000) | |
56a25641 | 109 | |
7c7095aa RK |
110 | #define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000) |
111 | #define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000) | |
112 | #define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000) | |
113 | #define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000) | |
114 | #define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000) | |
56a25641 | 115 | |
92105bb7 TL |
116 | #define OMAP24XX_GPIO_REVISION 0x0000 |
117 | #define OMAP24XX_GPIO_SYSCONFIG 0x0010 | |
118 | #define OMAP24XX_GPIO_SYSSTATUS 0x0014 | |
119 | #define OMAP24XX_GPIO_IRQSTATUS1 0x0018 | |
bee7930f HD |
120 | #define OMAP24XX_GPIO_IRQSTATUS2 0x0028 |
121 | #define OMAP24XX_GPIO_IRQENABLE2 0x002c | |
92105bb7 | 122 | #define OMAP24XX_GPIO_IRQENABLE1 0x001c |
723fdb78 | 123 | #define OMAP24XX_GPIO_WAKE_EN 0x0020 |
92105bb7 TL |
124 | #define OMAP24XX_GPIO_CTRL 0x0030 |
125 | #define OMAP24XX_GPIO_OE 0x0034 | |
126 | #define OMAP24XX_GPIO_DATAIN 0x0038 | |
127 | #define OMAP24XX_GPIO_DATAOUT 0x003c | |
128 | #define OMAP24XX_GPIO_LEVELDETECT0 0x0040 | |
129 | #define OMAP24XX_GPIO_LEVELDETECT1 0x0044 | |
130 | #define OMAP24XX_GPIO_RISINGDETECT 0x0048 | |
131 | #define OMAP24XX_GPIO_FALLINGDETECT 0x004c | |
5eb3bb9c KH |
132 | #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 |
133 | #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 | |
92105bb7 TL |
134 | #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 |
135 | #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 | |
136 | #define OMAP24XX_GPIO_CLEARWKUENA 0x0080 | |
137 | #define OMAP24XX_GPIO_SETWKUENA 0x0084 | |
138 | #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 | |
139 | #define OMAP24XX_GPIO_SETDATAOUT 0x0094 | |
140 | ||
5492fb1a SMK |
141 | /* |
142 | * omap34xx specific GPIO registers | |
143 | */ | |
144 | ||
7c7095aa RK |
145 | #define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000) |
146 | #define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000) | |
147 | #define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000) | |
148 | #define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000) | |
149 | #define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000) | |
150 | #define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000) | |
5492fb1a | 151 | |
44169075 SS |
152 | /* |
153 | * OMAP44XX specific GPIO registers | |
154 | */ | |
155 | #define OMAP44XX_GPIO1_BASE IO_ADDRESS(0x4a310000) | |
156 | #define OMAP44XX_GPIO2_BASE IO_ADDRESS(0x48055000) | |
157 | #define OMAP44XX_GPIO3_BASE IO_ADDRESS(0x48057000) | |
158 | #define OMAP44XX_GPIO4_BASE IO_ADDRESS(0x48059000) | |
159 | #define OMAP44XX_GPIO5_BASE IO_ADDRESS(0x4805B000) | |
160 | #define OMAP44XX_GPIO6_BASE IO_ADDRESS(0x4805D000) | |
161 | ||
7c7095aa | 162 | #define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE) |
5492fb1a | 163 | |
5e1c5ff4 | 164 | struct gpio_bank { |
92105bb7 | 165 | void __iomem *base; |
5e1c5ff4 TL |
166 | u16 irq; |
167 | u16 virtual_irq_start; | |
92105bb7 | 168 | int method; |
44169075 SS |
169 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ |
170 | defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4) | |
92105bb7 TL |
171 | u32 suspend_wakeup; |
172 | u32 saved_wakeup; | |
3ac4fa99 | 173 | #endif |
44169075 SS |
174 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
175 | defined(CONFIG_ARCH_OMAP4) | |
3ac4fa99 JY |
176 | u32 non_wakeup_gpios; |
177 | u32 enabled_non_wakeup_gpios; | |
178 | ||
179 | u32 saved_datain; | |
180 | u32 saved_fallingdetect; | |
181 | u32 saved_risingdetect; | |
182 | #endif | |
b144ff6f | 183 | u32 level_mask; |
5e1c5ff4 | 184 | spinlock_t lock; |
52e31344 | 185 | struct gpio_chip chip; |
89db9482 | 186 | struct clk *dbck; |
5e1c5ff4 TL |
187 | }; |
188 | ||
189 | #define METHOD_MPUIO 0 | |
190 | #define METHOD_GPIO_1510 1 | |
191 | #define METHOD_GPIO_1610 2 | |
192 | #define METHOD_GPIO_730 3 | |
56739a69 ZM |
193 | #define METHOD_GPIO_850 4 |
194 | #define METHOD_GPIO_24XX 5 | |
5e1c5ff4 | 195 | |
92105bb7 | 196 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 197 | static struct gpio_bank gpio_bank_1610[5] = { |
7c7095aa | 198 | { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO}, |
5e1c5ff4 TL |
199 | { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 }, |
200 | { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 }, | |
201 | { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 }, | |
202 | { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 }, | |
203 | }; | |
204 | #endif | |
205 | ||
1a8bfa1e | 206 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 207 | static struct gpio_bank gpio_bank_1510[2] = { |
7c7095aa | 208 | { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, |
5e1c5ff4 TL |
209 | { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 } |
210 | }; | |
211 | #endif | |
212 | ||
213 | #ifdef CONFIG_ARCH_OMAP730 | |
214 | static struct gpio_bank gpio_bank_730[7] = { | |
7c7095aa | 215 | { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, |
5e1c5ff4 TL |
216 | { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 }, |
217 | { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 }, | |
218 | { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 }, | |
219 | { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 }, | |
220 | { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 }, | |
221 | { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 }, | |
222 | }; | |
223 | #endif | |
224 | ||
56739a69 ZM |
225 | #ifdef CONFIG_ARCH_OMAP850 |
226 | static struct gpio_bank gpio_bank_850[7] = { | |
227 | { OMAP_MPUIO_BASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, | |
228 | { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 }, | |
229 | { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 }, | |
230 | { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 }, | |
231 | { OMAP850_GPIO4_BASE, INT_850_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_850 }, | |
232 | { OMAP850_GPIO5_BASE, INT_850_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_850 }, | |
233 | { OMAP850_GPIO6_BASE, INT_850_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_850 }, | |
234 | }; | |
235 | #endif | |
236 | ||
237 | ||
92105bb7 | 238 | #ifdef CONFIG_ARCH_OMAP24XX |
56a25641 SMK |
239 | |
240 | static struct gpio_bank gpio_bank_242x[4] = { | |
241 | { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, | |
242 | { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, | |
243 | { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, | |
244 | { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, | |
92105bb7 | 245 | }; |
56a25641 SMK |
246 | |
247 | static struct gpio_bank gpio_bank_243x[5] = { | |
248 | { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, | |
249 | { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, | |
250 | { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, | |
251 | { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, | |
252 | { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX }, | |
253 | }; | |
254 | ||
92105bb7 TL |
255 | #endif |
256 | ||
5492fb1a SMK |
257 | #ifdef CONFIG_ARCH_OMAP34XX |
258 | static struct gpio_bank gpio_bank_34xx[6] = { | |
259 | { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, | |
260 | { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, | |
261 | { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, | |
262 | { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, | |
263 | { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX }, | |
264 | { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX }, | |
265 | }; | |
266 | ||
267 | #endif | |
268 | ||
44169075 SS |
269 | #ifdef CONFIG_ARCH_OMAP4 |
270 | static struct gpio_bank gpio_bank_44xx[6] = { | |
271 | { OMAP44XX_GPIO1_BASE, INT_44XX_GPIO_BANK1, IH_GPIO_BASE, \ | |
272 | METHOD_GPIO_24XX }, | |
273 | { OMAP44XX_GPIO2_BASE, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32, \ | |
274 | METHOD_GPIO_24XX }, | |
275 | { OMAP44XX_GPIO3_BASE, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64, \ | |
276 | METHOD_GPIO_24XX }, | |
277 | { OMAP44XX_GPIO4_BASE, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96, \ | |
278 | METHOD_GPIO_24XX }, | |
279 | { OMAP44XX_GPIO5_BASE, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, \ | |
280 | METHOD_GPIO_24XX }, | |
281 | { OMAP44XX_GPIO6_BASE, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, \ | |
282 | METHOD_GPIO_24XX }, | |
283 | }; | |
284 | ||
285 | #endif | |
286 | ||
5e1c5ff4 TL |
287 | static struct gpio_bank *gpio_bank; |
288 | static int gpio_bank_count; | |
289 | ||
290 | static inline struct gpio_bank *get_gpio_bank(int gpio) | |
291 | { | |
6e60e79a | 292 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
293 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
294 | return &gpio_bank[0]; | |
295 | return &gpio_bank[1]; | |
296 | } | |
5e1c5ff4 TL |
297 | if (cpu_is_omap16xx()) { |
298 | if (OMAP_GPIO_IS_MPUIO(gpio)) | |
299 | return &gpio_bank[0]; | |
300 | return &gpio_bank[1 + (gpio >> 4)]; | |
301 | } | |
56739a69 | 302 | if (cpu_is_omap7xx()) { |
5e1c5ff4 TL |
303 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
304 | return &gpio_bank[0]; | |
305 | return &gpio_bank[1 + (gpio >> 5)]; | |
306 | } | |
92105bb7 TL |
307 | if (cpu_is_omap24xx()) |
308 | return &gpio_bank[gpio >> 5]; | |
44169075 | 309 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) |
5492fb1a | 310 | return &gpio_bank[gpio >> 5]; |
e031ab23 DB |
311 | BUG(); |
312 | return NULL; | |
5e1c5ff4 TL |
313 | } |
314 | ||
315 | static inline int get_gpio_index(int gpio) | |
316 | { | |
56739a69 | 317 | if (cpu_is_omap7xx()) |
5e1c5ff4 | 318 | return gpio & 0x1f; |
92105bb7 TL |
319 | if (cpu_is_omap24xx()) |
320 | return gpio & 0x1f; | |
44169075 | 321 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) |
5492fb1a | 322 | return gpio & 0x1f; |
92105bb7 | 323 | return gpio & 0x0f; |
5e1c5ff4 TL |
324 | } |
325 | ||
326 | static inline int gpio_valid(int gpio) | |
327 | { | |
328 | if (gpio < 0) | |
329 | return -1; | |
d11ac979 | 330 | if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) { |
193e68be | 331 | if (gpio >= OMAP_MAX_GPIO_LINES + 16) |
5e1c5ff4 TL |
332 | return -1; |
333 | return 0; | |
334 | } | |
6e60e79a | 335 | if (cpu_is_omap15xx() && gpio < 16) |
5e1c5ff4 | 336 | return 0; |
5e1c5ff4 TL |
337 | if ((cpu_is_omap16xx()) && gpio < 64) |
338 | return 0; | |
56739a69 | 339 | if (cpu_is_omap7xx() && gpio < 192) |
5e1c5ff4 | 340 | return 0; |
92105bb7 TL |
341 | if (cpu_is_omap24xx() && gpio < 128) |
342 | return 0; | |
44169075 | 343 | if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192) |
5492fb1a | 344 | return 0; |
5e1c5ff4 TL |
345 | return -1; |
346 | } | |
347 | ||
348 | static int check_gpio(int gpio) | |
349 | { | |
350 | if (unlikely(gpio_valid(gpio)) < 0) { | |
351 | printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio); | |
352 | dump_stack(); | |
353 | return -1; | |
354 | } | |
355 | return 0; | |
356 | } | |
357 | ||
358 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |
359 | { | |
92105bb7 | 360 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
361 | u32 l; |
362 | ||
363 | switch (bank->method) { | |
e5c56ed3 | 364 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
365 | case METHOD_MPUIO: |
366 | reg += OMAP_MPUIO_IO_CNTL; | |
367 | break; | |
e5c56ed3 DB |
368 | #endif |
369 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
370 | case METHOD_GPIO_1510: |
371 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
372 | break; | |
e5c56ed3 DB |
373 | #endif |
374 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
375 | case METHOD_GPIO_1610: |
376 | reg += OMAP1610_GPIO_DIRECTION; | |
377 | break; | |
e5c56ed3 DB |
378 | #endif |
379 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
380 | case METHOD_GPIO_730: |
381 | reg += OMAP730_GPIO_DIR_CONTROL; | |
382 | break; | |
e5c56ed3 | 383 | #endif |
56739a69 ZM |
384 | #ifdef CONFIG_ARCH_OMAP850 |
385 | case METHOD_GPIO_850: | |
386 | reg += OMAP850_GPIO_DIR_CONTROL; | |
387 | break; | |
388 | #endif | |
44169075 SS |
389 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
390 | defined(CONFIG_ARCH_OMAP4) | |
92105bb7 TL |
391 | case METHOD_GPIO_24XX: |
392 | reg += OMAP24XX_GPIO_OE; | |
393 | break; | |
e5c56ed3 DB |
394 | #endif |
395 | default: | |
396 | WARN_ON(1); | |
397 | return; | |
5e1c5ff4 TL |
398 | } |
399 | l = __raw_readl(reg); | |
400 | if (is_input) | |
401 | l |= 1 << gpio; | |
402 | else | |
403 | l &= ~(1 << gpio); | |
404 | __raw_writel(l, reg); | |
405 | } | |
406 | ||
5e1c5ff4 TL |
407 | static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) |
408 | { | |
92105bb7 | 409 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
410 | u32 l = 0; |
411 | ||
412 | switch (bank->method) { | |
e5c56ed3 | 413 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
414 | case METHOD_MPUIO: |
415 | reg += OMAP_MPUIO_OUTPUT; | |
416 | l = __raw_readl(reg); | |
417 | if (enable) | |
418 | l |= 1 << gpio; | |
419 | else | |
420 | l &= ~(1 << gpio); | |
421 | break; | |
e5c56ed3 DB |
422 | #endif |
423 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
424 | case METHOD_GPIO_1510: |
425 | reg += OMAP1510_GPIO_DATA_OUTPUT; | |
426 | l = __raw_readl(reg); | |
427 | if (enable) | |
428 | l |= 1 << gpio; | |
429 | else | |
430 | l &= ~(1 << gpio); | |
431 | break; | |
e5c56ed3 DB |
432 | #endif |
433 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
434 | case METHOD_GPIO_1610: |
435 | if (enable) | |
436 | reg += OMAP1610_GPIO_SET_DATAOUT; | |
437 | else | |
438 | reg += OMAP1610_GPIO_CLEAR_DATAOUT; | |
439 | l = 1 << gpio; | |
440 | break; | |
e5c56ed3 DB |
441 | #endif |
442 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
443 | case METHOD_GPIO_730: |
444 | reg += OMAP730_GPIO_DATA_OUTPUT; | |
445 | l = __raw_readl(reg); | |
446 | if (enable) | |
447 | l |= 1 << gpio; | |
448 | else | |
449 | l &= ~(1 << gpio); | |
450 | break; | |
e5c56ed3 | 451 | #endif |
56739a69 ZM |
452 | #ifdef CONFIG_ARCH_OMAP850 |
453 | case METHOD_GPIO_850: | |
454 | reg += OMAP850_GPIO_DATA_OUTPUT; | |
455 | l = __raw_readl(reg); | |
456 | if (enable) | |
457 | l |= 1 << gpio; | |
458 | else | |
459 | l &= ~(1 << gpio); | |
460 | break; | |
461 | #endif | |
44169075 SS |
462 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
463 | defined(CONFIG_ARCH_OMAP4) | |
92105bb7 TL |
464 | case METHOD_GPIO_24XX: |
465 | if (enable) | |
466 | reg += OMAP24XX_GPIO_SETDATAOUT; | |
467 | else | |
468 | reg += OMAP24XX_GPIO_CLEARDATAOUT; | |
469 | l = 1 << gpio; | |
470 | break; | |
e5c56ed3 | 471 | #endif |
5e1c5ff4 | 472 | default: |
e5c56ed3 | 473 | WARN_ON(1); |
5e1c5ff4 TL |
474 | return; |
475 | } | |
476 | __raw_writel(l, reg); | |
477 | } | |
478 | ||
b37c45b8 | 479 | static int _get_gpio_datain(struct gpio_bank *bank, int gpio) |
5e1c5ff4 | 480 | { |
92105bb7 | 481 | void __iomem *reg; |
5e1c5ff4 TL |
482 | |
483 | if (check_gpio(gpio) < 0) | |
e5c56ed3 | 484 | return -EINVAL; |
5e1c5ff4 TL |
485 | reg = bank->base; |
486 | switch (bank->method) { | |
e5c56ed3 | 487 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
488 | case METHOD_MPUIO: |
489 | reg += OMAP_MPUIO_INPUT_LATCH; | |
490 | break; | |
e5c56ed3 DB |
491 | #endif |
492 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
493 | case METHOD_GPIO_1510: |
494 | reg += OMAP1510_GPIO_DATA_INPUT; | |
495 | break; | |
e5c56ed3 DB |
496 | #endif |
497 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
498 | case METHOD_GPIO_1610: |
499 | reg += OMAP1610_GPIO_DATAIN; | |
500 | break; | |
e5c56ed3 DB |
501 | #endif |
502 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
503 | case METHOD_GPIO_730: |
504 | reg += OMAP730_GPIO_DATA_INPUT; | |
505 | break; | |
e5c56ed3 | 506 | #endif |
56739a69 ZM |
507 | #ifdef CONFIG_ARCH_OMAP850 |
508 | case METHOD_GPIO_850: | |
509 | reg += OMAP850_GPIO_DATA_INPUT; | |
510 | break; | |
511 | #endif | |
44169075 SS |
512 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
513 | defined(CONFIG_ARCH_OMAP4) | |
92105bb7 TL |
514 | case METHOD_GPIO_24XX: |
515 | reg += OMAP24XX_GPIO_DATAIN; | |
516 | break; | |
e5c56ed3 | 517 | #endif |
5e1c5ff4 | 518 | default: |
e5c56ed3 | 519 | return -EINVAL; |
5e1c5ff4 | 520 | } |
92105bb7 TL |
521 | return (__raw_readl(reg) |
522 | & (1 << get_gpio_index(gpio))) != 0; | |
5e1c5ff4 TL |
523 | } |
524 | ||
b37c45b8 RQ |
525 | static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) |
526 | { | |
527 | void __iomem *reg; | |
528 | ||
529 | if (check_gpio(gpio) < 0) | |
530 | return -EINVAL; | |
531 | reg = bank->base; | |
532 | ||
533 | switch (bank->method) { | |
534 | #ifdef CONFIG_ARCH_OMAP1 | |
535 | case METHOD_MPUIO: | |
536 | reg += OMAP_MPUIO_OUTPUT; | |
537 | break; | |
538 | #endif | |
539 | #ifdef CONFIG_ARCH_OMAP15XX | |
540 | case METHOD_GPIO_1510: | |
541 | reg += OMAP1510_GPIO_DATA_OUTPUT; | |
542 | break; | |
543 | #endif | |
544 | #ifdef CONFIG_ARCH_OMAP16XX | |
545 | case METHOD_GPIO_1610: | |
546 | reg += OMAP1610_GPIO_DATAOUT; | |
547 | break; | |
548 | #endif | |
549 | #ifdef CONFIG_ARCH_OMAP730 | |
550 | case METHOD_GPIO_730: | |
551 | reg += OMAP730_GPIO_DATA_OUTPUT; | |
552 | break; | |
553 | #endif | |
554 | #ifdef CONFIG_ARCH_OMAP850 | |
555 | case METHOD_GPIO_850: | |
556 | reg += OMAP850_GPIO_DATA_OUTPUT; | |
557 | break; | |
558 | #endif | |
559 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ | |
560 | defined(CONFIG_ARCH_OMAP4) | |
561 | case METHOD_GPIO_24XX: | |
562 | reg += OMAP24XX_GPIO_DATAOUT; | |
563 | break; | |
564 | #endif | |
565 | default: | |
566 | return -EINVAL; | |
567 | } | |
568 | ||
569 | return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0; | |
570 | } | |
571 | ||
92105bb7 TL |
572 | #define MOD_REG_BIT(reg, bit_mask, set) \ |
573 | do { \ | |
574 | int l = __raw_readl(base + reg); \ | |
575 | if (set) l |= bit_mask; \ | |
576 | else l &= ~bit_mask; \ | |
577 | __raw_writel(l, base + reg); \ | |
578 | } while(0) | |
579 | ||
5eb3bb9c KH |
580 | void omap_set_gpio_debounce(int gpio, int enable) |
581 | { | |
582 | struct gpio_bank *bank; | |
583 | void __iomem *reg; | |
e031ab23 | 584 | unsigned long flags; |
5eb3bb9c KH |
585 | u32 val, l = 1 << get_gpio_index(gpio); |
586 | ||
587 | if (cpu_class_is_omap1()) | |
588 | return; | |
589 | ||
590 | bank = get_gpio_bank(gpio); | |
591 | reg = bank->base; | |
5eb3bb9c | 592 | reg += OMAP24XX_GPIO_DEBOUNCE_EN; |
e031ab23 DB |
593 | |
594 | spin_lock_irqsave(&bank->lock, flags); | |
5eb3bb9c KH |
595 | val = __raw_readl(reg); |
596 | ||
89db9482 | 597 | if (enable && !(val & l)) |
5eb3bb9c | 598 | val |= l; |
e031ab23 | 599 | else if (!enable && (val & l)) |
5eb3bb9c | 600 | val &= ~l; |
89db9482 | 601 | else |
e031ab23 | 602 | goto done; |
89db9482 | 603 | |
44169075 | 604 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { |
e031ab23 DB |
605 | if (enable) |
606 | clk_enable(bank->dbck); | |
607 | else | |
608 | clk_disable(bank->dbck); | |
609 | } | |
5eb3bb9c KH |
610 | |
611 | __raw_writel(val, reg); | |
e031ab23 DB |
612 | done: |
613 | spin_unlock_irqrestore(&bank->lock, flags); | |
5eb3bb9c KH |
614 | } |
615 | EXPORT_SYMBOL(omap_set_gpio_debounce); | |
616 | ||
617 | void omap_set_gpio_debounce_time(int gpio, int enc_time) | |
618 | { | |
619 | struct gpio_bank *bank; | |
620 | void __iomem *reg; | |
621 | ||
622 | if (cpu_class_is_omap1()) | |
623 | return; | |
624 | ||
625 | bank = get_gpio_bank(gpio); | |
626 | reg = bank->base; | |
627 | ||
628 | enc_time &= 0xff; | |
629 | reg += OMAP24XX_GPIO_DEBOUNCE_VAL; | |
630 | __raw_writel(enc_time, reg); | |
631 | } | |
632 | EXPORT_SYMBOL(omap_set_gpio_debounce_time); | |
633 | ||
44169075 SS |
634 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
635 | defined(CONFIG_ARCH_OMAP4) | |
5eb3bb9c KH |
636 | static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, |
637 | int trigger) | |
5e1c5ff4 | 638 | { |
3ac4fa99 | 639 | void __iomem *base = bank->base; |
92105bb7 TL |
640 | u32 gpio_bit = 1 << gpio; |
641 | ||
642 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, | |
6cab4860 | 643 | trigger & IRQ_TYPE_LEVEL_LOW); |
92105bb7 | 644 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, |
6cab4860 | 645 | trigger & IRQ_TYPE_LEVEL_HIGH); |
92105bb7 | 646 | MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, |
6cab4860 | 647 | trigger & IRQ_TYPE_EDGE_RISING); |
92105bb7 | 648 | MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, |
6cab4860 | 649 | trigger & IRQ_TYPE_EDGE_FALLING); |
5eb3bb9c | 650 | |
3ac4fa99 JY |
651 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { |
652 | if (trigger != 0) | |
5eb3bb9c KH |
653 | __raw_writel(1 << gpio, bank->base |
654 | + OMAP24XX_GPIO_SETWKUENA); | |
3ac4fa99 | 655 | else |
5eb3bb9c KH |
656 | __raw_writel(1 << gpio, bank->base |
657 | + OMAP24XX_GPIO_CLEARWKUENA); | |
3ac4fa99 JY |
658 | } else { |
659 | if (trigger != 0) | |
660 | bank->enabled_non_wakeup_gpios |= gpio_bit; | |
661 | else | |
662 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
663 | } | |
5eb3bb9c | 664 | |
b144ff6f KH |
665 | bank->level_mask = |
666 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) | | |
667 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
92105bb7 | 668 | } |
3ac4fa99 | 669 | #endif |
92105bb7 TL |
670 | |
671 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) | |
672 | { | |
673 | void __iomem *reg = bank->base; | |
674 | u32 l = 0; | |
5e1c5ff4 TL |
675 | |
676 | switch (bank->method) { | |
e5c56ed3 | 677 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
678 | case METHOD_MPUIO: |
679 | reg += OMAP_MPUIO_GPIO_INT_EDGE; | |
680 | l = __raw_readl(reg); | |
6cab4860 | 681 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 682 | l |= 1 << gpio; |
6cab4860 | 683 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 684 | l &= ~(1 << gpio); |
92105bb7 TL |
685 | else |
686 | goto bad; | |
5e1c5ff4 | 687 | break; |
e5c56ed3 DB |
688 | #endif |
689 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
690 | case METHOD_GPIO_1510: |
691 | reg += OMAP1510_GPIO_INT_CONTROL; | |
692 | l = __raw_readl(reg); | |
6cab4860 | 693 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 694 | l |= 1 << gpio; |
6cab4860 | 695 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 696 | l &= ~(1 << gpio); |
92105bb7 TL |
697 | else |
698 | goto bad; | |
5e1c5ff4 | 699 | break; |
e5c56ed3 | 700 | #endif |
3ac4fa99 | 701 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 702 | case METHOD_GPIO_1610: |
5e1c5ff4 TL |
703 | if (gpio & 0x08) |
704 | reg += OMAP1610_GPIO_EDGE_CTRL2; | |
705 | else | |
706 | reg += OMAP1610_GPIO_EDGE_CTRL1; | |
707 | gpio &= 0x07; | |
708 | l = __raw_readl(reg); | |
709 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 710 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 711 | l |= 2 << (gpio << 1); |
6cab4860 | 712 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 713 | l |= 1 << (gpio << 1); |
3ac4fa99 JY |
714 | if (trigger) |
715 | /* Enable wake-up during idle for dynamic tick */ | |
716 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA); | |
717 | else | |
718 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); | |
5e1c5ff4 | 719 | break; |
3ac4fa99 JY |
720 | #endif |
721 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
722 | case METHOD_GPIO_730: |
723 | reg += OMAP730_GPIO_INT_CONTROL; | |
724 | l = __raw_readl(reg); | |
6cab4860 | 725 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 726 | l |= 1 << gpio; |
6cab4860 | 727 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 728 | l &= ~(1 << gpio); |
92105bb7 TL |
729 | else |
730 | goto bad; | |
731 | break; | |
3ac4fa99 | 732 | #endif |
56739a69 ZM |
733 | #ifdef CONFIG_ARCH_OMAP850 |
734 | case METHOD_GPIO_850: | |
735 | reg += OMAP850_GPIO_INT_CONTROL; | |
736 | l = __raw_readl(reg); | |
737 | if (trigger & IRQ_TYPE_EDGE_RISING) | |
738 | l |= 1 << gpio; | |
739 | else if (trigger & IRQ_TYPE_EDGE_FALLING) | |
740 | l &= ~(1 << gpio); | |
741 | else | |
742 | goto bad; | |
743 | break; | |
744 | #endif | |
44169075 SS |
745 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
746 | defined(CONFIG_ARCH_OMAP4) | |
92105bb7 | 747 | case METHOD_GPIO_24XX: |
3ac4fa99 | 748 | set_24xx_gpio_triggering(bank, gpio, trigger); |
5e1c5ff4 | 749 | break; |
3ac4fa99 | 750 | #endif |
5e1c5ff4 | 751 | default: |
92105bb7 | 752 | goto bad; |
5e1c5ff4 | 753 | } |
92105bb7 TL |
754 | __raw_writel(l, reg); |
755 | return 0; | |
756 | bad: | |
757 | return -EINVAL; | |
5e1c5ff4 TL |
758 | } |
759 | ||
92105bb7 | 760 | static int gpio_irq_type(unsigned irq, unsigned type) |
5e1c5ff4 TL |
761 | { |
762 | struct gpio_bank *bank; | |
92105bb7 TL |
763 | unsigned gpio; |
764 | int retval; | |
a6472533 | 765 | unsigned long flags; |
92105bb7 | 766 | |
5492fb1a | 767 | if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE) |
92105bb7 TL |
768 | gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); |
769 | else | |
770 | gpio = irq - IH_GPIO_BASE; | |
5e1c5ff4 TL |
771 | |
772 | if (check_gpio(gpio) < 0) | |
92105bb7 TL |
773 | return -EINVAL; |
774 | ||
e5c56ed3 | 775 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 776 | return -EINVAL; |
e5c56ed3 DB |
777 | |
778 | /* OMAP1 allows only only edge triggering */ | |
5492fb1a | 779 | if (!cpu_class_is_omap2() |
e5c56ed3 | 780 | && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) |
92105bb7 TL |
781 | return -EINVAL; |
782 | ||
58781016 | 783 | bank = get_irq_chip_data(irq); |
a6472533 | 784 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 785 | retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); |
b9772a22 DB |
786 | if (retval == 0) { |
787 | irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; | |
788 | irq_desc[irq].status |= type; | |
789 | } | |
a6472533 | 790 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
791 | |
792 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
793 | __set_irq_handler_unlocked(irq, handle_level_irq); | |
794 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
795 | __set_irq_handler_unlocked(irq, handle_edge_irq); | |
796 | ||
92105bb7 | 797 | return retval; |
5e1c5ff4 TL |
798 | } |
799 | ||
800 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
801 | { | |
92105bb7 | 802 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
803 | |
804 | switch (bank->method) { | |
e5c56ed3 | 805 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
806 | case METHOD_MPUIO: |
807 | /* MPUIO irqstatus is reset by reading the status register, | |
808 | * so do nothing here */ | |
809 | return; | |
e5c56ed3 DB |
810 | #endif |
811 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
812 | case METHOD_GPIO_1510: |
813 | reg += OMAP1510_GPIO_INT_STATUS; | |
814 | break; | |
e5c56ed3 DB |
815 | #endif |
816 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
817 | case METHOD_GPIO_1610: |
818 | reg += OMAP1610_GPIO_IRQSTATUS1; | |
819 | break; | |
e5c56ed3 DB |
820 | #endif |
821 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
822 | case METHOD_GPIO_730: |
823 | reg += OMAP730_GPIO_INT_STATUS; | |
824 | break; | |
e5c56ed3 | 825 | #endif |
56739a69 ZM |
826 | #ifdef CONFIG_ARCH_OMAP850 |
827 | case METHOD_GPIO_850: | |
828 | reg += OMAP850_GPIO_INT_STATUS; | |
829 | break; | |
830 | #endif | |
44169075 SS |
831 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
832 | defined(CONFIG_ARCH_OMAP4) | |
92105bb7 TL |
833 | case METHOD_GPIO_24XX: |
834 | reg += OMAP24XX_GPIO_IRQSTATUS1; | |
835 | break; | |
e5c56ed3 | 836 | #endif |
5e1c5ff4 | 837 | default: |
e5c56ed3 | 838 | WARN_ON(1); |
5e1c5ff4 TL |
839 | return; |
840 | } | |
841 | __raw_writel(gpio_mask, reg); | |
bee7930f HD |
842 | |
843 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
5492fb1a | 844 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
bedfd154 | 845 | reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; |
5492fb1a | 846 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) |
bedfd154 RQ |
847 | __raw_writel(gpio_mask, reg); |
848 | ||
849 | /* Flush posted write for the irq status to avoid spurious interrupts */ | |
850 | __raw_readl(reg); | |
5492fb1a | 851 | #endif |
5e1c5ff4 TL |
852 | } |
853 | ||
854 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
855 | { | |
856 | _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio)); | |
857 | } | |
858 | ||
ea6dedd7 ID |
859 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
860 | { | |
861 | void __iomem *reg = bank->base; | |
99c47707 ID |
862 | int inv = 0; |
863 | u32 l; | |
864 | u32 mask; | |
ea6dedd7 ID |
865 | |
866 | switch (bank->method) { | |
e5c56ed3 | 867 | #ifdef CONFIG_ARCH_OMAP1 |
ea6dedd7 ID |
868 | case METHOD_MPUIO: |
869 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
99c47707 ID |
870 | mask = 0xffff; |
871 | inv = 1; | |
ea6dedd7 | 872 | break; |
e5c56ed3 DB |
873 | #endif |
874 | #ifdef CONFIG_ARCH_OMAP15XX | |
ea6dedd7 ID |
875 | case METHOD_GPIO_1510: |
876 | reg += OMAP1510_GPIO_INT_MASK; | |
99c47707 ID |
877 | mask = 0xffff; |
878 | inv = 1; | |
ea6dedd7 | 879 | break; |
e5c56ed3 DB |
880 | #endif |
881 | #ifdef CONFIG_ARCH_OMAP16XX | |
ea6dedd7 ID |
882 | case METHOD_GPIO_1610: |
883 | reg += OMAP1610_GPIO_IRQENABLE1; | |
99c47707 | 884 | mask = 0xffff; |
ea6dedd7 | 885 | break; |
e5c56ed3 DB |
886 | #endif |
887 | #ifdef CONFIG_ARCH_OMAP730 | |
ea6dedd7 ID |
888 | case METHOD_GPIO_730: |
889 | reg += OMAP730_GPIO_INT_MASK; | |
99c47707 ID |
890 | mask = 0xffffffff; |
891 | inv = 1; | |
ea6dedd7 | 892 | break; |
e5c56ed3 | 893 | #endif |
56739a69 ZM |
894 | #ifdef CONFIG_ARCH_OMAP850 |
895 | case METHOD_GPIO_850: | |
896 | reg += OMAP850_GPIO_INT_MASK; | |
897 | mask = 0xffffffff; | |
898 | inv = 1; | |
899 | break; | |
900 | #endif | |
44169075 SS |
901 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
902 | defined(CONFIG_ARCH_OMAP4) | |
ea6dedd7 ID |
903 | case METHOD_GPIO_24XX: |
904 | reg += OMAP24XX_GPIO_IRQENABLE1; | |
99c47707 | 905 | mask = 0xffffffff; |
ea6dedd7 | 906 | break; |
e5c56ed3 | 907 | #endif |
ea6dedd7 | 908 | default: |
e5c56ed3 | 909 | WARN_ON(1); |
ea6dedd7 ID |
910 | return 0; |
911 | } | |
912 | ||
99c47707 ID |
913 | l = __raw_readl(reg); |
914 | if (inv) | |
915 | l = ~l; | |
916 | l &= mask; | |
917 | return l; | |
ea6dedd7 ID |
918 | } |
919 | ||
5e1c5ff4 TL |
920 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) |
921 | { | |
92105bb7 | 922 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
923 | u32 l; |
924 | ||
925 | switch (bank->method) { | |
e5c56ed3 | 926 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
927 | case METHOD_MPUIO: |
928 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
929 | l = __raw_readl(reg); | |
930 | if (enable) | |
931 | l &= ~(gpio_mask); | |
932 | else | |
933 | l |= gpio_mask; | |
934 | break; | |
e5c56ed3 DB |
935 | #endif |
936 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
937 | case METHOD_GPIO_1510: |
938 | reg += OMAP1510_GPIO_INT_MASK; | |
939 | l = __raw_readl(reg); | |
940 | if (enable) | |
941 | l &= ~(gpio_mask); | |
942 | else | |
943 | l |= gpio_mask; | |
944 | break; | |
e5c56ed3 DB |
945 | #endif |
946 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
947 | case METHOD_GPIO_1610: |
948 | if (enable) | |
949 | reg += OMAP1610_GPIO_SET_IRQENABLE1; | |
950 | else | |
951 | reg += OMAP1610_GPIO_CLEAR_IRQENABLE1; | |
952 | l = gpio_mask; | |
953 | break; | |
e5c56ed3 DB |
954 | #endif |
955 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
956 | case METHOD_GPIO_730: |
957 | reg += OMAP730_GPIO_INT_MASK; | |
958 | l = __raw_readl(reg); | |
959 | if (enable) | |
960 | l &= ~(gpio_mask); | |
961 | else | |
962 | l |= gpio_mask; | |
963 | break; | |
e5c56ed3 | 964 | #endif |
56739a69 ZM |
965 | #ifdef CONFIG_ARCH_OMAP850 |
966 | case METHOD_GPIO_850: | |
967 | reg += OMAP850_GPIO_INT_MASK; | |
968 | l = __raw_readl(reg); | |
969 | if (enable) | |
970 | l &= ~(gpio_mask); | |
971 | else | |
972 | l |= gpio_mask; | |
973 | break; | |
974 | #endif | |
44169075 SS |
975 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
976 | defined(CONFIG_ARCH_OMAP4) | |
92105bb7 TL |
977 | case METHOD_GPIO_24XX: |
978 | if (enable) | |
979 | reg += OMAP24XX_GPIO_SETIRQENABLE1; | |
980 | else | |
981 | reg += OMAP24XX_GPIO_CLEARIRQENABLE1; | |
982 | l = gpio_mask; | |
983 | break; | |
e5c56ed3 | 984 | #endif |
5e1c5ff4 | 985 | default: |
e5c56ed3 | 986 | WARN_ON(1); |
5e1c5ff4 TL |
987 | return; |
988 | } | |
989 | __raw_writel(l, reg); | |
990 | } | |
991 | ||
992 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
993 | { | |
994 | _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable); | |
995 | } | |
996 | ||
92105bb7 TL |
997 | /* |
998 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
999 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
1000 | * to the target, system will wake up always on GPIO events. While | |
1001 | * system is running all registered GPIO interrupts need to have wake-up | |
1002 | * enabled. When system is suspended, only selected GPIO interrupts need | |
1003 | * to have wake-up enabled. | |
1004 | */ | |
1005 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
1006 | { | |
a6472533 DB |
1007 | unsigned long flags; |
1008 | ||
92105bb7 | 1009 | switch (bank->method) { |
3ac4fa99 | 1010 | #ifdef CONFIG_ARCH_OMAP16XX |
11a78b79 | 1011 | case METHOD_MPUIO: |
92105bb7 | 1012 | case METHOD_GPIO_1610: |
a6472533 | 1013 | spin_lock_irqsave(&bank->lock, flags); |
b3bb4f68 | 1014 | if (enable) |
92105bb7 | 1015 | bank->suspend_wakeup |= (1 << gpio); |
b3bb4f68 | 1016 | else |
92105bb7 | 1017 | bank->suspend_wakeup &= ~(1 << gpio); |
a6472533 | 1018 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 1019 | return 0; |
3ac4fa99 | 1020 | #endif |
44169075 SS |
1021 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
1022 | defined(CONFIG_ARCH_OMAP4) | |
3ac4fa99 | 1023 | case METHOD_GPIO_24XX: |
11a78b79 DB |
1024 | if (bank->non_wakeup_gpios & (1 << gpio)) { |
1025 | printk(KERN_ERR "Unable to modify wakeup on " | |
1026 | "non-wakeup GPIO%d\n", | |
1027 | (bank - gpio_bank) * 32 + gpio); | |
1028 | return -EINVAL; | |
1029 | } | |
a6472533 | 1030 | spin_lock_irqsave(&bank->lock, flags); |
b3bb4f68 | 1031 | if (enable) |
3ac4fa99 | 1032 | bank->suspend_wakeup |= (1 << gpio); |
b3bb4f68 | 1033 | else |
3ac4fa99 | 1034 | bank->suspend_wakeup &= ~(1 << gpio); |
a6472533 | 1035 | spin_unlock_irqrestore(&bank->lock, flags); |
3ac4fa99 JY |
1036 | return 0; |
1037 | #endif | |
92105bb7 TL |
1038 | default: |
1039 | printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n", | |
1040 | bank->method); | |
1041 | return -EINVAL; | |
1042 | } | |
1043 | } | |
1044 | ||
4196dd6b TL |
1045 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
1046 | { | |
1047 | _set_gpio_direction(bank, get_gpio_index(gpio), 1); | |
1048 | _set_gpio_irqenable(bank, gpio, 0); | |
1049 | _clear_gpio_irqstatus(bank, gpio); | |
6cab4860 | 1050 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); |
4196dd6b TL |
1051 | } |
1052 | ||
92105bb7 TL |
1053 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
1054 | static int gpio_wake_enable(unsigned int irq, unsigned int enable) | |
1055 | { | |
1056 | unsigned int gpio = irq - IH_GPIO_BASE; | |
1057 | struct gpio_bank *bank; | |
1058 | int retval; | |
1059 | ||
1060 | if (check_gpio(gpio) < 0) | |
1061 | return -ENODEV; | |
58781016 | 1062 | bank = get_irq_chip_data(irq); |
92105bb7 | 1063 | retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); |
92105bb7 TL |
1064 | |
1065 | return retval; | |
1066 | } | |
1067 | ||
3ff164e1 | 1068 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 1069 | { |
3ff164e1 | 1070 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 1071 | unsigned long flags; |
52e31344 | 1072 | |
a6472533 | 1073 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 1074 | |
4196dd6b TL |
1075 | /* Set trigger to none. You need to enable the desired trigger with |
1076 | * request_irq() or set_irq_type(). | |
1077 | */ | |
3ff164e1 | 1078 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
92105bb7 | 1079 | |
1a8bfa1e | 1080 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 1081 | if (bank->method == METHOD_GPIO_1510) { |
92105bb7 | 1082 | void __iomem *reg; |
5e1c5ff4 | 1083 | |
92105bb7 | 1084 | /* Claim the pin for MPU */ |
5e1c5ff4 | 1085 | reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; |
3ff164e1 | 1086 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
5e1c5ff4 TL |
1087 | } |
1088 | #endif | |
a6472533 | 1089 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
1090 | |
1091 | return 0; | |
1092 | } | |
1093 | ||
3ff164e1 | 1094 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 1095 | { |
3ff164e1 | 1096 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 1097 | unsigned long flags; |
5e1c5ff4 | 1098 | |
a6472533 | 1099 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1100 | #ifdef CONFIG_ARCH_OMAP16XX |
1101 | if (bank->method == METHOD_GPIO_1610) { | |
1102 | /* Disable wake-up during idle for dynamic tick */ | |
1103 | void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
3ff164e1 | 1104 | __raw_writel(1 << offset, reg); |
92105bb7 TL |
1105 | } |
1106 | #endif | |
44169075 SS |
1107 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
1108 | defined(CONFIG_ARCH_OMAP4) | |
92105bb7 TL |
1109 | if (bank->method == METHOD_GPIO_24XX) { |
1110 | /* Disable wake-up during idle for dynamic tick */ | |
1111 | void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; | |
3ff164e1 | 1112 | __raw_writel(1 << offset, reg); |
92105bb7 TL |
1113 | } |
1114 | #endif | |
3ff164e1 | 1115 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 1116 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
1117 | } |
1118 | ||
1119 | /* | |
1120 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
1121 | * avoid missing GPIO interrupts for other lines in the bank. | |
1122 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
1123 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
1124 | * If we wait to unmask individual GPIO lines in the bank after the | |
1125 | * line's interrupt handler has been run, we may miss some nested | |
1126 | * interrupts. | |
1127 | */ | |
10dd5ce2 | 1128 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 1129 | { |
92105bb7 | 1130 | void __iomem *isr_reg = NULL; |
5e1c5ff4 TL |
1131 | u32 isr; |
1132 | unsigned int gpio_irq; | |
1133 | struct gpio_bank *bank; | |
ea6dedd7 ID |
1134 | u32 retrigger = 0; |
1135 | int unmasked = 0; | |
5e1c5ff4 TL |
1136 | |
1137 | desc->chip->ack(irq); | |
1138 | ||
418ca1f0 | 1139 | bank = get_irq_data(irq); |
e5c56ed3 | 1140 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
1141 | if (bank->method == METHOD_MPUIO) |
1142 | isr_reg = bank->base + OMAP_MPUIO_GPIO_INT; | |
e5c56ed3 | 1143 | #endif |
1a8bfa1e | 1144 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 TL |
1145 | if (bank->method == METHOD_GPIO_1510) |
1146 | isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS; | |
1147 | #endif | |
1148 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1149 | if (bank->method == METHOD_GPIO_1610) | |
1150 | isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; | |
1151 | #endif | |
1152 | #ifdef CONFIG_ARCH_OMAP730 | |
1153 | if (bank->method == METHOD_GPIO_730) | |
1154 | isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; | |
1155 | #endif | |
56739a69 ZM |
1156 | #ifdef CONFIG_ARCH_OMAP850 |
1157 | if (bank->method == METHOD_GPIO_850) | |
1158 | isr_reg = bank->base + OMAP850_GPIO_INT_STATUS; | |
1159 | #endif | |
44169075 SS |
1160 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
1161 | defined(CONFIG_ARCH_OMAP4) | |
92105bb7 TL |
1162 | if (bank->method == METHOD_GPIO_24XX) |
1163 | isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; | |
1164 | #endif | |
92105bb7 | 1165 | while(1) { |
6e60e79a | 1166 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 1167 | u32 enabled; |
6e60e79a | 1168 | |
ea6dedd7 ID |
1169 | enabled = _get_gpio_irqbank_mask(bank); |
1170 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a TL |
1171 | |
1172 | if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) | |
1173 | isr &= 0x0000ffff; | |
1174 | ||
5492fb1a | 1175 | if (cpu_class_is_omap2()) { |
b144ff6f | 1176 | level_mask = bank->level_mask & enabled; |
ea6dedd7 | 1177 | } |
6e60e79a TL |
1178 | |
1179 | /* clear edge sensitive interrupts before handler(s) are | |
1180 | called so that we don't miss any interrupt occurred while | |
1181 | executing them */ | |
1182 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0); | |
1183 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); | |
1184 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1); | |
1185 | ||
1186 | /* if there is only edge sensitive GPIO pin interrupts | |
1187 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
1188 | if (!level_mask && !unmasked) { |
1189 | unmasked = 1; | |
6e60e79a | 1190 | desc->chip->unmask(irq); |
ea6dedd7 | 1191 | } |
92105bb7 | 1192 | |
ea6dedd7 ID |
1193 | isr |= retrigger; |
1194 | retrigger = 0; | |
92105bb7 TL |
1195 | if (!isr) |
1196 | break; | |
1197 | ||
1198 | gpio_irq = bank->virtual_irq_start; | |
1199 | for (; isr != 0; isr >>= 1, gpio_irq++) { | |
92105bb7 TL |
1200 | if (!(isr & 1)) |
1201 | continue; | |
29454dde | 1202 | |
d8aa0251 | 1203 | generic_handle_irq(gpio_irq); |
92105bb7 | 1204 | } |
1a8bfa1e | 1205 | } |
ea6dedd7 ID |
1206 | /* if bank has any level sensitive GPIO pin interrupt |
1207 | configured, we must unmask the bank interrupt only after | |
1208 | handler(s) are executed in order to avoid spurious bank | |
1209 | interrupt */ | |
1210 | if (!unmasked) | |
1211 | desc->chip->unmask(irq); | |
1212 | ||
5e1c5ff4 TL |
1213 | } |
1214 | ||
4196dd6b TL |
1215 | static void gpio_irq_shutdown(unsigned int irq) |
1216 | { | |
1217 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1218 | struct gpio_bank *bank = get_irq_chip_data(irq); |
4196dd6b TL |
1219 | |
1220 | _reset_gpio(bank, gpio); | |
1221 | } | |
1222 | ||
5e1c5ff4 TL |
1223 | static void gpio_ack_irq(unsigned int irq) |
1224 | { | |
1225 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1226 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1227 | |
1228 | _clear_gpio_irqstatus(bank, gpio); | |
1229 | } | |
1230 | ||
1231 | static void gpio_mask_irq(unsigned int irq) | |
1232 | { | |
1233 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1234 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1235 | |
1236 | _set_gpio_irqenable(bank, gpio, 0); | |
55b6019a | 1237 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); |
5e1c5ff4 TL |
1238 | } |
1239 | ||
1240 | static void gpio_unmask_irq(unsigned int irq) | |
1241 | { | |
1242 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1243 | struct gpio_bank *bank = get_irq_chip_data(irq); |
b144ff6f | 1244 | unsigned int irq_mask = 1 << get_gpio_index(gpio); |
55b6019a KH |
1245 | struct irq_desc *desc = irq_to_desc(irq); |
1246 | u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK; | |
1247 | ||
1248 | if (trigger) | |
1249 | _set_gpio_triggering(bank, get_gpio_index(gpio), trigger); | |
b144ff6f KH |
1250 | |
1251 | /* For level-triggered GPIOs, the clearing must be done after | |
1252 | * the HW source is cleared, thus after the handler has run */ | |
1253 | if (bank->level_mask & irq_mask) { | |
1254 | _set_gpio_irqenable(bank, gpio, 0); | |
1255 | _clear_gpio_irqstatus(bank, gpio); | |
1256 | } | |
5e1c5ff4 | 1257 | |
4de8c75b | 1258 | _set_gpio_irqenable(bank, gpio, 1); |
5e1c5ff4 TL |
1259 | } |
1260 | ||
e5c56ed3 DB |
1261 | static struct irq_chip gpio_irq_chip = { |
1262 | .name = "GPIO", | |
1263 | .shutdown = gpio_irq_shutdown, | |
1264 | .ack = gpio_ack_irq, | |
1265 | .mask = gpio_mask_irq, | |
1266 | .unmask = gpio_unmask_irq, | |
1267 | .set_type = gpio_irq_type, | |
1268 | .set_wake = gpio_wake_enable, | |
1269 | }; | |
1270 | ||
1271 | /*---------------------------------------------------------------------*/ | |
1272 | ||
1273 | #ifdef CONFIG_ARCH_OMAP1 | |
1274 | ||
1275 | /* MPUIO uses the always-on 32k clock */ | |
1276 | ||
5e1c5ff4 TL |
1277 | static void mpuio_ack_irq(unsigned int irq) |
1278 | { | |
1279 | /* The ISR is reset automatically, so do nothing here. */ | |
1280 | } | |
1281 | ||
1282 | static void mpuio_mask_irq(unsigned int irq) | |
1283 | { | |
1284 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1285 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1286 | |
1287 | _set_gpio_irqenable(bank, gpio, 0); | |
1288 | } | |
1289 | ||
1290 | static void mpuio_unmask_irq(unsigned int irq) | |
1291 | { | |
1292 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1293 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1294 | |
1295 | _set_gpio_irqenable(bank, gpio, 1); | |
1296 | } | |
1297 | ||
e5c56ed3 DB |
1298 | static struct irq_chip mpuio_irq_chip = { |
1299 | .name = "MPUIO", | |
1300 | .ack = mpuio_ack_irq, | |
1301 | .mask = mpuio_mask_irq, | |
1302 | .unmask = mpuio_unmask_irq, | |
92105bb7 | 1303 | .set_type = gpio_irq_type, |
11a78b79 DB |
1304 | #ifdef CONFIG_ARCH_OMAP16XX |
1305 | /* REVISIT: assuming only 16xx supports MPUIO wake events */ | |
1306 | .set_wake = gpio_wake_enable, | |
1307 | #endif | |
5e1c5ff4 TL |
1308 | }; |
1309 | ||
e5c56ed3 DB |
1310 | |
1311 | #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) | |
1312 | ||
11a78b79 DB |
1313 | |
1314 | #ifdef CONFIG_ARCH_OMAP16XX | |
1315 | ||
1316 | #include <linux/platform_device.h> | |
1317 | ||
1318 | static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg) | |
1319 | { | |
1320 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1321 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
a6472533 | 1322 | unsigned long flags; |
11a78b79 | 1323 | |
a6472533 | 1324 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 DB |
1325 | bank->saved_wakeup = __raw_readl(mask_reg); |
1326 | __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); | |
a6472533 | 1327 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1328 | |
1329 | return 0; | |
1330 | } | |
1331 | ||
1332 | static int omap_mpuio_resume_early(struct platform_device *pdev) | |
1333 | { | |
1334 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1335 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
a6472533 | 1336 | unsigned long flags; |
11a78b79 | 1337 | |
a6472533 | 1338 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 1339 | __raw_writel(bank->saved_wakeup, mask_reg); |
a6472533 | 1340 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1341 | |
1342 | return 0; | |
1343 | } | |
1344 | ||
1345 | /* use platform_driver for this, now that there's no longer any | |
1346 | * point to sys_device (other than not disturbing old code). | |
1347 | */ | |
1348 | static struct platform_driver omap_mpuio_driver = { | |
1349 | .suspend_late = omap_mpuio_suspend_late, | |
1350 | .resume_early = omap_mpuio_resume_early, | |
1351 | .driver = { | |
1352 | .name = "mpuio", | |
1353 | }, | |
1354 | }; | |
1355 | ||
1356 | static struct platform_device omap_mpuio_device = { | |
1357 | .name = "mpuio", | |
1358 | .id = -1, | |
1359 | .dev = { | |
1360 | .driver = &omap_mpuio_driver.driver, | |
1361 | } | |
1362 | /* could list the /proc/iomem resources */ | |
1363 | }; | |
1364 | ||
1365 | static inline void mpuio_init(void) | |
1366 | { | |
fcf126d8 DB |
1367 | platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]); |
1368 | ||
11a78b79 DB |
1369 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
1370 | (void) platform_device_register(&omap_mpuio_device); | |
1371 | } | |
1372 | ||
1373 | #else | |
1374 | static inline void mpuio_init(void) {} | |
1375 | #endif /* 16xx */ | |
1376 | ||
e5c56ed3 DB |
1377 | #else |
1378 | ||
1379 | extern struct irq_chip mpuio_irq_chip; | |
1380 | ||
1381 | #define bank_is_mpuio(bank) 0 | |
11a78b79 | 1382 | static inline void mpuio_init(void) {} |
e5c56ed3 DB |
1383 | |
1384 | #endif | |
1385 | ||
1386 | /*---------------------------------------------------------------------*/ | |
5e1c5ff4 | 1387 | |
52e31344 DB |
1388 | /* REVISIT these are stupid implementations! replace by ones that |
1389 | * don't switch on METHOD_* and which mostly avoid spinlocks | |
1390 | */ | |
1391 | ||
1392 | static int gpio_input(struct gpio_chip *chip, unsigned offset) | |
1393 | { | |
1394 | struct gpio_bank *bank; | |
1395 | unsigned long flags; | |
1396 | ||
1397 | bank = container_of(chip, struct gpio_bank, chip); | |
1398 | spin_lock_irqsave(&bank->lock, flags); | |
1399 | _set_gpio_direction(bank, offset, 1); | |
1400 | spin_unlock_irqrestore(&bank->lock, flags); | |
1401 | return 0; | |
1402 | } | |
1403 | ||
b37c45b8 RQ |
1404 | static int gpio_is_input(struct gpio_bank *bank, int mask) |
1405 | { | |
1406 | void __iomem *reg = bank->base; | |
1407 | ||
1408 | switch (bank->method) { | |
1409 | case METHOD_MPUIO: | |
1410 | reg += OMAP_MPUIO_IO_CNTL; | |
1411 | break; | |
1412 | case METHOD_GPIO_1510: | |
1413 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
1414 | break; | |
1415 | case METHOD_GPIO_1610: | |
1416 | reg += OMAP1610_GPIO_DIRECTION; | |
1417 | break; | |
1418 | case METHOD_GPIO_730: | |
1419 | reg += OMAP730_GPIO_DIR_CONTROL; | |
1420 | break; | |
1421 | case METHOD_GPIO_850: | |
1422 | reg += OMAP850_GPIO_DIR_CONTROL; | |
1423 | break; | |
1424 | case METHOD_GPIO_24XX: | |
1425 | reg += OMAP24XX_GPIO_OE; | |
1426 | break; | |
1427 | } | |
1428 | return __raw_readl(reg) & mask; | |
1429 | } | |
1430 | ||
52e31344 DB |
1431 | static int gpio_get(struct gpio_chip *chip, unsigned offset) |
1432 | { | |
b37c45b8 RQ |
1433 | struct gpio_bank *bank; |
1434 | void __iomem *reg; | |
1435 | int gpio; | |
1436 | u32 mask; | |
1437 | ||
1438 | gpio = chip->base + offset; | |
1439 | bank = get_gpio_bank(gpio); | |
1440 | reg = bank->base; | |
1441 | mask = 1 << get_gpio_index(gpio); | |
1442 | ||
1443 | if (gpio_is_input(bank, mask)) | |
1444 | return _get_gpio_datain(bank, gpio); | |
1445 | else | |
1446 | return _get_gpio_dataout(bank, gpio); | |
52e31344 DB |
1447 | } |
1448 | ||
1449 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
1450 | { | |
1451 | struct gpio_bank *bank; | |
1452 | unsigned long flags; | |
1453 | ||
1454 | bank = container_of(chip, struct gpio_bank, chip); | |
1455 | spin_lock_irqsave(&bank->lock, flags); | |
1456 | _set_gpio_dataout(bank, offset, value); | |
1457 | _set_gpio_direction(bank, offset, 0); | |
1458 | spin_unlock_irqrestore(&bank->lock, flags); | |
1459 | return 0; | |
1460 | } | |
1461 | ||
1462 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
1463 | { | |
1464 | struct gpio_bank *bank; | |
1465 | unsigned long flags; | |
1466 | ||
1467 | bank = container_of(chip, struct gpio_bank, chip); | |
1468 | spin_lock_irqsave(&bank->lock, flags); | |
1469 | _set_gpio_dataout(bank, offset, value); | |
1470 | spin_unlock_irqrestore(&bank->lock, flags); | |
1471 | } | |
1472 | ||
a007b709 DB |
1473 | static int gpio_2irq(struct gpio_chip *chip, unsigned offset) |
1474 | { | |
1475 | struct gpio_bank *bank; | |
1476 | ||
1477 | bank = container_of(chip, struct gpio_bank, chip); | |
1478 | return bank->virtual_irq_start + offset; | |
1479 | } | |
1480 | ||
52e31344 DB |
1481 | /*---------------------------------------------------------------------*/ |
1482 | ||
1a8bfa1e | 1483 | static int initialized; |
44169075 | 1484 | #if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)) |
1a8bfa1e | 1485 | static struct clk * gpio_ick; |
5492fb1a SMK |
1486 | #endif |
1487 | ||
1488 | #if defined(CONFIG_ARCH_OMAP2) | |
1a8bfa1e | 1489 | static struct clk * gpio_fck; |
5492fb1a | 1490 | #endif |
5e1c5ff4 | 1491 | |
5492fb1a | 1492 | #if defined(CONFIG_ARCH_OMAP2430) |
56a25641 SMK |
1493 | static struct clk * gpio5_ick; |
1494 | static struct clk * gpio5_fck; | |
1495 | #endif | |
1496 | ||
44169075 | 1497 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
5492fb1a SMK |
1498 | static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; |
1499 | #endif | |
1500 | ||
8ba55c5c DB |
1501 | /* This lock class tells lockdep that GPIO irqs are in a different |
1502 | * category than their parents, so it won't report false recursion. | |
1503 | */ | |
1504 | static struct lock_class_key gpio_lock_class; | |
1505 | ||
5e1c5ff4 TL |
1506 | static int __init _omap_gpio_init(void) |
1507 | { | |
1508 | int i; | |
52e31344 | 1509 | int gpio = 0; |
5e1c5ff4 | 1510 | struct gpio_bank *bank; |
5492fb1a | 1511 | char clk_name[11]; |
5e1c5ff4 TL |
1512 | |
1513 | initialized = 1; | |
1514 | ||
5492fb1a | 1515 | #if defined(CONFIG_ARCH_OMAP1) |
6e60e79a | 1516 | if (cpu_is_omap15xx()) { |
1a8bfa1e TL |
1517 | gpio_ick = clk_get(NULL, "arm_gpio_ck"); |
1518 | if (IS_ERR(gpio_ick)) | |
92105bb7 TL |
1519 | printk("Could not get arm_gpio_ck\n"); |
1520 | else | |
30ff720b | 1521 | clk_enable(gpio_ick); |
1a8bfa1e | 1522 | } |
5492fb1a SMK |
1523 | #endif |
1524 | #if defined(CONFIG_ARCH_OMAP2) | |
1525 | if (cpu_class_is_omap2()) { | |
1a8bfa1e TL |
1526 | gpio_ick = clk_get(NULL, "gpios_ick"); |
1527 | if (IS_ERR(gpio_ick)) | |
1528 | printk("Could not get gpios_ick\n"); | |
1529 | else | |
30ff720b | 1530 | clk_enable(gpio_ick); |
1a8bfa1e | 1531 | gpio_fck = clk_get(NULL, "gpios_fck"); |
1630b52d | 1532 | if (IS_ERR(gpio_fck)) |
1a8bfa1e TL |
1533 | printk("Could not get gpios_fck\n"); |
1534 | else | |
30ff720b | 1535 | clk_enable(gpio_fck); |
56a25641 SMK |
1536 | |
1537 | /* | |
5492fb1a | 1538 | * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK |
56a25641 | 1539 | */ |
5492fb1a | 1540 | #if defined(CONFIG_ARCH_OMAP2430) |
56a25641 SMK |
1541 | if (cpu_is_omap2430()) { |
1542 | gpio5_ick = clk_get(NULL, "gpio5_ick"); | |
1543 | if (IS_ERR(gpio5_ick)) | |
1544 | printk("Could not get gpio5_ick\n"); | |
1545 | else | |
1546 | clk_enable(gpio5_ick); | |
1547 | gpio5_fck = clk_get(NULL, "gpio5_fck"); | |
1548 | if (IS_ERR(gpio5_fck)) | |
1549 | printk("Could not get gpio5_fck\n"); | |
1550 | else | |
1551 | clk_enable(gpio5_fck); | |
1552 | } | |
1553 | #endif | |
5492fb1a SMK |
1554 | } |
1555 | #endif | |
1556 | ||
44169075 SS |
1557 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
1558 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { | |
5492fb1a SMK |
1559 | for (i = 0; i < OMAP34XX_NR_GPIOS; i++) { |
1560 | sprintf(clk_name, "gpio%d_ick", i + 1); | |
1561 | gpio_iclks[i] = clk_get(NULL, clk_name); | |
1562 | if (IS_ERR(gpio_iclks[i])) | |
1563 | printk(KERN_ERR "Could not get %s\n", clk_name); | |
1564 | else | |
1565 | clk_enable(gpio_iclks[i]); | |
5492fb1a SMK |
1566 | } |
1567 | } | |
1568 | #endif | |
1569 | ||
92105bb7 | 1570 | |
1a8bfa1e | 1571 | #ifdef CONFIG_ARCH_OMAP15XX |
6e60e79a | 1572 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
1573 | printk(KERN_INFO "OMAP1510 GPIO hardware\n"); |
1574 | gpio_bank_count = 2; | |
1575 | gpio_bank = gpio_bank_1510; | |
1576 | } | |
1577 | #endif | |
1578 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1579 | if (cpu_is_omap16xx()) { | |
92105bb7 | 1580 | u32 rev; |
5e1c5ff4 TL |
1581 | |
1582 | gpio_bank_count = 5; | |
1583 | gpio_bank = gpio_bank_1610; | |
7c7095aa | 1584 | rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); |
5e1c5ff4 TL |
1585 | printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", |
1586 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1587 | } | |
1588 | #endif | |
1589 | #ifdef CONFIG_ARCH_OMAP730 | |
1590 | if (cpu_is_omap730()) { | |
1591 | printk(KERN_INFO "OMAP730 GPIO hardware\n"); | |
1592 | gpio_bank_count = 7; | |
1593 | gpio_bank = gpio_bank_730; | |
1594 | } | |
92105bb7 | 1595 | #endif |
56739a69 ZM |
1596 | #ifdef CONFIG_ARCH_OMAP850 |
1597 | if (cpu_is_omap850()) { | |
1598 | printk(KERN_INFO "OMAP850 GPIO hardware\n"); | |
1599 | gpio_bank_count = 7; | |
1600 | gpio_bank = gpio_bank_850; | |
1601 | } | |
1602 | #endif | |
56a25641 | 1603 | |
92105bb7 | 1604 | #ifdef CONFIG_ARCH_OMAP24XX |
56a25641 | 1605 | if (cpu_is_omap242x()) { |
92105bb7 TL |
1606 | int rev; |
1607 | ||
1608 | gpio_bank_count = 4; | |
56a25641 | 1609 | gpio_bank = gpio_bank_242x; |
7c7095aa | 1610 | rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); |
56a25641 SMK |
1611 | printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n", |
1612 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1613 | } | |
1614 | if (cpu_is_omap243x()) { | |
1615 | int rev; | |
1616 | ||
1617 | gpio_bank_count = 5; | |
1618 | gpio_bank = gpio_bank_243x; | |
7c7095aa | 1619 | rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); |
56a25641 | 1620 | printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n", |
92105bb7 TL |
1621 | (rev >> 4) & 0x0f, rev & 0x0f); |
1622 | } | |
5492fb1a SMK |
1623 | #endif |
1624 | #ifdef CONFIG_ARCH_OMAP34XX | |
1625 | if (cpu_is_omap34xx()) { | |
1626 | int rev; | |
1627 | ||
1628 | gpio_bank_count = OMAP34XX_NR_GPIOS; | |
1629 | gpio_bank = gpio_bank_34xx; | |
7c7095aa | 1630 | rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); |
5492fb1a SMK |
1631 | printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n", |
1632 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1633 | } | |
44169075 SS |
1634 | #endif |
1635 | #ifdef CONFIG_ARCH_OMAP4 | |
1636 | if (cpu_is_omap44xx()) { | |
1637 | int rev; | |
1638 | ||
1639 | gpio_bank_count = OMAP34XX_NR_GPIOS; | |
1640 | gpio_bank = gpio_bank_44xx; | |
1641 | rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); | |
1642 | printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n", | |
1643 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1644 | } | |
5e1c5ff4 TL |
1645 | #endif |
1646 | for (i = 0; i < gpio_bank_count; i++) { | |
1647 | int j, gpio_count = 16; | |
1648 | ||
1649 | bank = &gpio_bank[i]; | |
5e1c5ff4 | 1650 | spin_lock_init(&bank->lock); |
e5c56ed3 | 1651 | if (bank_is_mpuio(bank)) |
7c7095aa | 1652 | __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT); |
d11ac979 | 1653 | if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { |
5e1c5ff4 TL |
1654 | __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); |
1655 | __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); | |
1656 | } | |
d11ac979 | 1657 | if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { |
5e1c5ff4 TL |
1658 | __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1); |
1659 | __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); | |
92105bb7 | 1660 | __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); |
5e1c5ff4 | 1661 | } |
56739a69 | 1662 | if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) { |
5e1c5ff4 TL |
1663 | __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); |
1664 | __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); | |
1665 | ||
1666 | gpio_count = 32; /* 730 has 32-bit GPIOs */ | |
1667 | } | |
d11ac979 | 1668 | |
44169075 SS |
1669 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
1670 | defined(CONFIG_ARCH_OMAP4) | |
92105bb7 | 1671 | if (bank->method == METHOD_GPIO_24XX) { |
3ac4fa99 JY |
1672 | static const u32 non_wakeup_gpios[] = { |
1673 | 0xe203ffc0, 0x08700040 | |
1674 | }; | |
1675 | ||
92105bb7 TL |
1676 | __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1); |
1677 | __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1); | |
14f1c3bf | 1678 | __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG); |
cb5793db | 1679 | __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN); |
14f1c3bf JY |
1680 | |
1681 | /* Initialize interface clock ungated, module enabled */ | |
1682 | __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); | |
3ac4fa99 JY |
1683 | if (i < ARRAY_SIZE(non_wakeup_gpios)) |
1684 | bank->non_wakeup_gpios = non_wakeup_gpios[i]; | |
92105bb7 TL |
1685 | gpio_count = 32; |
1686 | } | |
5e1c5ff4 | 1687 | #endif |
52e31344 DB |
1688 | |
1689 | /* REVISIT eventually switch from OMAP-specific gpio structs | |
1690 | * over to the generic ones | |
1691 | */ | |
3ff164e1 JN |
1692 | bank->chip.request = omap_gpio_request; |
1693 | bank->chip.free = omap_gpio_free; | |
52e31344 DB |
1694 | bank->chip.direction_input = gpio_input; |
1695 | bank->chip.get = gpio_get; | |
1696 | bank->chip.direction_output = gpio_output; | |
1697 | bank->chip.set = gpio_set; | |
a007b709 | 1698 | bank->chip.to_irq = gpio_2irq; |
52e31344 DB |
1699 | if (bank_is_mpuio(bank)) { |
1700 | bank->chip.label = "mpuio"; | |
69114a47 | 1701 | #ifdef CONFIG_ARCH_OMAP16XX |
d8f388d8 DB |
1702 | bank->chip.dev = &omap_mpuio_device.dev; |
1703 | #endif | |
52e31344 DB |
1704 | bank->chip.base = OMAP_MPUIO(0); |
1705 | } else { | |
1706 | bank->chip.label = "gpio"; | |
1707 | bank->chip.base = gpio; | |
1708 | gpio += gpio_count; | |
1709 | } | |
1710 | bank->chip.ngpio = gpio_count; | |
1711 | ||
1712 | gpiochip_add(&bank->chip); | |
1713 | ||
5e1c5ff4 TL |
1714 | for (j = bank->virtual_irq_start; |
1715 | j < bank->virtual_irq_start + gpio_count; j++) { | |
8ba55c5c | 1716 | lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); |
58781016 | 1717 | set_irq_chip_data(j, bank); |
e5c56ed3 | 1718 | if (bank_is_mpuio(bank)) |
5e1c5ff4 TL |
1719 | set_irq_chip(j, &mpuio_irq_chip); |
1720 | else | |
1721 | set_irq_chip(j, &gpio_irq_chip); | |
10dd5ce2 | 1722 | set_irq_handler(j, handle_simple_irq); |
5e1c5ff4 TL |
1723 | set_irq_flags(j, IRQF_VALID); |
1724 | } | |
1725 | set_irq_chained_handler(bank->irq, gpio_irq_handler); | |
1726 | set_irq_data(bank->irq, bank); | |
89db9482 | 1727 | |
44169075 | 1728 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { |
89db9482 JH |
1729 | sprintf(clk_name, "gpio%d_dbck", i + 1); |
1730 | bank->dbck = clk_get(NULL, clk_name); | |
1731 | if (IS_ERR(bank->dbck)) | |
1732 | printk(KERN_ERR "Could not get %s\n", clk_name); | |
1733 | } | |
5e1c5ff4 TL |
1734 | } |
1735 | ||
1736 | /* Enable system clock for GPIO module. | |
1737 | * The CAM_CLK_CTRL *is* really the right place. */ | |
92105bb7 | 1738 | if (cpu_is_omap16xx()) |
5e1c5ff4 TL |
1739 | omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL); |
1740 | ||
14f1c3bf JY |
1741 | /* Enable autoidle for the OCP interface */ |
1742 | if (cpu_is_omap24xx()) | |
1743 | omap_writel(1 << 0, 0x48019010); | |
5492fb1a SMK |
1744 | if (cpu_is_omap34xx()) |
1745 | omap_writel(1 << 0, 0x48306814); | |
d11ac979 | 1746 | |
5e1c5ff4 TL |
1747 | return 0; |
1748 | } | |
1749 | ||
44169075 SS |
1750 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ |
1751 | defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4) | |
92105bb7 TL |
1752 | static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) |
1753 | { | |
1754 | int i; | |
1755 | ||
5492fb1a | 1756 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
1757 | return 0; |
1758 | ||
1759 | for (i = 0; i < gpio_bank_count; i++) { | |
1760 | struct gpio_bank *bank = &gpio_bank[i]; | |
1761 | void __iomem *wake_status; | |
1762 | void __iomem *wake_clear; | |
1763 | void __iomem *wake_set; | |
a6472533 | 1764 | unsigned long flags; |
92105bb7 TL |
1765 | |
1766 | switch (bank->method) { | |
e5c56ed3 | 1767 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1768 | case METHOD_GPIO_1610: |
1769 | wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; | |
1770 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1771 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1772 | break; | |
e5c56ed3 | 1773 | #endif |
44169075 SS |
1774 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
1775 | defined(CONFIG_ARCH_OMAP4) | |
92105bb7 | 1776 | case METHOD_GPIO_24XX: |
723fdb78 | 1777 | wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; |
92105bb7 TL |
1778 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1779 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
1780 | break; | |
e5c56ed3 | 1781 | #endif |
92105bb7 TL |
1782 | default: |
1783 | continue; | |
1784 | } | |
1785 | ||
a6472533 | 1786 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1787 | bank->saved_wakeup = __raw_readl(wake_status); |
1788 | __raw_writel(0xffffffff, wake_clear); | |
1789 | __raw_writel(bank->suspend_wakeup, wake_set); | |
a6472533 | 1790 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
1791 | } |
1792 | ||
1793 | return 0; | |
1794 | } | |
1795 | ||
1796 | static int omap_gpio_resume(struct sys_device *dev) | |
1797 | { | |
1798 | int i; | |
1799 | ||
723fdb78 | 1800 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
1801 | return 0; |
1802 | ||
1803 | for (i = 0; i < gpio_bank_count; i++) { | |
1804 | struct gpio_bank *bank = &gpio_bank[i]; | |
1805 | void __iomem *wake_clear; | |
1806 | void __iomem *wake_set; | |
a6472533 | 1807 | unsigned long flags; |
92105bb7 TL |
1808 | |
1809 | switch (bank->method) { | |
e5c56ed3 | 1810 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1811 | case METHOD_GPIO_1610: |
1812 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1813 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1814 | break; | |
e5c56ed3 | 1815 | #endif |
44169075 SS |
1816 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
1817 | defined(CONFIG_ARCH_OMAP4) | |
92105bb7 | 1818 | case METHOD_GPIO_24XX: |
0d9356cb TL |
1819 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1820 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
92105bb7 | 1821 | break; |
e5c56ed3 | 1822 | #endif |
92105bb7 TL |
1823 | default: |
1824 | continue; | |
1825 | } | |
1826 | ||
a6472533 | 1827 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1828 | __raw_writel(0xffffffff, wake_clear); |
1829 | __raw_writel(bank->saved_wakeup, wake_set); | |
a6472533 | 1830 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
1831 | } |
1832 | ||
1833 | return 0; | |
1834 | } | |
1835 | ||
1836 | static struct sysdev_class omap_gpio_sysclass = { | |
af5ca3f4 | 1837 | .name = "gpio", |
92105bb7 TL |
1838 | .suspend = omap_gpio_suspend, |
1839 | .resume = omap_gpio_resume, | |
1840 | }; | |
1841 | ||
1842 | static struct sys_device omap_gpio_device = { | |
1843 | .id = 0, | |
1844 | .cls = &omap_gpio_sysclass, | |
1845 | }; | |
3ac4fa99 JY |
1846 | |
1847 | #endif | |
1848 | ||
44169075 SS |
1849 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
1850 | defined(CONFIG_ARCH_OMAP4) | |
3ac4fa99 JY |
1851 | |
1852 | static int workaround_enabled; | |
1853 | ||
1854 | void omap2_gpio_prepare_for_retention(void) | |
1855 | { | |
1856 | int i, c = 0; | |
1857 | ||
1858 | /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious | |
1859 | * IRQs will be generated. See OMAP2420 Errata item 1.101. */ | |
1860 | for (i = 0; i < gpio_bank_count; i++) { | |
1861 | struct gpio_bank *bank = &gpio_bank[i]; | |
1862 | u32 l1, l2; | |
1863 | ||
1864 | if (!(bank->enabled_non_wakeup_gpios)) | |
1865 | continue; | |
44169075 SS |
1866 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
1867 | defined(CONFIG_ARCH_OMAP4) | |
3ac4fa99 JY |
1868 | bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
1869 | l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1870 | l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
5492fb1a | 1871 | #endif |
3ac4fa99 JY |
1872 | bank->saved_fallingdetect = l1; |
1873 | bank->saved_risingdetect = l2; | |
1874 | l1 &= ~bank->enabled_non_wakeup_gpios; | |
1875 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
44169075 SS |
1876 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
1877 | defined(CONFIG_ARCH_OMAP4) | |
3ac4fa99 JY |
1878 | __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT); |
1879 | __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
5492fb1a | 1880 | #endif |
3ac4fa99 JY |
1881 | c++; |
1882 | } | |
1883 | if (!c) { | |
1884 | workaround_enabled = 0; | |
1885 | return; | |
1886 | } | |
1887 | workaround_enabled = 1; | |
1888 | } | |
1889 | ||
1890 | void omap2_gpio_resume_after_retention(void) | |
1891 | { | |
1892 | int i; | |
1893 | ||
1894 | if (!workaround_enabled) | |
1895 | return; | |
1896 | for (i = 0; i < gpio_bank_count; i++) { | |
1897 | struct gpio_bank *bank = &gpio_bank[i]; | |
1898 | u32 l; | |
1899 | ||
1900 | if (!(bank->enabled_non_wakeup_gpios)) | |
1901 | continue; | |
44169075 SS |
1902 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
1903 | defined(CONFIG_ARCH_OMAP4) | |
3ac4fa99 JY |
1904 | __raw_writel(bank->saved_fallingdetect, |
1905 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1906 | __raw_writel(bank->saved_risingdetect, | |
1907 | bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
5492fb1a | 1908 | #endif |
3ac4fa99 JY |
1909 | /* Check if any of the non-wakeup interrupt GPIOs have changed |
1910 | * state. If so, generate an IRQ by software. This is | |
1911 | * horribly racy, but it's the best we can do to work around | |
1912 | * this silicon bug. */ | |
44169075 SS |
1913 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
1914 | defined(CONFIG_ARCH_OMAP4) | |
3ac4fa99 | 1915 | l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
5492fb1a | 1916 | #endif |
3ac4fa99 JY |
1917 | l ^= bank->saved_datain; |
1918 | l &= bank->non_wakeup_gpios; | |
1919 | if (l) { | |
1920 | u32 old0, old1; | |
44169075 SS |
1921 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
1922 | defined(CONFIG_ARCH_OMAP4) | |
3ac4fa99 JY |
1923 | old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); |
1924 | old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
1925 | __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
1926 | __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
1927 | __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
1928 | __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
5492fb1a | 1929 | #endif |
3ac4fa99 JY |
1930 | } |
1931 | } | |
1932 | ||
1933 | } | |
1934 | ||
92105bb7 TL |
1935 | #endif |
1936 | ||
5e1c5ff4 TL |
1937 | /* |
1938 | * This may get called early from board specific init | |
1a8bfa1e | 1939 | * for boards that have interrupts routed via FPGA. |
5e1c5ff4 | 1940 | */ |
277d58ef | 1941 | int __init omap_gpio_init(void) |
5e1c5ff4 TL |
1942 | { |
1943 | if (!initialized) | |
1944 | return _omap_gpio_init(); | |
1945 | else | |
1946 | return 0; | |
1947 | } | |
1948 | ||
92105bb7 TL |
1949 | static int __init omap_gpio_sysinit(void) |
1950 | { | |
1951 | int ret = 0; | |
1952 | ||
1953 | if (!initialized) | |
1954 | ret = _omap_gpio_init(); | |
1955 | ||
11a78b79 DB |
1956 | mpuio_init(); |
1957 | ||
44169075 SS |
1958 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ |
1959 | defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4) | |
5492fb1a | 1960 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) { |
92105bb7 TL |
1961 | if (ret == 0) { |
1962 | ret = sysdev_class_register(&omap_gpio_sysclass); | |
1963 | if (ret == 0) | |
1964 | ret = sysdev_register(&omap_gpio_device); | |
1965 | } | |
1966 | } | |
1967 | #endif | |
1968 | ||
1969 | return ret; | |
1970 | } | |
1971 | ||
92105bb7 | 1972 | arch_initcall(omap_gpio_sysinit); |
b9772a22 DB |
1973 | |
1974 | ||
1975 | #ifdef CONFIG_DEBUG_FS | |
1976 | ||
1977 | #include <linux/debugfs.h> | |
1978 | #include <linux/seq_file.h> | |
1979 | ||
b9772a22 DB |
1980 | static int dbg_gpio_show(struct seq_file *s, void *unused) |
1981 | { | |
1982 | unsigned i, j, gpio; | |
1983 | ||
1984 | for (i = 0, gpio = 0; i < gpio_bank_count; i++) { | |
1985 | struct gpio_bank *bank = gpio_bank + i; | |
1986 | unsigned bankwidth = 16; | |
1987 | u32 mask = 1; | |
1988 | ||
e5c56ed3 | 1989 | if (bank_is_mpuio(bank)) |
b9772a22 | 1990 | gpio = OMAP_MPUIO(0); |
56739a69 ZM |
1991 | else if (cpu_class_is_omap2() || cpu_is_omap730() || |
1992 | cpu_is_omap850()) | |
b9772a22 DB |
1993 | bankwidth = 32; |
1994 | ||
1995 | for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { | |
1996 | unsigned irq, value, is_in, irqstat; | |
52e31344 | 1997 | const char *label; |
b9772a22 | 1998 | |
52e31344 DB |
1999 | label = gpiochip_is_requested(&bank->chip, j); |
2000 | if (!label) | |
b9772a22 DB |
2001 | continue; |
2002 | ||
2003 | irq = bank->virtual_irq_start + j; | |
0b84b5ca | 2004 | value = gpio_get_value(gpio); |
b9772a22 DB |
2005 | is_in = gpio_is_input(bank, mask); |
2006 | ||
e5c56ed3 | 2007 | if (bank_is_mpuio(bank)) |
52e31344 | 2008 | seq_printf(s, "MPUIO %2d ", j); |
b9772a22 | 2009 | else |
52e31344 | 2010 | seq_printf(s, "GPIO %3d ", gpio); |
21c867f1 | 2011 | seq_printf(s, "(%-20.20s): %s %s", |
52e31344 | 2012 | label, |
b9772a22 DB |
2013 | is_in ? "in " : "out", |
2014 | value ? "hi" : "lo"); | |
2015 | ||
52e31344 DB |
2016 | /* FIXME for at least omap2, show pullup/pulldown state */ |
2017 | ||
b9772a22 | 2018 | irqstat = irq_desc[irq].status; |
3a26e331 | 2019 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ |
44169075 | 2020 | defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4) |
b9772a22 DB |
2021 | if (is_in && ((bank->suspend_wakeup & mask) |
2022 | || irqstat & IRQ_TYPE_SENSE_MASK)) { | |
2023 | char *trigger = NULL; | |
2024 | ||
2025 | switch (irqstat & IRQ_TYPE_SENSE_MASK) { | |
2026 | case IRQ_TYPE_EDGE_FALLING: | |
2027 | trigger = "falling"; | |
2028 | break; | |
2029 | case IRQ_TYPE_EDGE_RISING: | |
2030 | trigger = "rising"; | |
2031 | break; | |
2032 | case IRQ_TYPE_EDGE_BOTH: | |
2033 | trigger = "bothedge"; | |
2034 | break; | |
2035 | case IRQ_TYPE_LEVEL_LOW: | |
2036 | trigger = "low"; | |
2037 | break; | |
2038 | case IRQ_TYPE_LEVEL_HIGH: | |
2039 | trigger = "high"; | |
2040 | break; | |
2041 | case IRQ_TYPE_NONE: | |
52e31344 | 2042 | trigger = "(?)"; |
b9772a22 DB |
2043 | break; |
2044 | } | |
52e31344 | 2045 | seq_printf(s, ", irq-%d %-8s%s", |
b9772a22 DB |
2046 | irq, trigger, |
2047 | (bank->suspend_wakeup & mask) | |
2048 | ? " wakeup" : ""); | |
2049 | } | |
3a26e331 | 2050 | #endif |
b9772a22 DB |
2051 | seq_printf(s, "\n"); |
2052 | } | |
2053 | ||
e5c56ed3 | 2054 | if (bank_is_mpuio(bank)) { |
b9772a22 DB |
2055 | seq_printf(s, "\n"); |
2056 | gpio = 0; | |
2057 | } | |
2058 | } | |
2059 | return 0; | |
2060 | } | |
2061 | ||
2062 | static int dbg_gpio_open(struct inode *inode, struct file *file) | |
2063 | { | |
e5c56ed3 | 2064 | return single_open(file, dbg_gpio_show, &inode->i_private); |
b9772a22 DB |
2065 | } |
2066 | ||
2067 | static const struct file_operations debug_fops = { | |
2068 | .open = dbg_gpio_open, | |
2069 | .read = seq_read, | |
2070 | .llseek = seq_lseek, | |
2071 | .release = single_release, | |
2072 | }; | |
2073 | ||
2074 | static int __init omap_gpio_debuginit(void) | |
2075 | { | |
e5c56ed3 DB |
2076 | (void) debugfs_create_file("omap_gpio", S_IRUGO, |
2077 | NULL, NULL, &debug_fops); | |
b9772a22 DB |
2078 | return 0; |
2079 | } | |
2080 | late_initcall(omap_gpio_debuginit); | |
2081 | #endif |