Commit | Line | Data |
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5e1c5ff4 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/gpio.c | |
3 | * | |
4 | * Support functions for OMAP GPIO | |
5 | * | |
92105bb7 | 6 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 7 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 TL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
5e1c5ff4 TL |
14 | #include <linux/init.h> |
15 | #include <linux/module.h> | |
5e1c5ff4 | 16 | #include <linux/interrupt.h> |
92105bb7 TL |
17 | #include <linux/sysdev.h> |
18 | #include <linux/err.h> | |
f8ce2547 | 19 | #include <linux/clk.h> |
5e1c5ff4 TL |
20 | |
21 | #include <asm/hardware.h> | |
22 | #include <asm/irq.h> | |
23 | #include <asm/arch/irqs.h> | |
24 | #include <asm/arch/gpio.h> | |
25 | #include <asm/mach/irq.h> | |
26 | ||
27 | #include <asm/io.h> | |
28 | ||
29 | /* | |
30 | * OMAP1510 GPIO registers | |
31 | */ | |
92105bb7 | 32 | #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000 |
5e1c5ff4 TL |
33 | #define OMAP1510_GPIO_DATA_INPUT 0x00 |
34 | #define OMAP1510_GPIO_DATA_OUTPUT 0x04 | |
35 | #define OMAP1510_GPIO_DIR_CONTROL 0x08 | |
36 | #define OMAP1510_GPIO_INT_CONTROL 0x0c | |
37 | #define OMAP1510_GPIO_INT_MASK 0x10 | |
38 | #define OMAP1510_GPIO_INT_STATUS 0x14 | |
39 | #define OMAP1510_GPIO_PIN_CONTROL 0x18 | |
40 | ||
41 | #define OMAP1510_IH_GPIO_BASE 64 | |
42 | ||
43 | /* | |
44 | * OMAP1610 specific GPIO registers | |
45 | */ | |
92105bb7 TL |
46 | #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400 |
47 | #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00 | |
48 | #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400 | |
49 | #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00 | |
5e1c5ff4 TL |
50 | #define OMAP1610_GPIO_REVISION 0x0000 |
51 | #define OMAP1610_GPIO_SYSCONFIG 0x0010 | |
52 | #define OMAP1610_GPIO_SYSSTATUS 0x0014 | |
53 | #define OMAP1610_GPIO_IRQSTATUS1 0x0018 | |
54 | #define OMAP1610_GPIO_IRQENABLE1 0x001c | |
92105bb7 | 55 | #define OMAP1610_GPIO_WAKEUPENABLE 0x0028 |
5e1c5ff4 TL |
56 | #define OMAP1610_GPIO_DATAIN 0x002c |
57 | #define OMAP1610_GPIO_DATAOUT 0x0030 | |
58 | #define OMAP1610_GPIO_DIRECTION 0x0034 | |
59 | #define OMAP1610_GPIO_EDGE_CTRL1 0x0038 | |
60 | #define OMAP1610_GPIO_EDGE_CTRL2 0x003c | |
61 | #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c | |
92105bb7 | 62 | #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8 |
5e1c5ff4 TL |
63 | #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0 |
64 | #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc | |
92105bb7 | 65 | #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8 |
5e1c5ff4 TL |
66 | #define OMAP1610_GPIO_SET_DATAOUT 0x00f0 |
67 | ||
68 | /* | |
69 | * OMAP730 specific GPIO registers | |
70 | */ | |
92105bb7 TL |
71 | #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000 |
72 | #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800 | |
73 | #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000 | |
74 | #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800 | |
75 | #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000 | |
76 | #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800 | |
5e1c5ff4 TL |
77 | #define OMAP730_GPIO_DATA_INPUT 0x00 |
78 | #define OMAP730_GPIO_DATA_OUTPUT 0x04 | |
79 | #define OMAP730_GPIO_DIR_CONTROL 0x08 | |
80 | #define OMAP730_GPIO_INT_CONTROL 0x0c | |
81 | #define OMAP730_GPIO_INT_MASK 0x10 | |
82 | #define OMAP730_GPIO_INT_STATUS 0x14 | |
83 | ||
92105bb7 TL |
84 | /* |
85 | * omap24xx specific GPIO registers | |
86 | */ | |
56a25641 SMK |
87 | #define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000 |
88 | #define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000 | |
89 | #define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000 | |
90 | #define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000 | |
91 | ||
92 | #define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000 | |
93 | #define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000 | |
94 | #define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000 | |
95 | #define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000 | |
96 | #define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000 | |
97 | ||
92105bb7 TL |
98 | #define OMAP24XX_GPIO_REVISION 0x0000 |
99 | #define OMAP24XX_GPIO_SYSCONFIG 0x0010 | |
100 | #define OMAP24XX_GPIO_SYSSTATUS 0x0014 | |
101 | #define OMAP24XX_GPIO_IRQSTATUS1 0x0018 | |
bee7930f HD |
102 | #define OMAP24XX_GPIO_IRQSTATUS2 0x0028 |
103 | #define OMAP24XX_GPIO_IRQENABLE2 0x002c | |
92105bb7 TL |
104 | #define OMAP24XX_GPIO_IRQENABLE1 0x001c |
105 | #define OMAP24XX_GPIO_CTRL 0x0030 | |
106 | #define OMAP24XX_GPIO_OE 0x0034 | |
107 | #define OMAP24XX_GPIO_DATAIN 0x0038 | |
108 | #define OMAP24XX_GPIO_DATAOUT 0x003c | |
109 | #define OMAP24XX_GPIO_LEVELDETECT0 0x0040 | |
110 | #define OMAP24XX_GPIO_LEVELDETECT1 0x0044 | |
111 | #define OMAP24XX_GPIO_RISINGDETECT 0x0048 | |
112 | #define OMAP24XX_GPIO_FALLINGDETECT 0x004c | |
5eb3bb9c KH |
113 | #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 |
114 | #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 | |
92105bb7 TL |
115 | #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 |
116 | #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 | |
117 | #define OMAP24XX_GPIO_CLEARWKUENA 0x0080 | |
118 | #define OMAP24XX_GPIO_SETWKUENA 0x0084 | |
119 | #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 | |
120 | #define OMAP24XX_GPIO_SETDATAOUT 0x0094 | |
121 | ||
5492fb1a SMK |
122 | /* |
123 | * omap34xx specific GPIO registers | |
124 | */ | |
125 | ||
126 | #define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000 | |
127 | #define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000 | |
128 | #define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000 | |
129 | #define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000 | |
130 | #define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000 | |
131 | #define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000 | |
132 | ||
133 | ||
5e1c5ff4 | 134 | struct gpio_bank { |
92105bb7 | 135 | void __iomem *base; |
5e1c5ff4 TL |
136 | u16 irq; |
137 | u16 virtual_irq_start; | |
92105bb7 | 138 | int method; |
5492fb1a | 139 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
140 | u32 suspend_wakeup; |
141 | u32 saved_wakeup; | |
3ac4fa99 | 142 | #endif |
5492fb1a | 143 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
144 | u32 non_wakeup_gpios; |
145 | u32 enabled_non_wakeup_gpios; | |
146 | ||
147 | u32 saved_datain; | |
148 | u32 saved_fallingdetect; | |
149 | u32 saved_risingdetect; | |
150 | #endif | |
5e1c5ff4 | 151 | spinlock_t lock; |
52e31344 | 152 | struct gpio_chip chip; |
5e1c5ff4 TL |
153 | }; |
154 | ||
155 | #define METHOD_MPUIO 0 | |
156 | #define METHOD_GPIO_1510 1 | |
157 | #define METHOD_GPIO_1610 2 | |
158 | #define METHOD_GPIO_730 3 | |
92105bb7 | 159 | #define METHOD_GPIO_24XX 4 |
5e1c5ff4 | 160 | |
92105bb7 | 161 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 TL |
162 | static struct gpio_bank gpio_bank_1610[5] = { |
163 | { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO}, | |
164 | { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 }, | |
165 | { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 }, | |
166 | { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 }, | |
167 | { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 }, | |
168 | }; | |
169 | #endif | |
170 | ||
1a8bfa1e | 171 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 TL |
172 | static struct gpio_bank gpio_bank_1510[2] = { |
173 | { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, | |
174 | { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 } | |
175 | }; | |
176 | #endif | |
177 | ||
178 | #ifdef CONFIG_ARCH_OMAP730 | |
179 | static struct gpio_bank gpio_bank_730[7] = { | |
180 | { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, | |
181 | { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 }, | |
182 | { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 }, | |
183 | { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 }, | |
184 | { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 }, | |
185 | { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 }, | |
186 | { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 }, | |
187 | }; | |
188 | #endif | |
189 | ||
92105bb7 | 190 | #ifdef CONFIG_ARCH_OMAP24XX |
56a25641 SMK |
191 | |
192 | static struct gpio_bank gpio_bank_242x[4] = { | |
193 | { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, | |
194 | { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, | |
195 | { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, | |
196 | { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, | |
92105bb7 | 197 | }; |
56a25641 SMK |
198 | |
199 | static struct gpio_bank gpio_bank_243x[5] = { | |
200 | { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, | |
201 | { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, | |
202 | { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, | |
203 | { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, | |
204 | { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX }, | |
205 | }; | |
206 | ||
92105bb7 TL |
207 | #endif |
208 | ||
5492fb1a SMK |
209 | #ifdef CONFIG_ARCH_OMAP34XX |
210 | static struct gpio_bank gpio_bank_34xx[6] = { | |
211 | { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, | |
212 | { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, | |
213 | { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, | |
214 | { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, | |
215 | { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX }, | |
216 | { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX }, | |
217 | }; | |
218 | ||
219 | #endif | |
220 | ||
5e1c5ff4 TL |
221 | static struct gpio_bank *gpio_bank; |
222 | static int gpio_bank_count; | |
223 | ||
224 | static inline struct gpio_bank *get_gpio_bank(int gpio) | |
225 | { | |
6e60e79a | 226 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
227 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
228 | return &gpio_bank[0]; | |
229 | return &gpio_bank[1]; | |
230 | } | |
5e1c5ff4 TL |
231 | if (cpu_is_omap16xx()) { |
232 | if (OMAP_GPIO_IS_MPUIO(gpio)) | |
233 | return &gpio_bank[0]; | |
234 | return &gpio_bank[1 + (gpio >> 4)]; | |
235 | } | |
5e1c5ff4 TL |
236 | if (cpu_is_omap730()) { |
237 | if (OMAP_GPIO_IS_MPUIO(gpio)) | |
238 | return &gpio_bank[0]; | |
239 | return &gpio_bank[1 + (gpio >> 5)]; | |
240 | } | |
92105bb7 TL |
241 | if (cpu_is_omap24xx()) |
242 | return &gpio_bank[gpio >> 5]; | |
5492fb1a SMK |
243 | if (cpu_is_omap34xx()) |
244 | return &gpio_bank[gpio >> 5]; | |
5e1c5ff4 TL |
245 | } |
246 | ||
247 | static inline int get_gpio_index(int gpio) | |
248 | { | |
249 | if (cpu_is_omap730()) | |
250 | return gpio & 0x1f; | |
92105bb7 TL |
251 | if (cpu_is_omap24xx()) |
252 | return gpio & 0x1f; | |
5492fb1a SMK |
253 | if (cpu_is_omap34xx()) |
254 | return gpio & 0x1f; | |
92105bb7 | 255 | return gpio & 0x0f; |
5e1c5ff4 TL |
256 | } |
257 | ||
258 | static inline int gpio_valid(int gpio) | |
259 | { | |
260 | if (gpio < 0) | |
261 | return -1; | |
d11ac979 | 262 | if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) { |
193e68be | 263 | if (gpio >= OMAP_MAX_GPIO_LINES + 16) |
5e1c5ff4 TL |
264 | return -1; |
265 | return 0; | |
266 | } | |
6e60e79a | 267 | if (cpu_is_omap15xx() && gpio < 16) |
5e1c5ff4 | 268 | return 0; |
5e1c5ff4 TL |
269 | if ((cpu_is_omap16xx()) && gpio < 64) |
270 | return 0; | |
5e1c5ff4 TL |
271 | if (cpu_is_omap730() && gpio < 192) |
272 | return 0; | |
92105bb7 TL |
273 | if (cpu_is_omap24xx() && gpio < 128) |
274 | return 0; | |
5492fb1a SMK |
275 | if (cpu_is_omap34xx() && gpio < 160) |
276 | return 0; | |
5e1c5ff4 TL |
277 | return -1; |
278 | } | |
279 | ||
280 | static int check_gpio(int gpio) | |
281 | { | |
282 | if (unlikely(gpio_valid(gpio)) < 0) { | |
283 | printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio); | |
284 | dump_stack(); | |
285 | return -1; | |
286 | } | |
287 | return 0; | |
288 | } | |
289 | ||
290 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |
291 | { | |
92105bb7 | 292 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
293 | u32 l; |
294 | ||
295 | switch (bank->method) { | |
e5c56ed3 | 296 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
297 | case METHOD_MPUIO: |
298 | reg += OMAP_MPUIO_IO_CNTL; | |
299 | break; | |
e5c56ed3 DB |
300 | #endif |
301 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
302 | case METHOD_GPIO_1510: |
303 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
304 | break; | |
e5c56ed3 DB |
305 | #endif |
306 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
307 | case METHOD_GPIO_1610: |
308 | reg += OMAP1610_GPIO_DIRECTION; | |
309 | break; | |
e5c56ed3 DB |
310 | #endif |
311 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
312 | case METHOD_GPIO_730: |
313 | reg += OMAP730_GPIO_DIR_CONTROL; | |
314 | break; | |
e5c56ed3 | 315 | #endif |
5492fb1a | 316 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
317 | case METHOD_GPIO_24XX: |
318 | reg += OMAP24XX_GPIO_OE; | |
319 | break; | |
e5c56ed3 DB |
320 | #endif |
321 | default: | |
322 | WARN_ON(1); | |
323 | return; | |
5e1c5ff4 TL |
324 | } |
325 | l = __raw_readl(reg); | |
326 | if (is_input) | |
327 | l |= 1 << gpio; | |
328 | else | |
329 | l &= ~(1 << gpio); | |
330 | __raw_writel(l, reg); | |
331 | } | |
332 | ||
333 | void omap_set_gpio_direction(int gpio, int is_input) | |
334 | { | |
335 | struct gpio_bank *bank; | |
a6472533 | 336 | unsigned long flags; |
5e1c5ff4 TL |
337 | |
338 | if (check_gpio(gpio) < 0) | |
339 | return; | |
340 | bank = get_gpio_bank(gpio); | |
a6472533 | 341 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 | 342 | _set_gpio_direction(bank, get_gpio_index(gpio), is_input); |
a6472533 | 343 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
344 | } |
345 | ||
346 | static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) | |
347 | { | |
92105bb7 | 348 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
349 | u32 l = 0; |
350 | ||
351 | switch (bank->method) { | |
e5c56ed3 | 352 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
353 | case METHOD_MPUIO: |
354 | reg += OMAP_MPUIO_OUTPUT; | |
355 | l = __raw_readl(reg); | |
356 | if (enable) | |
357 | l |= 1 << gpio; | |
358 | else | |
359 | l &= ~(1 << gpio); | |
360 | break; | |
e5c56ed3 DB |
361 | #endif |
362 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
363 | case METHOD_GPIO_1510: |
364 | reg += OMAP1510_GPIO_DATA_OUTPUT; | |
365 | l = __raw_readl(reg); | |
366 | if (enable) | |
367 | l |= 1 << gpio; | |
368 | else | |
369 | l &= ~(1 << gpio); | |
370 | break; | |
e5c56ed3 DB |
371 | #endif |
372 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
373 | case METHOD_GPIO_1610: |
374 | if (enable) | |
375 | reg += OMAP1610_GPIO_SET_DATAOUT; | |
376 | else | |
377 | reg += OMAP1610_GPIO_CLEAR_DATAOUT; | |
378 | l = 1 << gpio; | |
379 | break; | |
e5c56ed3 DB |
380 | #endif |
381 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
382 | case METHOD_GPIO_730: |
383 | reg += OMAP730_GPIO_DATA_OUTPUT; | |
384 | l = __raw_readl(reg); | |
385 | if (enable) | |
386 | l |= 1 << gpio; | |
387 | else | |
388 | l &= ~(1 << gpio); | |
389 | break; | |
e5c56ed3 | 390 | #endif |
5492fb1a | 391 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
392 | case METHOD_GPIO_24XX: |
393 | if (enable) | |
394 | reg += OMAP24XX_GPIO_SETDATAOUT; | |
395 | else | |
396 | reg += OMAP24XX_GPIO_CLEARDATAOUT; | |
397 | l = 1 << gpio; | |
398 | break; | |
e5c56ed3 | 399 | #endif |
5e1c5ff4 | 400 | default: |
e5c56ed3 | 401 | WARN_ON(1); |
5e1c5ff4 TL |
402 | return; |
403 | } | |
404 | __raw_writel(l, reg); | |
405 | } | |
406 | ||
407 | void omap_set_gpio_dataout(int gpio, int enable) | |
408 | { | |
409 | struct gpio_bank *bank; | |
a6472533 | 410 | unsigned long flags; |
5e1c5ff4 TL |
411 | |
412 | if (check_gpio(gpio) < 0) | |
413 | return; | |
414 | bank = get_gpio_bank(gpio); | |
a6472533 | 415 | spin_lock_irqsave(&bank->lock, flags); |
5e1c5ff4 | 416 | _set_gpio_dataout(bank, get_gpio_index(gpio), enable); |
a6472533 | 417 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
418 | } |
419 | ||
420 | int omap_get_gpio_datain(int gpio) | |
421 | { | |
422 | struct gpio_bank *bank; | |
92105bb7 | 423 | void __iomem *reg; |
5e1c5ff4 TL |
424 | |
425 | if (check_gpio(gpio) < 0) | |
e5c56ed3 | 426 | return -EINVAL; |
5e1c5ff4 TL |
427 | bank = get_gpio_bank(gpio); |
428 | reg = bank->base; | |
429 | switch (bank->method) { | |
e5c56ed3 | 430 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
431 | case METHOD_MPUIO: |
432 | reg += OMAP_MPUIO_INPUT_LATCH; | |
433 | break; | |
e5c56ed3 DB |
434 | #endif |
435 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
436 | case METHOD_GPIO_1510: |
437 | reg += OMAP1510_GPIO_DATA_INPUT; | |
438 | break; | |
e5c56ed3 DB |
439 | #endif |
440 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
441 | case METHOD_GPIO_1610: |
442 | reg += OMAP1610_GPIO_DATAIN; | |
443 | break; | |
e5c56ed3 DB |
444 | #endif |
445 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
446 | case METHOD_GPIO_730: |
447 | reg += OMAP730_GPIO_DATA_INPUT; | |
448 | break; | |
e5c56ed3 | 449 | #endif |
5492fb1a | 450 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
451 | case METHOD_GPIO_24XX: |
452 | reg += OMAP24XX_GPIO_DATAIN; | |
453 | break; | |
e5c56ed3 | 454 | #endif |
5e1c5ff4 | 455 | default: |
e5c56ed3 | 456 | return -EINVAL; |
5e1c5ff4 | 457 | } |
92105bb7 TL |
458 | return (__raw_readl(reg) |
459 | & (1 << get_gpio_index(gpio))) != 0; | |
5e1c5ff4 TL |
460 | } |
461 | ||
92105bb7 TL |
462 | #define MOD_REG_BIT(reg, bit_mask, set) \ |
463 | do { \ | |
464 | int l = __raw_readl(base + reg); \ | |
465 | if (set) l |= bit_mask; \ | |
466 | else l &= ~bit_mask; \ | |
467 | __raw_writel(l, base + reg); \ | |
468 | } while(0) | |
469 | ||
5eb3bb9c KH |
470 | void omap_set_gpio_debounce(int gpio, int enable) |
471 | { | |
472 | struct gpio_bank *bank; | |
473 | void __iomem *reg; | |
474 | u32 val, l = 1 << get_gpio_index(gpio); | |
475 | ||
476 | if (cpu_class_is_omap1()) | |
477 | return; | |
478 | ||
479 | bank = get_gpio_bank(gpio); | |
480 | reg = bank->base; | |
481 | ||
482 | reg += OMAP24XX_GPIO_DEBOUNCE_EN; | |
483 | val = __raw_readl(reg); | |
484 | ||
485 | if (enable) | |
486 | val |= l; | |
487 | else | |
488 | val &= ~l; | |
489 | ||
490 | __raw_writel(val, reg); | |
491 | } | |
492 | EXPORT_SYMBOL(omap_set_gpio_debounce); | |
493 | ||
494 | void omap_set_gpio_debounce_time(int gpio, int enc_time) | |
495 | { | |
496 | struct gpio_bank *bank; | |
497 | void __iomem *reg; | |
498 | ||
499 | if (cpu_class_is_omap1()) | |
500 | return; | |
501 | ||
502 | bank = get_gpio_bank(gpio); | |
503 | reg = bank->base; | |
504 | ||
505 | enc_time &= 0xff; | |
506 | reg += OMAP24XX_GPIO_DEBOUNCE_VAL; | |
507 | __raw_writel(enc_time, reg); | |
508 | } | |
509 | EXPORT_SYMBOL(omap_set_gpio_debounce_time); | |
510 | ||
5492fb1a | 511 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
5eb3bb9c KH |
512 | static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, |
513 | int trigger) | |
5e1c5ff4 | 514 | { |
3ac4fa99 | 515 | void __iomem *base = bank->base; |
92105bb7 TL |
516 | u32 gpio_bit = 1 << gpio; |
517 | ||
518 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, | |
6e60e79a | 519 | trigger & __IRQT_LOWLVL); |
92105bb7 | 520 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, |
6e60e79a | 521 | trigger & __IRQT_HIGHLVL); |
92105bb7 | 522 | MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, |
6e60e79a | 523 | trigger & __IRQT_RISEDGE); |
92105bb7 | 524 | MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, |
6e60e79a | 525 | trigger & __IRQT_FALEDGE); |
5eb3bb9c | 526 | |
3ac4fa99 JY |
527 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { |
528 | if (trigger != 0) | |
5eb3bb9c KH |
529 | __raw_writel(1 << gpio, bank->base |
530 | + OMAP24XX_GPIO_SETWKUENA); | |
3ac4fa99 | 531 | else |
5eb3bb9c KH |
532 | __raw_writel(1 << gpio, bank->base |
533 | + OMAP24XX_GPIO_CLEARWKUENA); | |
3ac4fa99 JY |
534 | } else { |
535 | if (trigger != 0) | |
536 | bank->enabled_non_wakeup_gpios |= gpio_bit; | |
537 | else | |
538 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
539 | } | |
5eb3bb9c KH |
540 | |
541 | /* | |
542 | * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only | |
543 | * level triggering requested. | |
544 | */ | |
92105bb7 | 545 | } |
3ac4fa99 | 546 | #endif |
92105bb7 TL |
547 | |
548 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) | |
549 | { | |
550 | void __iomem *reg = bank->base; | |
551 | u32 l = 0; | |
5e1c5ff4 TL |
552 | |
553 | switch (bank->method) { | |
e5c56ed3 | 554 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
555 | case METHOD_MPUIO: |
556 | reg += OMAP_MPUIO_GPIO_INT_EDGE; | |
557 | l = __raw_readl(reg); | |
6e60e79a | 558 | if (trigger & __IRQT_RISEDGE) |
5e1c5ff4 | 559 | l |= 1 << gpio; |
6e60e79a | 560 | else if (trigger & __IRQT_FALEDGE) |
5e1c5ff4 | 561 | l &= ~(1 << gpio); |
92105bb7 TL |
562 | else |
563 | goto bad; | |
5e1c5ff4 | 564 | break; |
e5c56ed3 DB |
565 | #endif |
566 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
567 | case METHOD_GPIO_1510: |
568 | reg += OMAP1510_GPIO_INT_CONTROL; | |
569 | l = __raw_readl(reg); | |
6e60e79a | 570 | if (trigger & __IRQT_RISEDGE) |
5e1c5ff4 | 571 | l |= 1 << gpio; |
6e60e79a | 572 | else if (trigger & __IRQT_FALEDGE) |
5e1c5ff4 | 573 | l &= ~(1 << gpio); |
92105bb7 TL |
574 | else |
575 | goto bad; | |
5e1c5ff4 | 576 | break; |
e5c56ed3 | 577 | #endif |
3ac4fa99 | 578 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 579 | case METHOD_GPIO_1610: |
5e1c5ff4 TL |
580 | if (gpio & 0x08) |
581 | reg += OMAP1610_GPIO_EDGE_CTRL2; | |
582 | else | |
583 | reg += OMAP1610_GPIO_EDGE_CTRL1; | |
584 | gpio &= 0x07; | |
585 | l = __raw_readl(reg); | |
586 | l &= ~(3 << (gpio << 1)); | |
6e60e79a TL |
587 | if (trigger & __IRQT_RISEDGE) |
588 | l |= 2 << (gpio << 1); | |
589 | if (trigger & __IRQT_FALEDGE) | |
590 | l |= 1 << (gpio << 1); | |
3ac4fa99 JY |
591 | if (trigger) |
592 | /* Enable wake-up during idle for dynamic tick */ | |
593 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA); | |
594 | else | |
595 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); | |
5e1c5ff4 | 596 | break; |
3ac4fa99 JY |
597 | #endif |
598 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
599 | case METHOD_GPIO_730: |
600 | reg += OMAP730_GPIO_INT_CONTROL; | |
601 | l = __raw_readl(reg); | |
6e60e79a | 602 | if (trigger & __IRQT_RISEDGE) |
5e1c5ff4 | 603 | l |= 1 << gpio; |
6e60e79a | 604 | else if (trigger & __IRQT_FALEDGE) |
5e1c5ff4 | 605 | l &= ~(1 << gpio); |
92105bb7 TL |
606 | else |
607 | goto bad; | |
608 | break; | |
3ac4fa99 | 609 | #endif |
5492fb1a | 610 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 | 611 | case METHOD_GPIO_24XX: |
3ac4fa99 | 612 | set_24xx_gpio_triggering(bank, gpio, trigger); |
5e1c5ff4 | 613 | break; |
3ac4fa99 | 614 | #endif |
5e1c5ff4 | 615 | default: |
92105bb7 | 616 | goto bad; |
5e1c5ff4 | 617 | } |
92105bb7 TL |
618 | __raw_writel(l, reg); |
619 | return 0; | |
620 | bad: | |
621 | return -EINVAL; | |
5e1c5ff4 TL |
622 | } |
623 | ||
92105bb7 | 624 | static int gpio_irq_type(unsigned irq, unsigned type) |
5e1c5ff4 TL |
625 | { |
626 | struct gpio_bank *bank; | |
92105bb7 TL |
627 | unsigned gpio; |
628 | int retval; | |
a6472533 | 629 | unsigned long flags; |
92105bb7 | 630 | |
5492fb1a | 631 | if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE) |
92105bb7 TL |
632 | gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); |
633 | else | |
634 | gpio = irq - IH_GPIO_BASE; | |
5e1c5ff4 TL |
635 | |
636 | if (check_gpio(gpio) < 0) | |
92105bb7 TL |
637 | return -EINVAL; |
638 | ||
e5c56ed3 | 639 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 640 | return -EINVAL; |
e5c56ed3 DB |
641 | |
642 | /* OMAP1 allows only only edge triggering */ | |
5492fb1a | 643 | if (!cpu_class_is_omap2() |
e5c56ed3 | 644 | && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) |
92105bb7 TL |
645 | return -EINVAL; |
646 | ||
58781016 | 647 | bank = get_irq_chip_data(irq); |
a6472533 | 648 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 649 | retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); |
b9772a22 DB |
650 | if (retval == 0) { |
651 | irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; | |
652 | irq_desc[irq].status |= type; | |
653 | } | |
a6472533 | 654 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 655 | return retval; |
5e1c5ff4 TL |
656 | } |
657 | ||
658 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
659 | { | |
92105bb7 | 660 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
661 | |
662 | switch (bank->method) { | |
e5c56ed3 | 663 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
664 | case METHOD_MPUIO: |
665 | /* MPUIO irqstatus is reset by reading the status register, | |
666 | * so do nothing here */ | |
667 | return; | |
e5c56ed3 DB |
668 | #endif |
669 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
670 | case METHOD_GPIO_1510: |
671 | reg += OMAP1510_GPIO_INT_STATUS; | |
672 | break; | |
e5c56ed3 DB |
673 | #endif |
674 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
675 | case METHOD_GPIO_1610: |
676 | reg += OMAP1610_GPIO_IRQSTATUS1; | |
677 | break; | |
e5c56ed3 DB |
678 | #endif |
679 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
680 | case METHOD_GPIO_730: |
681 | reg += OMAP730_GPIO_INT_STATUS; | |
682 | break; | |
e5c56ed3 | 683 | #endif |
5492fb1a | 684 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
685 | case METHOD_GPIO_24XX: |
686 | reg += OMAP24XX_GPIO_IRQSTATUS1; | |
687 | break; | |
e5c56ed3 | 688 | #endif |
5e1c5ff4 | 689 | default: |
e5c56ed3 | 690 | WARN_ON(1); |
5e1c5ff4 TL |
691 | return; |
692 | } | |
693 | __raw_writel(gpio_mask, reg); | |
bee7930f HD |
694 | |
695 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
5492fb1a SMK |
696 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
697 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
bee7930f | 698 | __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2); |
5492fb1a | 699 | #endif |
5e1c5ff4 TL |
700 | } |
701 | ||
702 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
703 | { | |
704 | _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio)); | |
705 | } | |
706 | ||
ea6dedd7 ID |
707 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
708 | { | |
709 | void __iomem *reg = bank->base; | |
99c47707 ID |
710 | int inv = 0; |
711 | u32 l; | |
712 | u32 mask; | |
ea6dedd7 ID |
713 | |
714 | switch (bank->method) { | |
e5c56ed3 | 715 | #ifdef CONFIG_ARCH_OMAP1 |
ea6dedd7 ID |
716 | case METHOD_MPUIO: |
717 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
99c47707 ID |
718 | mask = 0xffff; |
719 | inv = 1; | |
ea6dedd7 | 720 | break; |
e5c56ed3 DB |
721 | #endif |
722 | #ifdef CONFIG_ARCH_OMAP15XX | |
ea6dedd7 ID |
723 | case METHOD_GPIO_1510: |
724 | reg += OMAP1510_GPIO_INT_MASK; | |
99c47707 ID |
725 | mask = 0xffff; |
726 | inv = 1; | |
ea6dedd7 | 727 | break; |
e5c56ed3 DB |
728 | #endif |
729 | #ifdef CONFIG_ARCH_OMAP16XX | |
ea6dedd7 ID |
730 | case METHOD_GPIO_1610: |
731 | reg += OMAP1610_GPIO_IRQENABLE1; | |
99c47707 | 732 | mask = 0xffff; |
ea6dedd7 | 733 | break; |
e5c56ed3 DB |
734 | #endif |
735 | #ifdef CONFIG_ARCH_OMAP730 | |
ea6dedd7 ID |
736 | case METHOD_GPIO_730: |
737 | reg += OMAP730_GPIO_INT_MASK; | |
99c47707 ID |
738 | mask = 0xffffffff; |
739 | inv = 1; | |
ea6dedd7 | 740 | break; |
e5c56ed3 | 741 | #endif |
5492fb1a | 742 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
ea6dedd7 ID |
743 | case METHOD_GPIO_24XX: |
744 | reg += OMAP24XX_GPIO_IRQENABLE1; | |
99c47707 | 745 | mask = 0xffffffff; |
ea6dedd7 | 746 | break; |
e5c56ed3 | 747 | #endif |
ea6dedd7 | 748 | default: |
e5c56ed3 | 749 | WARN_ON(1); |
ea6dedd7 ID |
750 | return 0; |
751 | } | |
752 | ||
99c47707 ID |
753 | l = __raw_readl(reg); |
754 | if (inv) | |
755 | l = ~l; | |
756 | l &= mask; | |
757 | return l; | |
ea6dedd7 ID |
758 | } |
759 | ||
5e1c5ff4 TL |
760 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) |
761 | { | |
92105bb7 | 762 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
763 | u32 l; |
764 | ||
765 | switch (bank->method) { | |
e5c56ed3 | 766 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
767 | case METHOD_MPUIO: |
768 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
769 | l = __raw_readl(reg); | |
770 | if (enable) | |
771 | l &= ~(gpio_mask); | |
772 | else | |
773 | l |= gpio_mask; | |
774 | break; | |
e5c56ed3 DB |
775 | #endif |
776 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
777 | case METHOD_GPIO_1510: |
778 | reg += OMAP1510_GPIO_INT_MASK; | |
779 | l = __raw_readl(reg); | |
780 | if (enable) | |
781 | l &= ~(gpio_mask); | |
782 | else | |
783 | l |= gpio_mask; | |
784 | break; | |
e5c56ed3 DB |
785 | #endif |
786 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
787 | case METHOD_GPIO_1610: |
788 | if (enable) | |
789 | reg += OMAP1610_GPIO_SET_IRQENABLE1; | |
790 | else | |
791 | reg += OMAP1610_GPIO_CLEAR_IRQENABLE1; | |
792 | l = gpio_mask; | |
793 | break; | |
e5c56ed3 DB |
794 | #endif |
795 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
796 | case METHOD_GPIO_730: |
797 | reg += OMAP730_GPIO_INT_MASK; | |
798 | l = __raw_readl(reg); | |
799 | if (enable) | |
800 | l &= ~(gpio_mask); | |
801 | else | |
802 | l |= gpio_mask; | |
803 | break; | |
e5c56ed3 | 804 | #endif |
5492fb1a | 805 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
806 | case METHOD_GPIO_24XX: |
807 | if (enable) | |
808 | reg += OMAP24XX_GPIO_SETIRQENABLE1; | |
809 | else | |
810 | reg += OMAP24XX_GPIO_CLEARIRQENABLE1; | |
811 | l = gpio_mask; | |
812 | break; | |
e5c56ed3 | 813 | #endif |
5e1c5ff4 | 814 | default: |
e5c56ed3 | 815 | WARN_ON(1); |
5e1c5ff4 TL |
816 | return; |
817 | } | |
818 | __raw_writel(l, reg); | |
819 | } | |
820 | ||
821 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
822 | { | |
823 | _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable); | |
824 | } | |
825 | ||
92105bb7 TL |
826 | /* |
827 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
828 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
829 | * to the target, system will wake up always on GPIO events. While | |
830 | * system is running all registered GPIO interrupts need to have wake-up | |
831 | * enabled. When system is suspended, only selected GPIO interrupts need | |
832 | * to have wake-up enabled. | |
833 | */ | |
834 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
835 | { | |
a6472533 DB |
836 | unsigned long flags; |
837 | ||
92105bb7 | 838 | switch (bank->method) { |
3ac4fa99 | 839 | #ifdef CONFIG_ARCH_OMAP16XX |
11a78b79 | 840 | case METHOD_MPUIO: |
92105bb7 | 841 | case METHOD_GPIO_1610: |
a6472533 | 842 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 843 | if (enable) { |
92105bb7 | 844 | bank->suspend_wakeup |= (1 << gpio); |
11a78b79 DB |
845 | enable_irq_wake(bank->irq); |
846 | } else { | |
847 | disable_irq_wake(bank->irq); | |
92105bb7 | 848 | bank->suspend_wakeup &= ~(1 << gpio); |
11a78b79 | 849 | } |
a6472533 | 850 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 851 | return 0; |
3ac4fa99 | 852 | #endif |
5492fb1a | 853 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 | 854 | case METHOD_GPIO_24XX: |
11a78b79 DB |
855 | if (bank->non_wakeup_gpios & (1 << gpio)) { |
856 | printk(KERN_ERR "Unable to modify wakeup on " | |
857 | "non-wakeup GPIO%d\n", | |
858 | (bank - gpio_bank) * 32 + gpio); | |
859 | return -EINVAL; | |
860 | } | |
a6472533 | 861 | spin_lock_irqsave(&bank->lock, flags); |
3ac4fa99 | 862 | if (enable) { |
3ac4fa99 | 863 | bank->suspend_wakeup |= (1 << gpio); |
11a78b79 DB |
864 | enable_irq_wake(bank->irq); |
865 | } else { | |
866 | disable_irq_wake(bank->irq); | |
3ac4fa99 | 867 | bank->suspend_wakeup &= ~(1 << gpio); |
11a78b79 | 868 | } |
a6472533 | 869 | spin_unlock_irqrestore(&bank->lock, flags); |
3ac4fa99 JY |
870 | return 0; |
871 | #endif | |
92105bb7 TL |
872 | default: |
873 | printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n", | |
874 | bank->method); | |
875 | return -EINVAL; | |
876 | } | |
877 | } | |
878 | ||
4196dd6b TL |
879 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
880 | { | |
881 | _set_gpio_direction(bank, get_gpio_index(gpio), 1); | |
882 | _set_gpio_irqenable(bank, gpio, 0); | |
883 | _clear_gpio_irqstatus(bank, gpio); | |
884 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE); | |
885 | } | |
886 | ||
92105bb7 TL |
887 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
888 | static int gpio_wake_enable(unsigned int irq, unsigned int enable) | |
889 | { | |
890 | unsigned int gpio = irq - IH_GPIO_BASE; | |
891 | struct gpio_bank *bank; | |
892 | int retval; | |
893 | ||
894 | if (check_gpio(gpio) < 0) | |
895 | return -ENODEV; | |
58781016 | 896 | bank = get_irq_chip_data(irq); |
92105bb7 | 897 | retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); |
92105bb7 TL |
898 | |
899 | return retval; | |
900 | } | |
901 | ||
5e1c5ff4 TL |
902 | int omap_request_gpio(int gpio) |
903 | { | |
904 | struct gpio_bank *bank; | |
a6472533 | 905 | unsigned long flags; |
52e31344 | 906 | int status; |
5e1c5ff4 TL |
907 | |
908 | if (check_gpio(gpio) < 0) | |
909 | return -EINVAL; | |
910 | ||
52e31344 DB |
911 | status = gpio_request(gpio, NULL); |
912 | if (status < 0) | |
913 | return status; | |
914 | ||
5e1c5ff4 | 915 | bank = get_gpio_bank(gpio); |
a6472533 | 916 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 917 | |
4196dd6b TL |
918 | /* Set trigger to none. You need to enable the desired trigger with |
919 | * request_irq() or set_irq_type(). | |
920 | */ | |
92105bb7 TL |
921 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE); |
922 | ||
1a8bfa1e | 923 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 924 | if (bank->method == METHOD_GPIO_1510) { |
92105bb7 | 925 | void __iomem *reg; |
5e1c5ff4 | 926 | |
92105bb7 | 927 | /* Claim the pin for MPU */ |
5e1c5ff4 TL |
928 | reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; |
929 | __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg); | |
930 | } | |
931 | #endif | |
a6472533 | 932 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
933 | |
934 | return 0; | |
935 | } | |
936 | ||
937 | void omap_free_gpio(int gpio) | |
938 | { | |
939 | struct gpio_bank *bank; | |
a6472533 | 940 | unsigned long flags; |
5e1c5ff4 TL |
941 | |
942 | if (check_gpio(gpio) < 0) | |
943 | return; | |
944 | bank = get_gpio_bank(gpio); | |
a6472533 | 945 | spin_lock_irqsave(&bank->lock, flags); |
52e31344 DB |
946 | if (unlikely(!gpiochip_is_requested(&bank->chip, |
947 | get_gpio_index(gpio)))) { | |
948 | spin_unlock_irqrestore(&bank->lock, flags); | |
5e1c5ff4 TL |
949 | printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio); |
950 | dump_stack(); | |
5e1c5ff4 TL |
951 | return; |
952 | } | |
92105bb7 TL |
953 | #ifdef CONFIG_ARCH_OMAP16XX |
954 | if (bank->method == METHOD_GPIO_1610) { | |
955 | /* Disable wake-up during idle for dynamic tick */ | |
956 | void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
957 | __raw_writel(1 << get_gpio_index(gpio), reg); | |
958 | } | |
959 | #endif | |
5492fb1a | 960 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
961 | if (bank->method == METHOD_GPIO_24XX) { |
962 | /* Disable wake-up during idle for dynamic tick */ | |
963 | void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; | |
964 | __raw_writel(1 << get_gpio_index(gpio), reg); | |
965 | } | |
966 | #endif | |
4196dd6b | 967 | _reset_gpio(bank, gpio); |
a6472533 | 968 | spin_unlock_irqrestore(&bank->lock, flags); |
52e31344 | 969 | gpio_free(gpio); |
5e1c5ff4 TL |
970 | } |
971 | ||
972 | /* | |
973 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
974 | * avoid missing GPIO interrupts for other lines in the bank. | |
975 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
976 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
977 | * If we wait to unmask individual GPIO lines in the bank after the | |
978 | * line's interrupt handler has been run, we may miss some nested | |
979 | * interrupts. | |
980 | */ | |
10dd5ce2 | 981 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 982 | { |
92105bb7 | 983 | void __iomem *isr_reg = NULL; |
5e1c5ff4 TL |
984 | u32 isr; |
985 | unsigned int gpio_irq; | |
986 | struct gpio_bank *bank; | |
ea6dedd7 ID |
987 | u32 retrigger = 0; |
988 | int unmasked = 0; | |
5e1c5ff4 TL |
989 | |
990 | desc->chip->ack(irq); | |
991 | ||
418ca1f0 | 992 | bank = get_irq_data(irq); |
e5c56ed3 | 993 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
994 | if (bank->method == METHOD_MPUIO) |
995 | isr_reg = bank->base + OMAP_MPUIO_GPIO_INT; | |
e5c56ed3 | 996 | #endif |
1a8bfa1e | 997 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 TL |
998 | if (bank->method == METHOD_GPIO_1510) |
999 | isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS; | |
1000 | #endif | |
1001 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1002 | if (bank->method == METHOD_GPIO_1610) | |
1003 | isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; | |
1004 | #endif | |
1005 | #ifdef CONFIG_ARCH_OMAP730 | |
1006 | if (bank->method == METHOD_GPIO_730) | |
1007 | isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; | |
1008 | #endif | |
5492fb1a | 1009 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
1010 | if (bank->method == METHOD_GPIO_24XX) |
1011 | isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; | |
1012 | #endif | |
92105bb7 | 1013 | while(1) { |
6e60e79a | 1014 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 1015 | u32 enabled; |
6e60e79a | 1016 | |
ea6dedd7 ID |
1017 | enabled = _get_gpio_irqbank_mask(bank); |
1018 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a TL |
1019 | |
1020 | if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) | |
1021 | isr &= 0x0000ffff; | |
1022 | ||
5492fb1a | 1023 | if (cpu_class_is_omap2()) { |
6e60e79a TL |
1024 | level_mask = |
1025 | __raw_readl(bank->base + | |
1026 | OMAP24XX_GPIO_LEVELDETECT0) | | |
1027 | __raw_readl(bank->base + | |
1028 | OMAP24XX_GPIO_LEVELDETECT1); | |
ea6dedd7 ID |
1029 | level_mask &= enabled; |
1030 | } | |
6e60e79a TL |
1031 | |
1032 | /* clear edge sensitive interrupts before handler(s) are | |
1033 | called so that we don't miss any interrupt occurred while | |
1034 | executing them */ | |
1035 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0); | |
1036 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); | |
1037 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1); | |
1038 | ||
1039 | /* if there is only edge sensitive GPIO pin interrupts | |
1040 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
1041 | if (!level_mask && !unmasked) { |
1042 | unmasked = 1; | |
6e60e79a | 1043 | desc->chip->unmask(irq); |
ea6dedd7 | 1044 | } |
92105bb7 | 1045 | |
ea6dedd7 ID |
1046 | isr |= retrigger; |
1047 | retrigger = 0; | |
92105bb7 TL |
1048 | if (!isr) |
1049 | break; | |
1050 | ||
1051 | gpio_irq = bank->virtual_irq_start; | |
1052 | for (; isr != 0; isr >>= 1, gpio_irq++) { | |
10dd5ce2 | 1053 | struct irq_desc *d; |
ea6dedd7 | 1054 | int irq_mask; |
92105bb7 TL |
1055 | if (!(isr & 1)) |
1056 | continue; | |
1057 | d = irq_desc + gpio_irq; | |
ea6dedd7 ID |
1058 | /* Don't run the handler if it's already running |
1059 | * or was disabled lazely. | |
1060 | */ | |
29454dde TG |
1061 | if (unlikely((d->depth || |
1062 | (d->status & IRQ_INPROGRESS)))) { | |
ea6dedd7 ID |
1063 | irq_mask = 1 << |
1064 | (gpio_irq - bank->virtual_irq_start); | |
1065 | /* The unmasking will be done by | |
1066 | * enable_irq in case it is disabled or | |
1067 | * after returning from the handler if | |
1068 | * it's already running. | |
1069 | */ | |
1070 | _enable_gpio_irqbank(bank, irq_mask, 0); | |
29454dde | 1071 | if (!d->depth) { |
ea6dedd7 ID |
1072 | /* Level triggered interrupts |
1073 | * won't ever be reentered | |
1074 | */ | |
1075 | BUG_ON(level_mask & irq_mask); | |
29454dde | 1076 | d->status |= IRQ_PENDING; |
ea6dedd7 ID |
1077 | } |
1078 | continue; | |
1079 | } | |
29454dde | 1080 | |
0cd61b68 | 1081 | desc_handle_irq(gpio_irq, d); |
29454dde TG |
1082 | |
1083 | if (unlikely((d->status & IRQ_PENDING) && !d->depth)) { | |
ea6dedd7 ID |
1084 | irq_mask = 1 << |
1085 | (gpio_irq - bank->virtual_irq_start); | |
29454dde | 1086 | d->status &= ~IRQ_PENDING; |
ea6dedd7 ID |
1087 | _enable_gpio_irqbank(bank, irq_mask, 1); |
1088 | retrigger |= irq_mask; | |
1089 | } | |
92105bb7 | 1090 | } |
6e60e79a | 1091 | |
5492fb1a | 1092 | if (cpu_class_is_omap2()) { |
6e60e79a TL |
1093 | /* clear level sensitive interrupts after handler(s) */ |
1094 | _enable_gpio_irqbank(bank, isr_saved & level_mask, 0); | |
1095 | _clear_gpio_irqbank(bank, isr_saved & level_mask); | |
1096 | _enable_gpio_irqbank(bank, isr_saved & level_mask, 1); | |
1097 | } | |
1098 | ||
1a8bfa1e | 1099 | } |
ea6dedd7 ID |
1100 | /* if bank has any level sensitive GPIO pin interrupt |
1101 | configured, we must unmask the bank interrupt only after | |
1102 | handler(s) are executed in order to avoid spurious bank | |
1103 | interrupt */ | |
1104 | if (!unmasked) | |
1105 | desc->chip->unmask(irq); | |
1106 | ||
5e1c5ff4 TL |
1107 | } |
1108 | ||
4196dd6b TL |
1109 | static void gpio_irq_shutdown(unsigned int irq) |
1110 | { | |
1111 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1112 | struct gpio_bank *bank = get_irq_chip_data(irq); |
4196dd6b TL |
1113 | |
1114 | _reset_gpio(bank, gpio); | |
1115 | } | |
1116 | ||
5e1c5ff4 TL |
1117 | static void gpio_ack_irq(unsigned int irq) |
1118 | { | |
1119 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1120 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1121 | |
1122 | _clear_gpio_irqstatus(bank, gpio); | |
1123 | } | |
1124 | ||
1125 | static void gpio_mask_irq(unsigned int irq) | |
1126 | { | |
1127 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1128 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1129 | |
1130 | _set_gpio_irqenable(bank, gpio, 0); | |
1131 | } | |
1132 | ||
1133 | static void gpio_unmask_irq(unsigned int irq) | |
1134 | { | |
1135 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1136 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 | 1137 | |
4de8c75b | 1138 | _set_gpio_irqenable(bank, gpio, 1); |
5e1c5ff4 TL |
1139 | } |
1140 | ||
e5c56ed3 DB |
1141 | static struct irq_chip gpio_irq_chip = { |
1142 | .name = "GPIO", | |
1143 | .shutdown = gpio_irq_shutdown, | |
1144 | .ack = gpio_ack_irq, | |
1145 | .mask = gpio_mask_irq, | |
1146 | .unmask = gpio_unmask_irq, | |
1147 | .set_type = gpio_irq_type, | |
1148 | .set_wake = gpio_wake_enable, | |
1149 | }; | |
1150 | ||
1151 | /*---------------------------------------------------------------------*/ | |
1152 | ||
1153 | #ifdef CONFIG_ARCH_OMAP1 | |
1154 | ||
1155 | /* MPUIO uses the always-on 32k clock */ | |
1156 | ||
5e1c5ff4 TL |
1157 | static void mpuio_ack_irq(unsigned int irq) |
1158 | { | |
1159 | /* The ISR is reset automatically, so do nothing here. */ | |
1160 | } | |
1161 | ||
1162 | static void mpuio_mask_irq(unsigned int irq) | |
1163 | { | |
1164 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1165 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1166 | |
1167 | _set_gpio_irqenable(bank, gpio, 0); | |
1168 | } | |
1169 | ||
1170 | static void mpuio_unmask_irq(unsigned int irq) | |
1171 | { | |
1172 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1173 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1174 | |
1175 | _set_gpio_irqenable(bank, gpio, 1); | |
1176 | } | |
1177 | ||
e5c56ed3 DB |
1178 | static struct irq_chip mpuio_irq_chip = { |
1179 | .name = "MPUIO", | |
1180 | .ack = mpuio_ack_irq, | |
1181 | .mask = mpuio_mask_irq, | |
1182 | .unmask = mpuio_unmask_irq, | |
92105bb7 | 1183 | .set_type = gpio_irq_type, |
11a78b79 DB |
1184 | #ifdef CONFIG_ARCH_OMAP16XX |
1185 | /* REVISIT: assuming only 16xx supports MPUIO wake events */ | |
1186 | .set_wake = gpio_wake_enable, | |
1187 | #endif | |
5e1c5ff4 TL |
1188 | }; |
1189 | ||
e5c56ed3 DB |
1190 | |
1191 | #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) | |
1192 | ||
11a78b79 DB |
1193 | |
1194 | #ifdef CONFIG_ARCH_OMAP16XX | |
1195 | ||
1196 | #include <linux/platform_device.h> | |
1197 | ||
1198 | static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg) | |
1199 | { | |
1200 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1201 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
a6472533 | 1202 | unsigned long flags; |
11a78b79 | 1203 | |
a6472533 | 1204 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 DB |
1205 | bank->saved_wakeup = __raw_readl(mask_reg); |
1206 | __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); | |
a6472533 | 1207 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1208 | |
1209 | return 0; | |
1210 | } | |
1211 | ||
1212 | static int omap_mpuio_resume_early(struct platform_device *pdev) | |
1213 | { | |
1214 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1215 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
a6472533 | 1216 | unsigned long flags; |
11a78b79 | 1217 | |
a6472533 | 1218 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 1219 | __raw_writel(bank->saved_wakeup, mask_reg); |
a6472533 | 1220 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1221 | |
1222 | return 0; | |
1223 | } | |
1224 | ||
1225 | /* use platform_driver for this, now that there's no longer any | |
1226 | * point to sys_device (other than not disturbing old code). | |
1227 | */ | |
1228 | static struct platform_driver omap_mpuio_driver = { | |
1229 | .suspend_late = omap_mpuio_suspend_late, | |
1230 | .resume_early = omap_mpuio_resume_early, | |
1231 | .driver = { | |
1232 | .name = "mpuio", | |
1233 | }, | |
1234 | }; | |
1235 | ||
1236 | static struct platform_device omap_mpuio_device = { | |
1237 | .name = "mpuio", | |
1238 | .id = -1, | |
1239 | .dev = { | |
1240 | .driver = &omap_mpuio_driver.driver, | |
1241 | } | |
1242 | /* could list the /proc/iomem resources */ | |
1243 | }; | |
1244 | ||
1245 | static inline void mpuio_init(void) | |
1246 | { | |
fcf126d8 DB |
1247 | platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]); |
1248 | ||
11a78b79 DB |
1249 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
1250 | (void) platform_device_register(&omap_mpuio_device); | |
1251 | } | |
1252 | ||
1253 | #else | |
1254 | static inline void mpuio_init(void) {} | |
1255 | #endif /* 16xx */ | |
1256 | ||
e5c56ed3 DB |
1257 | #else |
1258 | ||
1259 | extern struct irq_chip mpuio_irq_chip; | |
1260 | ||
1261 | #define bank_is_mpuio(bank) 0 | |
11a78b79 | 1262 | static inline void mpuio_init(void) {} |
e5c56ed3 DB |
1263 | |
1264 | #endif | |
1265 | ||
1266 | /*---------------------------------------------------------------------*/ | |
5e1c5ff4 | 1267 | |
52e31344 DB |
1268 | /* REVISIT these are stupid implementations! replace by ones that |
1269 | * don't switch on METHOD_* and which mostly avoid spinlocks | |
1270 | */ | |
1271 | ||
1272 | static int gpio_input(struct gpio_chip *chip, unsigned offset) | |
1273 | { | |
1274 | struct gpio_bank *bank; | |
1275 | unsigned long flags; | |
1276 | ||
1277 | bank = container_of(chip, struct gpio_bank, chip); | |
1278 | spin_lock_irqsave(&bank->lock, flags); | |
1279 | _set_gpio_direction(bank, offset, 1); | |
1280 | spin_unlock_irqrestore(&bank->lock, flags); | |
1281 | return 0; | |
1282 | } | |
1283 | ||
1284 | static int gpio_get(struct gpio_chip *chip, unsigned offset) | |
1285 | { | |
1286 | return omap_get_gpio_datain(chip->base + offset); | |
1287 | } | |
1288 | ||
1289 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
1290 | { | |
1291 | struct gpio_bank *bank; | |
1292 | unsigned long flags; | |
1293 | ||
1294 | bank = container_of(chip, struct gpio_bank, chip); | |
1295 | spin_lock_irqsave(&bank->lock, flags); | |
1296 | _set_gpio_dataout(bank, offset, value); | |
1297 | _set_gpio_direction(bank, offset, 0); | |
1298 | spin_unlock_irqrestore(&bank->lock, flags); | |
1299 | return 0; | |
1300 | } | |
1301 | ||
1302 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
1303 | { | |
1304 | struct gpio_bank *bank; | |
1305 | unsigned long flags; | |
1306 | ||
1307 | bank = container_of(chip, struct gpio_bank, chip); | |
1308 | spin_lock_irqsave(&bank->lock, flags); | |
1309 | _set_gpio_dataout(bank, offset, value); | |
1310 | spin_unlock_irqrestore(&bank->lock, flags); | |
1311 | } | |
1312 | ||
1313 | /*---------------------------------------------------------------------*/ | |
1314 | ||
1a8bfa1e | 1315 | static int initialized; |
5492fb1a | 1316 | #if !defined(CONFIG_ARCH_OMAP3) |
1a8bfa1e | 1317 | static struct clk * gpio_ick; |
5492fb1a SMK |
1318 | #endif |
1319 | ||
1320 | #if defined(CONFIG_ARCH_OMAP2) | |
1a8bfa1e | 1321 | static struct clk * gpio_fck; |
5492fb1a | 1322 | #endif |
5e1c5ff4 | 1323 | |
5492fb1a | 1324 | #if defined(CONFIG_ARCH_OMAP2430) |
56a25641 SMK |
1325 | static struct clk * gpio5_ick; |
1326 | static struct clk * gpio5_fck; | |
1327 | #endif | |
1328 | ||
5492fb1a SMK |
1329 | #if defined(CONFIG_ARCH_OMAP3) |
1330 | static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS]; | |
1331 | static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; | |
1332 | #endif | |
1333 | ||
8ba55c5c DB |
1334 | /* This lock class tells lockdep that GPIO irqs are in a different |
1335 | * category than their parents, so it won't report false recursion. | |
1336 | */ | |
1337 | static struct lock_class_key gpio_lock_class; | |
1338 | ||
5e1c5ff4 TL |
1339 | static int __init _omap_gpio_init(void) |
1340 | { | |
1341 | int i; | |
52e31344 | 1342 | int gpio = 0; |
5e1c5ff4 | 1343 | struct gpio_bank *bank; |
5492fb1a SMK |
1344 | #if defined(CONFIG_ARCH_OMAP3) |
1345 | char clk_name[11]; | |
1346 | #endif | |
5e1c5ff4 TL |
1347 | |
1348 | initialized = 1; | |
1349 | ||
5492fb1a | 1350 | #if defined(CONFIG_ARCH_OMAP1) |
6e60e79a | 1351 | if (cpu_is_omap15xx()) { |
1a8bfa1e TL |
1352 | gpio_ick = clk_get(NULL, "arm_gpio_ck"); |
1353 | if (IS_ERR(gpio_ick)) | |
92105bb7 TL |
1354 | printk("Could not get arm_gpio_ck\n"); |
1355 | else | |
30ff720b | 1356 | clk_enable(gpio_ick); |
1a8bfa1e | 1357 | } |
5492fb1a SMK |
1358 | #endif |
1359 | #if defined(CONFIG_ARCH_OMAP2) | |
1360 | if (cpu_class_is_omap2()) { | |
1a8bfa1e TL |
1361 | gpio_ick = clk_get(NULL, "gpios_ick"); |
1362 | if (IS_ERR(gpio_ick)) | |
1363 | printk("Could not get gpios_ick\n"); | |
1364 | else | |
30ff720b | 1365 | clk_enable(gpio_ick); |
1a8bfa1e | 1366 | gpio_fck = clk_get(NULL, "gpios_fck"); |
1630b52d | 1367 | if (IS_ERR(gpio_fck)) |
1a8bfa1e TL |
1368 | printk("Could not get gpios_fck\n"); |
1369 | else | |
30ff720b | 1370 | clk_enable(gpio_fck); |
56a25641 SMK |
1371 | |
1372 | /* | |
5492fb1a | 1373 | * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK |
56a25641 | 1374 | */ |
5492fb1a | 1375 | #if defined(CONFIG_ARCH_OMAP2430) |
56a25641 SMK |
1376 | if (cpu_is_omap2430()) { |
1377 | gpio5_ick = clk_get(NULL, "gpio5_ick"); | |
1378 | if (IS_ERR(gpio5_ick)) | |
1379 | printk("Could not get gpio5_ick\n"); | |
1380 | else | |
1381 | clk_enable(gpio5_ick); | |
1382 | gpio5_fck = clk_get(NULL, "gpio5_fck"); | |
1383 | if (IS_ERR(gpio5_fck)) | |
1384 | printk("Could not get gpio5_fck\n"); | |
1385 | else | |
1386 | clk_enable(gpio5_fck); | |
1387 | } | |
1388 | #endif | |
5492fb1a SMK |
1389 | } |
1390 | #endif | |
1391 | ||
1392 | #if defined(CONFIG_ARCH_OMAP3) | |
1393 | if (cpu_is_omap34xx()) { | |
1394 | for (i = 0; i < OMAP34XX_NR_GPIOS; i++) { | |
1395 | sprintf(clk_name, "gpio%d_ick", i + 1); | |
1396 | gpio_iclks[i] = clk_get(NULL, clk_name); | |
1397 | if (IS_ERR(gpio_iclks[i])) | |
1398 | printk(KERN_ERR "Could not get %s\n", clk_name); | |
1399 | else | |
1400 | clk_enable(gpio_iclks[i]); | |
1401 | sprintf(clk_name, "gpio%d_fck", i + 1); | |
1402 | gpio_fclks[i] = clk_get(NULL, clk_name); | |
1403 | if (IS_ERR(gpio_fclks[i])) | |
1404 | printk(KERN_ERR "Could not get %s\n", clk_name); | |
1405 | else | |
1406 | clk_enable(gpio_fclks[i]); | |
1407 | } | |
1408 | } | |
1409 | #endif | |
1410 | ||
92105bb7 | 1411 | |
1a8bfa1e | 1412 | #ifdef CONFIG_ARCH_OMAP15XX |
6e60e79a | 1413 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
1414 | printk(KERN_INFO "OMAP1510 GPIO hardware\n"); |
1415 | gpio_bank_count = 2; | |
1416 | gpio_bank = gpio_bank_1510; | |
1417 | } | |
1418 | #endif | |
1419 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1420 | if (cpu_is_omap16xx()) { | |
92105bb7 | 1421 | u32 rev; |
5e1c5ff4 TL |
1422 | |
1423 | gpio_bank_count = 5; | |
1424 | gpio_bank = gpio_bank_1610; | |
1425 | rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); | |
1426 | printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", | |
1427 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1428 | } | |
1429 | #endif | |
1430 | #ifdef CONFIG_ARCH_OMAP730 | |
1431 | if (cpu_is_omap730()) { | |
1432 | printk(KERN_INFO "OMAP730 GPIO hardware\n"); | |
1433 | gpio_bank_count = 7; | |
1434 | gpio_bank = gpio_bank_730; | |
1435 | } | |
92105bb7 | 1436 | #endif |
56a25641 | 1437 | |
92105bb7 | 1438 | #ifdef CONFIG_ARCH_OMAP24XX |
56a25641 | 1439 | if (cpu_is_omap242x()) { |
92105bb7 TL |
1440 | int rev; |
1441 | ||
1442 | gpio_bank_count = 4; | |
56a25641 SMK |
1443 | gpio_bank = gpio_bank_242x; |
1444 | rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); | |
1445 | printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n", | |
1446 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1447 | } | |
1448 | if (cpu_is_omap243x()) { | |
1449 | int rev; | |
1450 | ||
1451 | gpio_bank_count = 5; | |
1452 | gpio_bank = gpio_bank_243x; | |
92105bb7 | 1453 | rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); |
56a25641 | 1454 | printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n", |
92105bb7 TL |
1455 | (rev >> 4) & 0x0f, rev & 0x0f); |
1456 | } | |
5492fb1a SMK |
1457 | #endif |
1458 | #ifdef CONFIG_ARCH_OMAP34XX | |
1459 | if (cpu_is_omap34xx()) { | |
1460 | int rev; | |
1461 | ||
1462 | gpio_bank_count = OMAP34XX_NR_GPIOS; | |
1463 | gpio_bank = gpio_bank_34xx; | |
1464 | rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); | |
1465 | printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n", | |
1466 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1467 | } | |
5e1c5ff4 TL |
1468 | #endif |
1469 | for (i = 0; i < gpio_bank_count; i++) { | |
1470 | int j, gpio_count = 16; | |
1471 | ||
1472 | bank = &gpio_bank[i]; | |
5e1c5ff4 TL |
1473 | bank->base = IO_ADDRESS(bank->base); |
1474 | spin_lock_init(&bank->lock); | |
e5c56ed3 | 1475 | if (bank_is_mpuio(bank)) |
5e1c5ff4 | 1476 | omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT); |
d11ac979 | 1477 | if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { |
5e1c5ff4 TL |
1478 | __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); |
1479 | __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); | |
1480 | } | |
d11ac979 | 1481 | if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { |
5e1c5ff4 TL |
1482 | __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1); |
1483 | __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); | |
92105bb7 | 1484 | __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); |
5e1c5ff4 | 1485 | } |
d11ac979 | 1486 | if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) { |
5e1c5ff4 TL |
1487 | __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); |
1488 | __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); | |
1489 | ||
1490 | gpio_count = 32; /* 730 has 32-bit GPIOs */ | |
1491 | } | |
d11ac979 | 1492 | |
5492fb1a | 1493 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 | 1494 | if (bank->method == METHOD_GPIO_24XX) { |
3ac4fa99 JY |
1495 | static const u32 non_wakeup_gpios[] = { |
1496 | 0xe203ffc0, 0x08700040 | |
1497 | }; | |
1498 | ||
92105bb7 TL |
1499 | __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1); |
1500 | __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1); | |
14f1c3bf JY |
1501 | __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG); |
1502 | ||
1503 | /* Initialize interface clock ungated, module enabled */ | |
1504 | __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); | |
3ac4fa99 JY |
1505 | if (i < ARRAY_SIZE(non_wakeup_gpios)) |
1506 | bank->non_wakeup_gpios = non_wakeup_gpios[i]; | |
92105bb7 TL |
1507 | gpio_count = 32; |
1508 | } | |
5e1c5ff4 | 1509 | #endif |
52e31344 DB |
1510 | |
1511 | /* REVISIT eventually switch from OMAP-specific gpio structs | |
1512 | * over to the generic ones | |
1513 | */ | |
1514 | bank->chip.direction_input = gpio_input; | |
1515 | bank->chip.get = gpio_get; | |
1516 | bank->chip.direction_output = gpio_output; | |
1517 | bank->chip.set = gpio_set; | |
1518 | if (bank_is_mpuio(bank)) { | |
1519 | bank->chip.label = "mpuio"; | |
1520 | bank->chip.base = OMAP_MPUIO(0); | |
1521 | } else { | |
1522 | bank->chip.label = "gpio"; | |
1523 | bank->chip.base = gpio; | |
1524 | gpio += gpio_count; | |
1525 | } | |
1526 | bank->chip.ngpio = gpio_count; | |
1527 | ||
1528 | gpiochip_add(&bank->chip); | |
1529 | ||
5e1c5ff4 TL |
1530 | for (j = bank->virtual_irq_start; |
1531 | j < bank->virtual_irq_start + gpio_count; j++) { | |
8ba55c5c | 1532 | lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); |
58781016 | 1533 | set_irq_chip_data(j, bank); |
e5c56ed3 | 1534 | if (bank_is_mpuio(bank)) |
5e1c5ff4 TL |
1535 | set_irq_chip(j, &mpuio_irq_chip); |
1536 | else | |
1537 | set_irq_chip(j, &gpio_irq_chip); | |
10dd5ce2 | 1538 | set_irq_handler(j, handle_simple_irq); |
5e1c5ff4 TL |
1539 | set_irq_flags(j, IRQF_VALID); |
1540 | } | |
1541 | set_irq_chained_handler(bank->irq, gpio_irq_handler); | |
1542 | set_irq_data(bank->irq, bank); | |
1543 | } | |
1544 | ||
1545 | /* Enable system clock for GPIO module. | |
1546 | * The CAM_CLK_CTRL *is* really the right place. */ | |
92105bb7 | 1547 | if (cpu_is_omap16xx()) |
5e1c5ff4 TL |
1548 | omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL); |
1549 | ||
14f1c3bf JY |
1550 | /* Enable autoidle for the OCP interface */ |
1551 | if (cpu_is_omap24xx()) | |
1552 | omap_writel(1 << 0, 0x48019010); | |
5492fb1a SMK |
1553 | if (cpu_is_omap34xx()) |
1554 | omap_writel(1 << 0, 0x48306814); | |
d11ac979 | 1555 | |
5e1c5ff4 TL |
1556 | return 0; |
1557 | } | |
1558 | ||
5492fb1a | 1559 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
1560 | static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) |
1561 | { | |
1562 | int i; | |
1563 | ||
5492fb1a | 1564 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
1565 | return 0; |
1566 | ||
1567 | for (i = 0; i < gpio_bank_count; i++) { | |
1568 | struct gpio_bank *bank = &gpio_bank[i]; | |
1569 | void __iomem *wake_status; | |
1570 | void __iomem *wake_clear; | |
1571 | void __iomem *wake_set; | |
a6472533 | 1572 | unsigned long flags; |
92105bb7 TL |
1573 | |
1574 | switch (bank->method) { | |
e5c56ed3 | 1575 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1576 | case METHOD_GPIO_1610: |
1577 | wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; | |
1578 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1579 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1580 | break; | |
e5c56ed3 | 1581 | #endif |
5492fb1a | 1582 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
1583 | case METHOD_GPIO_24XX: |
1584 | wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
1585 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; | |
1586 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
1587 | break; | |
e5c56ed3 | 1588 | #endif |
92105bb7 TL |
1589 | default: |
1590 | continue; | |
1591 | } | |
1592 | ||
a6472533 | 1593 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1594 | bank->saved_wakeup = __raw_readl(wake_status); |
1595 | __raw_writel(0xffffffff, wake_clear); | |
1596 | __raw_writel(bank->suspend_wakeup, wake_set); | |
a6472533 | 1597 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
1598 | } |
1599 | ||
1600 | return 0; | |
1601 | } | |
1602 | ||
1603 | static int omap_gpio_resume(struct sys_device *dev) | |
1604 | { | |
1605 | int i; | |
1606 | ||
1607 | if (!cpu_is_omap24xx() && !cpu_is_omap16xx()) | |
1608 | return 0; | |
1609 | ||
1610 | for (i = 0; i < gpio_bank_count; i++) { | |
1611 | struct gpio_bank *bank = &gpio_bank[i]; | |
1612 | void __iomem *wake_clear; | |
1613 | void __iomem *wake_set; | |
a6472533 | 1614 | unsigned long flags; |
92105bb7 TL |
1615 | |
1616 | switch (bank->method) { | |
e5c56ed3 | 1617 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1618 | case METHOD_GPIO_1610: |
1619 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1620 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1621 | break; | |
e5c56ed3 | 1622 | #endif |
5492fb1a | 1623 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 | 1624 | case METHOD_GPIO_24XX: |
0d9356cb TL |
1625 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1626 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
92105bb7 | 1627 | break; |
e5c56ed3 | 1628 | #endif |
92105bb7 TL |
1629 | default: |
1630 | continue; | |
1631 | } | |
1632 | ||
a6472533 | 1633 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1634 | __raw_writel(0xffffffff, wake_clear); |
1635 | __raw_writel(bank->saved_wakeup, wake_set); | |
a6472533 | 1636 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
1637 | } |
1638 | ||
1639 | return 0; | |
1640 | } | |
1641 | ||
1642 | static struct sysdev_class omap_gpio_sysclass = { | |
af5ca3f4 | 1643 | .name = "gpio", |
92105bb7 TL |
1644 | .suspend = omap_gpio_suspend, |
1645 | .resume = omap_gpio_resume, | |
1646 | }; | |
1647 | ||
1648 | static struct sys_device omap_gpio_device = { | |
1649 | .id = 0, | |
1650 | .cls = &omap_gpio_sysclass, | |
1651 | }; | |
3ac4fa99 JY |
1652 | |
1653 | #endif | |
1654 | ||
5492fb1a | 1655 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1656 | |
1657 | static int workaround_enabled; | |
1658 | ||
1659 | void omap2_gpio_prepare_for_retention(void) | |
1660 | { | |
1661 | int i, c = 0; | |
1662 | ||
1663 | /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious | |
1664 | * IRQs will be generated. See OMAP2420 Errata item 1.101. */ | |
1665 | for (i = 0; i < gpio_bank_count; i++) { | |
1666 | struct gpio_bank *bank = &gpio_bank[i]; | |
1667 | u32 l1, l2; | |
1668 | ||
1669 | if (!(bank->enabled_non_wakeup_gpios)) | |
1670 | continue; | |
5492fb1a | 1671 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1672 | bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
1673 | l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1674 | l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
5492fb1a | 1675 | #endif |
3ac4fa99 JY |
1676 | bank->saved_fallingdetect = l1; |
1677 | bank->saved_risingdetect = l2; | |
1678 | l1 &= ~bank->enabled_non_wakeup_gpios; | |
1679 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
5492fb1a | 1680 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1681 | __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT); |
1682 | __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
5492fb1a | 1683 | #endif |
3ac4fa99 JY |
1684 | c++; |
1685 | } | |
1686 | if (!c) { | |
1687 | workaround_enabled = 0; | |
1688 | return; | |
1689 | } | |
1690 | workaround_enabled = 1; | |
1691 | } | |
1692 | ||
1693 | void omap2_gpio_resume_after_retention(void) | |
1694 | { | |
1695 | int i; | |
1696 | ||
1697 | if (!workaround_enabled) | |
1698 | return; | |
1699 | for (i = 0; i < gpio_bank_count; i++) { | |
1700 | struct gpio_bank *bank = &gpio_bank[i]; | |
1701 | u32 l; | |
1702 | ||
1703 | if (!(bank->enabled_non_wakeup_gpios)) | |
1704 | continue; | |
5492fb1a | 1705 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1706 | __raw_writel(bank->saved_fallingdetect, |
1707 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1708 | __raw_writel(bank->saved_risingdetect, | |
1709 | bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
5492fb1a | 1710 | #endif |
3ac4fa99 JY |
1711 | /* Check if any of the non-wakeup interrupt GPIOs have changed |
1712 | * state. If so, generate an IRQ by software. This is | |
1713 | * horribly racy, but it's the best we can do to work around | |
1714 | * this silicon bug. */ | |
5492fb1a | 1715 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 | 1716 | l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
5492fb1a | 1717 | #endif |
3ac4fa99 JY |
1718 | l ^= bank->saved_datain; |
1719 | l &= bank->non_wakeup_gpios; | |
1720 | if (l) { | |
1721 | u32 old0, old1; | |
5492fb1a | 1722 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1723 | old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); |
1724 | old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
1725 | __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
1726 | __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
1727 | __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
1728 | __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
5492fb1a | 1729 | #endif |
3ac4fa99 JY |
1730 | } |
1731 | } | |
1732 | ||
1733 | } | |
1734 | ||
92105bb7 TL |
1735 | #endif |
1736 | ||
5e1c5ff4 TL |
1737 | /* |
1738 | * This may get called early from board specific init | |
1a8bfa1e | 1739 | * for boards that have interrupts routed via FPGA. |
5e1c5ff4 | 1740 | */ |
277d58ef | 1741 | int __init omap_gpio_init(void) |
5e1c5ff4 TL |
1742 | { |
1743 | if (!initialized) | |
1744 | return _omap_gpio_init(); | |
1745 | else | |
1746 | return 0; | |
1747 | } | |
1748 | ||
92105bb7 TL |
1749 | static int __init omap_gpio_sysinit(void) |
1750 | { | |
1751 | int ret = 0; | |
1752 | ||
1753 | if (!initialized) | |
1754 | ret = _omap_gpio_init(); | |
1755 | ||
11a78b79 DB |
1756 | mpuio_init(); |
1757 | ||
5492fb1a SMK |
1758 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
1759 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) { | |
92105bb7 TL |
1760 | if (ret == 0) { |
1761 | ret = sysdev_class_register(&omap_gpio_sysclass); | |
1762 | if (ret == 0) | |
1763 | ret = sysdev_register(&omap_gpio_device); | |
1764 | } | |
1765 | } | |
1766 | #endif | |
1767 | ||
1768 | return ret; | |
1769 | } | |
1770 | ||
5e1c5ff4 TL |
1771 | EXPORT_SYMBOL(omap_request_gpio); |
1772 | EXPORT_SYMBOL(omap_free_gpio); | |
1773 | EXPORT_SYMBOL(omap_set_gpio_direction); | |
1774 | EXPORT_SYMBOL(omap_set_gpio_dataout); | |
1775 | EXPORT_SYMBOL(omap_get_gpio_datain); | |
5e1c5ff4 | 1776 | |
92105bb7 | 1777 | arch_initcall(omap_gpio_sysinit); |
b9772a22 DB |
1778 | |
1779 | ||
1780 | #ifdef CONFIG_DEBUG_FS | |
1781 | ||
1782 | #include <linux/debugfs.h> | |
1783 | #include <linux/seq_file.h> | |
1784 | ||
1785 | static int gpio_is_input(struct gpio_bank *bank, int mask) | |
1786 | { | |
1787 | void __iomem *reg = bank->base; | |
1788 | ||
1789 | switch (bank->method) { | |
1790 | case METHOD_MPUIO: | |
1791 | reg += OMAP_MPUIO_IO_CNTL; | |
1792 | break; | |
1793 | case METHOD_GPIO_1510: | |
1794 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
1795 | break; | |
1796 | case METHOD_GPIO_1610: | |
1797 | reg += OMAP1610_GPIO_DIRECTION; | |
1798 | break; | |
1799 | case METHOD_GPIO_730: | |
1800 | reg += OMAP730_GPIO_DIR_CONTROL; | |
1801 | break; | |
1802 | case METHOD_GPIO_24XX: | |
1803 | reg += OMAP24XX_GPIO_OE; | |
1804 | break; | |
1805 | } | |
1806 | return __raw_readl(reg) & mask; | |
1807 | } | |
1808 | ||
1809 | ||
1810 | static int dbg_gpio_show(struct seq_file *s, void *unused) | |
1811 | { | |
1812 | unsigned i, j, gpio; | |
1813 | ||
1814 | for (i = 0, gpio = 0; i < gpio_bank_count; i++) { | |
1815 | struct gpio_bank *bank = gpio_bank + i; | |
1816 | unsigned bankwidth = 16; | |
1817 | u32 mask = 1; | |
1818 | ||
e5c56ed3 | 1819 | if (bank_is_mpuio(bank)) |
b9772a22 | 1820 | gpio = OMAP_MPUIO(0); |
5492fb1a | 1821 | else if (cpu_class_is_omap2() || cpu_is_omap730()) |
b9772a22 DB |
1822 | bankwidth = 32; |
1823 | ||
1824 | for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { | |
1825 | unsigned irq, value, is_in, irqstat; | |
52e31344 | 1826 | const char *label; |
b9772a22 | 1827 | |
52e31344 DB |
1828 | label = gpiochip_is_requested(&bank->chip, j); |
1829 | if (!label) | |
b9772a22 DB |
1830 | continue; |
1831 | ||
1832 | irq = bank->virtual_irq_start + j; | |
1833 | value = omap_get_gpio_datain(gpio); | |
1834 | is_in = gpio_is_input(bank, mask); | |
1835 | ||
e5c56ed3 | 1836 | if (bank_is_mpuio(bank)) |
52e31344 | 1837 | seq_printf(s, "MPUIO %2d ", j); |
b9772a22 | 1838 | else |
52e31344 DB |
1839 | seq_printf(s, "GPIO %3d ", gpio); |
1840 | seq_printf(s, "(%10s): %s %s", | |
1841 | label, | |
b9772a22 DB |
1842 | is_in ? "in " : "out", |
1843 | value ? "hi" : "lo"); | |
1844 | ||
52e31344 DB |
1845 | /* FIXME for at least omap2, show pullup/pulldown state */ |
1846 | ||
b9772a22 DB |
1847 | irqstat = irq_desc[irq].status; |
1848 | if (is_in && ((bank->suspend_wakeup & mask) | |
1849 | || irqstat & IRQ_TYPE_SENSE_MASK)) { | |
1850 | char *trigger = NULL; | |
1851 | ||
1852 | switch (irqstat & IRQ_TYPE_SENSE_MASK) { | |
1853 | case IRQ_TYPE_EDGE_FALLING: | |
1854 | trigger = "falling"; | |
1855 | break; | |
1856 | case IRQ_TYPE_EDGE_RISING: | |
1857 | trigger = "rising"; | |
1858 | break; | |
1859 | case IRQ_TYPE_EDGE_BOTH: | |
1860 | trigger = "bothedge"; | |
1861 | break; | |
1862 | case IRQ_TYPE_LEVEL_LOW: | |
1863 | trigger = "low"; | |
1864 | break; | |
1865 | case IRQ_TYPE_LEVEL_HIGH: | |
1866 | trigger = "high"; | |
1867 | break; | |
1868 | case IRQ_TYPE_NONE: | |
52e31344 | 1869 | trigger = "(?)"; |
b9772a22 DB |
1870 | break; |
1871 | } | |
52e31344 | 1872 | seq_printf(s, ", irq-%d %-8s%s", |
b9772a22 DB |
1873 | irq, trigger, |
1874 | (bank->suspend_wakeup & mask) | |
1875 | ? " wakeup" : ""); | |
1876 | } | |
1877 | seq_printf(s, "\n"); | |
1878 | } | |
1879 | ||
e5c56ed3 | 1880 | if (bank_is_mpuio(bank)) { |
b9772a22 DB |
1881 | seq_printf(s, "\n"); |
1882 | gpio = 0; | |
1883 | } | |
1884 | } | |
1885 | return 0; | |
1886 | } | |
1887 | ||
1888 | static int dbg_gpio_open(struct inode *inode, struct file *file) | |
1889 | { | |
e5c56ed3 | 1890 | return single_open(file, dbg_gpio_show, &inode->i_private); |
b9772a22 DB |
1891 | } |
1892 | ||
1893 | static const struct file_operations debug_fops = { | |
1894 | .open = dbg_gpio_open, | |
1895 | .read = seq_read, | |
1896 | .llseek = seq_lseek, | |
1897 | .release = single_release, | |
1898 | }; | |
1899 | ||
1900 | static int __init omap_gpio_debuginit(void) | |
1901 | { | |
e5c56ed3 DB |
1902 | (void) debugfs_create_file("omap_gpio", S_IRUGO, |
1903 | NULL, NULL, &debug_fops); | |
b9772a22 DB |
1904 | return 0; |
1905 | } | |
1906 | late_initcall(omap_gpio_debuginit); | |
1907 | #endif |