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ARM: OMAP: Add 3430 gpio support
[deliverable/linux.git] / arch / arm / plat-omap / gpio.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
92105bb7 6 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4
TL		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
5e1c5ff4
TL		 14#include <linux/init.h>
15#include <linux/module.h>
5e1c5ff4 16#include <linux/interrupt.h>
92105bb7
TL		 17#include <linux/sysdev.h>
18#include <linux/err.h>
f8ce2547 19#include <linux/clk.h>
5e1c5ff4
TL		 20
21#include <asm/hardware.h>
22#include <asm/irq.h>
23#include <asm/arch/irqs.h>
24#include <asm/arch/gpio.h>
25#include <asm/mach/irq.h>
26
27#include <asm/io.h>
28
29/*
30 * OMAP1510 GPIO registers
31 */
92105bb7 32#define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
5e1c5ff4
TL		 33#define OMAP1510_GPIO_DATA_INPUT 0x00
34#define OMAP1510_GPIO_DATA_OUTPUT 0x04
35#define OMAP1510_GPIO_DIR_CONTROL 0x08
36#define OMAP1510_GPIO_INT_CONTROL 0x0c
37#define OMAP1510_GPIO_INT_MASK 0x10
38#define OMAP1510_GPIO_INT_STATUS 0x14
39#define OMAP1510_GPIO_PIN_CONTROL 0x18
40
41#define OMAP1510_IH_GPIO_BASE 64
42
43/*
44 * OMAP1610 specific GPIO registers
45 */
92105bb7
TL		 46#define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
47#define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
48#define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
49#define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
5e1c5ff4
TL		 50#define OMAP1610_GPIO_REVISION 0x0000
51#define OMAP1610_GPIO_SYSCONFIG 0x0010
52#define OMAP1610_GPIO_SYSSTATUS 0x0014
53#define OMAP1610_GPIO_IRQSTATUS1 0x0018
54#define OMAP1610_GPIO_IRQENABLE1 0x001c
92105bb7 55#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
5e1c5ff4
TL		 56#define OMAP1610_GPIO_DATAIN 0x002c
57#define OMAP1610_GPIO_DATAOUT 0x0030
58#define OMAP1610_GPIO_DIRECTION 0x0034
59#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
60#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
61#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
92105bb7 62#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
5e1c5ff4
TL		 63#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
64#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
92105bb7 65#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
5e1c5ff4
TL		 66#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
67
68/*
69 * OMAP730 specific GPIO registers
70 */
92105bb7
TL		 71#define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
72#define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
73#define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
74#define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
75#define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
76#define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
5e1c5ff4
TL		 77#define OMAP730_GPIO_DATA_INPUT 0x00
78#define OMAP730_GPIO_DATA_OUTPUT 0x04
79#define OMAP730_GPIO_DIR_CONTROL 0x08
80#define OMAP730_GPIO_INT_CONTROL 0x0c
81#define OMAP730_GPIO_INT_MASK 0x10
82#define OMAP730_GPIO_INT_STATUS 0x14
83
92105bb7
TL		 84/*
85 * omap24xx specific GPIO registers
86 */
56a25641
SMK		 87#define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000
88#define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000
89#define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000
90#define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000
91
92#define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000
93#define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000
94#define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000
95#define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000
96#define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000
97
92105bb7
TL		 98#define OMAP24XX_GPIO_REVISION 0x0000
99#define OMAP24XX_GPIO_SYSCONFIG 0x0010
100#define OMAP24XX_GPIO_SYSSTATUS 0x0014
101#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
bee7930f
HD		 102#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
103#define OMAP24XX_GPIO_IRQENABLE2 0x002c
92105bb7
TL		 104#define OMAP24XX_GPIO_IRQENABLE1 0x001c
105#define OMAP24XX_GPIO_CTRL 0x0030
106#define OMAP24XX_GPIO_OE 0x0034
107#define OMAP24XX_GPIO_DATAIN 0x0038
108#define OMAP24XX_GPIO_DATAOUT 0x003c
109#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
110#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
111#define OMAP24XX_GPIO_RISINGDETECT 0x0048
112#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
113#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
114#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
115#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
116#define OMAP24XX_GPIO_SETWKUENA 0x0084
117#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
118#define OMAP24XX_GPIO_SETDATAOUT 0x0094
119
5492fb1a
SMK		 120/*
121 * omap34xx specific GPIO registers
122 */
123
124#define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000
125#define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000
126#define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000
127#define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000
128#define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000
129#define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000
130
131
5e1c5ff4 132struct gpio_bank {
92105bb7 133 void __iomem *base;
5e1c5ff4
TL		 134 u16 irq;
135 u16 virtual_irq_start;
92105bb7 136 int method;
5e1c5ff4 137 u32 reserved_map;
5492fb1a 138#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 139 u32 suspend_wakeup;
140 u32 saved_wakeup;
3ac4fa99 141#endif
5492fb1a 142#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 143 u32 non_wakeup_gpios;
144 u32 enabled_non_wakeup_gpios;
145
146 u32 saved_datain;
147 u32 saved_fallingdetect;
148 u32 saved_risingdetect;
149#endif
5e1c5ff4
TL		 150 spinlock_t lock;
151};
152
153#define METHOD_MPUIO 0
154#define METHOD_GPIO_1510 1
155#define METHOD_GPIO_1610 2
156#define METHOD_GPIO_730 3
92105bb7 157#define METHOD_GPIO_24XX 4
5e1c5ff4 158
92105bb7 159#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 160static struct gpio_bank gpio_bank_1610[5] = {
161 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
162 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
163 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
164 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
165 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
166};
167#endif
168
1a8bfa1e 169#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 170static struct gpio_bank gpio_bank_1510[2] = {
171 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
172 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
173};
174#endif
175
176#ifdef CONFIG_ARCH_OMAP730
177static struct gpio_bank gpio_bank_730[7] = {
178 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
179 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
180 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
181 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
182 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
183 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
184 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
185};
186#endif
187
92105bb7 188#ifdef CONFIG_ARCH_OMAP24XX
56a25641
SMK		 189
190static struct gpio_bank gpio_bank_242x[4] = {
191 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
192 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
193 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
194 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
92105bb7 195};
56a25641
SMK		 196
197static struct gpio_bank gpio_bank_243x[5] = {
198 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
199 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
200 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
201 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
202 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
203};
204
92105bb7
TL		 205#endif
206
5492fb1a
SMK		 207#ifdef CONFIG_ARCH_OMAP34XX
208static struct gpio_bank gpio_bank_34xx[6] = {
209 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
210 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
211 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
212 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
213 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
214 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
215};
216
217#endif
218
5e1c5ff4
TL		 219static struct gpio_bank *gpio_bank;
220static int gpio_bank_count;
221
222static inline struct gpio_bank *get_gpio_bank(int gpio)
223{
1a8bfa1e 224#ifdef CONFIG_ARCH_OMAP15XX
6e60e79a 225 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 226 if (OMAP_GPIO_IS_MPUIO(gpio))
227 return &gpio_bank[0];
228 return &gpio_bank[1];
229 }
230#endif
231#if defined(CONFIG_ARCH_OMAP16XX)
232 if (cpu_is_omap16xx()) {
233 if (OMAP_GPIO_IS_MPUIO(gpio))
234 return &gpio_bank[0];
235 return &gpio_bank[1 + (gpio >> 4)];
236 }
237#endif
238#ifdef CONFIG_ARCH_OMAP730
239 if (cpu_is_omap730()) {
240 if (OMAP_GPIO_IS_MPUIO(gpio))
241 return &gpio_bank[0];
242 return &gpio_bank[1 + (gpio >> 5)];
243 }
244#endif
92105bb7
TL		 245#ifdef CONFIG_ARCH_OMAP24XX
246 if (cpu_is_omap24xx())
247 return &gpio_bank[gpio >> 5];
248#endif
5492fb1a
SMK		 249#ifdef CONFIG_ARCH_OMAP34XX
250 if (cpu_is_omap34xx())
251 return &gpio_bank[gpio >> 5];
252#endif
5e1c5ff4
TL		 253}
254
255static inline int get_gpio_index(int gpio)
256{
92105bb7 257#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 258 if (cpu_is_omap730())
259 return gpio & 0x1f;
92105bb7
TL		 260#endif
261#ifdef CONFIG_ARCH_OMAP24XX
262 if (cpu_is_omap24xx())
263 return gpio & 0x1f;
5492fb1a
SMK		 264#endif
265#ifdef CONFIG_ARCH_OMAP34XX
266 if (cpu_is_omap34xx())
267 return gpio & 0x1f;
92105bb7
TL		 268#endif
269 return gpio & 0x0f;
5e1c5ff4
TL		 270}
271
272static inline int gpio_valid(int gpio)
273{
274 if (gpio < 0)
275 return -1;
5a4e86da 276#ifndef CONFIG_ARCH_OMAP24XX
5e1c5ff4 277 if (OMAP_GPIO_IS_MPUIO(gpio)) {
193e68be 278 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
5e1c5ff4
TL		 279 return -1;
280 return 0;
281 }
5a4e86da 282#endif
1a8bfa1e 283#ifdef CONFIG_ARCH_OMAP15XX
6e60e79a 284 if (cpu_is_omap15xx() && gpio < 16)
5e1c5ff4
TL		 285 return 0;
286#endif
287#if defined(CONFIG_ARCH_OMAP16XX)
288 if ((cpu_is_omap16xx()) && gpio < 64)
289 return 0;
290#endif
291#ifdef CONFIG_ARCH_OMAP730
292 if (cpu_is_omap730() && gpio < 192)
293 return 0;
92105bb7
TL		 294#endif
295#ifdef CONFIG_ARCH_OMAP24XX
296 if (cpu_is_omap24xx() && gpio < 128)
297 return 0;
5492fb1a
SMK		 298#endif
299#ifdef CONFIG_ARCH_OMAP34XX
300 if (cpu_is_omap34xx() && gpio < 160)
301 return 0;
5e1c5ff4
TL		 302#endif
303 return -1;
304}
305
306static int check_gpio(int gpio)
307{
308 if (unlikely(gpio_valid(gpio)) < 0) {
309 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
310 dump_stack();
311 return -1;
312 }
313 return 0;
314}
315
316static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
317{
92105bb7 318 void __iomem *reg = bank->base;
5e1c5ff4
TL		 319 u32 l;
320
321 switch (bank->method) {
e5c56ed3 322#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 323 case METHOD_MPUIO:
324 reg += OMAP_MPUIO_IO_CNTL;
325 break;
e5c56ed3
DB		 326#endif
327#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 328 case METHOD_GPIO_1510:
329 reg += OMAP1510_GPIO_DIR_CONTROL;
330 break;
e5c56ed3
DB		 331#endif
332#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 333 case METHOD_GPIO_1610:
334 reg += OMAP1610_GPIO_DIRECTION;
335 break;
e5c56ed3
DB		 336#endif
337#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 338 case METHOD_GPIO_730:
339 reg += OMAP730_GPIO_DIR_CONTROL;
340 break;
e5c56ed3 341#endif
5492fb1a 342#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 343 case METHOD_GPIO_24XX:
344 reg += OMAP24XX_GPIO_OE;
345 break;
e5c56ed3
DB		 346#endif
347 default:
348 WARN_ON(1);
349 return;
5e1c5ff4
TL		 350 }
351 l = __raw_readl(reg);
352 if (is_input)
353 l |= 1 << gpio;
354 else
355 l &= ~(1 << gpio);
356 __raw_writel(l, reg);
357}
358
359void omap_set_gpio_direction(int gpio, int is_input)
360{
361 struct gpio_bank *bank;
362
363 if (check_gpio(gpio) < 0)
364 return;
365 bank = get_gpio_bank(gpio);
366 spin_lock(&bank->lock);
367 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
368 spin_unlock(&bank->lock);
369}
370
371static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
372{
92105bb7 373 void __iomem *reg = bank->base;
5e1c5ff4
TL		 374 u32 l = 0;
375
376 switch (bank->method) {
e5c56ed3 377#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 378 case METHOD_MPUIO:
379 reg += OMAP_MPUIO_OUTPUT;
380 l = __raw_readl(reg);
381 if (enable)
382 l |= 1 << gpio;
383 else
384 l &= ~(1 << gpio);
385 break;
e5c56ed3
DB		 386#endif
387#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 388 case METHOD_GPIO_1510:
389 reg += OMAP1510_GPIO_DATA_OUTPUT;
390 l = __raw_readl(reg);
391 if (enable)
392 l |= 1 << gpio;
393 else
394 l &= ~(1 << gpio);
395 break;
e5c56ed3
DB		 396#endif
397#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 398 case METHOD_GPIO_1610:
399 if (enable)
400 reg += OMAP1610_GPIO_SET_DATAOUT;
401 else
402 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
403 l = 1 << gpio;
404 break;
e5c56ed3
DB		 405#endif
406#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 407 case METHOD_GPIO_730:
408 reg += OMAP730_GPIO_DATA_OUTPUT;
409 l = __raw_readl(reg);
410 if (enable)
411 l |= 1 << gpio;
412 else
413 l &= ~(1 << gpio);
414 break;
e5c56ed3 415#endif
5492fb1a 416#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 417 case METHOD_GPIO_24XX:
418 if (enable)
419 reg += OMAP24XX_GPIO_SETDATAOUT;
420 else
421 reg += OMAP24XX_GPIO_CLEARDATAOUT;
422 l = 1 << gpio;
423 break;
e5c56ed3 424#endif
5e1c5ff4 425 default:
e5c56ed3 426 WARN_ON(1);
5e1c5ff4
TL		 427 return;
428 }
429 __raw_writel(l, reg);
430}
431
432void omap_set_gpio_dataout(int gpio, int enable)
433{
434 struct gpio_bank *bank;
435
436 if (check_gpio(gpio) < 0)
437 return;
438 bank = get_gpio_bank(gpio);
439 spin_lock(&bank->lock);
440 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
441 spin_unlock(&bank->lock);
442}
443
444int omap_get_gpio_datain(int gpio)
445{
446 struct gpio_bank *bank;
92105bb7 447 void __iomem *reg;
5e1c5ff4
TL		 448
449 if (check_gpio(gpio) < 0)
e5c56ed3 450 return -EINVAL;
5e1c5ff4
TL		 451 bank = get_gpio_bank(gpio);
452 reg = bank->base;
453 switch (bank->method) {
e5c56ed3 454#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 455 case METHOD_MPUIO:
456 reg += OMAP_MPUIO_INPUT_LATCH;
457 break;
e5c56ed3
DB		 458#endif
459#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 460 case METHOD_GPIO_1510:
461 reg += OMAP1510_GPIO_DATA_INPUT;
462 break;
e5c56ed3
DB		 463#endif
464#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 465 case METHOD_GPIO_1610:
466 reg += OMAP1610_GPIO_DATAIN;
467 break;
e5c56ed3
DB		 468#endif
469#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 470 case METHOD_GPIO_730:
471 reg += OMAP730_GPIO_DATA_INPUT;
472 break;
e5c56ed3 473#endif
5492fb1a 474#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 475 case METHOD_GPIO_24XX:
476 reg += OMAP24XX_GPIO_DATAIN;
477 break;
e5c56ed3 478#endif
5e1c5ff4 479 default:
e5c56ed3 480 return -EINVAL;
5e1c5ff4 481 }
92105bb7
TL		 482 return (__raw_readl(reg)
483 & (1 << get_gpio_index(gpio))) != 0;
5e1c5ff4
TL		 484}
485
92105bb7
TL		 486#define MOD_REG_BIT(reg, bit_mask, set) \
487do { \
488 int l = __raw_readl(base + reg); \
489 if (set) l |= bit_mask; \
490 else l &= ~bit_mask; \
491 __raw_writel(l, base + reg); \
492} while(0)
493
5492fb1a 494#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99 495static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
5e1c5ff4 496{
3ac4fa99 497 void __iomem *base = bank->base;
92105bb7
TL		 498 u32 gpio_bit = 1 << gpio;
499
500 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
6e60e79a 501 trigger & __IRQT_LOWLVL);
92105bb7 502 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
6e60e79a 503 trigger & __IRQT_HIGHLVL);
92105bb7 504 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
6e60e79a 505 trigger & __IRQT_RISEDGE);
92105bb7 506 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
6e60e79a 507 trigger & __IRQT_FALEDGE);
3ac4fa99
JY		 508 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
509 if (trigger != 0)
510 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA);
511 else
512 __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA);
513 } else {
514 if (trigger != 0)
515 bank->enabled_non_wakeup_gpios |= gpio_bit;
516 else
517 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
518 }
10dd5ce2 519 /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level
92105bb7
TL		 520 * triggering requested. */
521}
3ac4fa99 522#endif
92105bb7
TL		 523
524static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
525{
526 void __iomem *reg = bank->base;
527 u32 l = 0;
5e1c5ff4
TL		 528
529 switch (bank->method) {
e5c56ed3 530#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 531 case METHOD_MPUIO:
532 reg += OMAP_MPUIO_GPIO_INT_EDGE;
533 l = __raw_readl(reg);
6e60e79a 534 if (trigger & __IRQT_RISEDGE)
5e1c5ff4 535 l |= 1 << gpio;
6e60e79a 536 else if (trigger & __IRQT_FALEDGE)
5e1c5ff4 537 l &= ~(1 << gpio);
92105bb7
TL		 538 else
539 goto bad;
5e1c5ff4 540 break;
e5c56ed3
DB		 541#endif
542#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 543 case METHOD_GPIO_1510:
544 reg += OMAP1510_GPIO_INT_CONTROL;
545 l = __raw_readl(reg);
6e60e79a 546 if (trigger & __IRQT_RISEDGE)
5e1c5ff4 547 l |= 1 << gpio;
6e60e79a 548 else if (trigger & __IRQT_FALEDGE)
5e1c5ff4 549 l &= ~(1 << gpio);
92105bb7
TL		 550 else
551 goto bad;
5e1c5ff4 552 break;
e5c56ed3 553#endif
3ac4fa99 554#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 555 case METHOD_GPIO_1610:
5e1c5ff4
TL		 556 if (gpio & 0x08)
557 reg += OMAP1610_GPIO_EDGE_CTRL2;
558 else
559 reg += OMAP1610_GPIO_EDGE_CTRL1;
560 gpio &= 0x07;
561 l = __raw_readl(reg);
562 l &= ~(3 << (gpio << 1));
6e60e79a
TL		 563 if (trigger & __IRQT_RISEDGE)
564 l |= 2 << (gpio << 1);
565 if (trigger & __IRQT_FALEDGE)
566 l |= 1 << (gpio << 1);
3ac4fa99
JY		 567 if (trigger)
568 /* Enable wake-up during idle for dynamic tick */
569 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
570 else
571 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 572 break;
3ac4fa99
JY		 573#endif
574#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 575 case METHOD_GPIO_730:
576 reg += OMAP730_GPIO_INT_CONTROL;
577 l = __raw_readl(reg);
6e60e79a 578 if (trigger & __IRQT_RISEDGE)
5e1c5ff4 579 l |= 1 << gpio;
6e60e79a 580 else if (trigger & __IRQT_FALEDGE)
5e1c5ff4 581 l &= ~(1 << gpio);
92105bb7
TL		 582 else
583 goto bad;
584 break;
3ac4fa99 585#endif
5492fb1a 586#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 587 case METHOD_GPIO_24XX:
3ac4fa99 588 set_24xx_gpio_triggering(bank, gpio, trigger);
5e1c5ff4 589 break;
3ac4fa99 590#endif
5e1c5ff4 591 default:
92105bb7 592 goto bad;
5e1c5ff4 593 }
92105bb7
TL		 594 __raw_writel(l, reg);
595 return 0;
596bad:
597 return -EINVAL;
5e1c5ff4
TL		 598}
599
92105bb7 600static int gpio_irq_type(unsigned irq, unsigned type)
5e1c5ff4
TL		 601{
602 struct gpio_bank *bank;
92105bb7
TL		 603 unsigned gpio;
604 int retval;
605
5492fb1a 606 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
92105bb7
TL		 607 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
608 else
609 gpio = irq - IH_GPIO_BASE;
5e1c5ff4
TL		 610
611 if (check_gpio(gpio) < 0)
92105bb7
TL		 612 return -EINVAL;
613
e5c56ed3 614 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 615 return -EINVAL;
e5c56ed3
DB		 616
617 /* OMAP1 allows only only edge triggering */
5492fb1a 618 if (!cpu_class_is_omap2()
e5c56ed3 619 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 620 return -EINVAL;
621
58781016 622 bank = get_irq_chip_data(irq);
5e1c5ff4 623 spin_lock(&bank->lock);
92105bb7 624 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
b9772a22
DB		 625 if (retval == 0) {
626 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
627 irq_desc[irq].status |= type;
628 }
5e1c5ff4 629 spin_unlock(&bank->lock);
92105bb7 630 return retval;
5e1c5ff4
TL		 631}
632
633static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
634{
92105bb7 635 void __iomem *reg = bank->base;
5e1c5ff4
TL		 636
637 switch (bank->method) {
e5c56ed3 638#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 639 case METHOD_MPUIO:
640 /* MPUIO irqstatus is reset by reading the status register,
641 * so do nothing here */
642 return;
e5c56ed3
DB		 643#endif
644#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 645 case METHOD_GPIO_1510:
646 reg += OMAP1510_GPIO_INT_STATUS;
647 break;
e5c56ed3
DB		 648#endif
649#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 650 case METHOD_GPIO_1610:
651 reg += OMAP1610_GPIO_IRQSTATUS1;
652 break;
e5c56ed3
DB		 653#endif
654#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 655 case METHOD_GPIO_730:
656 reg += OMAP730_GPIO_INT_STATUS;
657 break;
e5c56ed3 658#endif
5492fb1a 659#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 660 case METHOD_GPIO_24XX:
661 reg += OMAP24XX_GPIO_IRQSTATUS1;
662 break;
e5c56ed3 663#endif
5e1c5ff4 664 default:
e5c56ed3 665 WARN_ON(1);
5e1c5ff4
TL		 666 return;
667 }
668 __raw_writel(gpio_mask, reg);
bee7930f
HD		 669
670 /* Workaround for clearing DSP GPIO interrupts to allow retention */
5492fb1a
SMK		 671#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
672 if (cpu_is_omap24xx() || cpu_is_omap34xx())
bee7930f 673 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
5492fb1a 674#endif
5e1c5ff4
TL		 675}
676
677static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
678{
679 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
680}
681
ea6dedd7
ID		 682static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
683{
684 void __iomem *reg = bank->base;
99c47707
ID		 685 int inv = 0;
686 u32 l;
687 u32 mask;
ea6dedd7
ID		 688
689 switch (bank->method) {
e5c56ed3 690#ifdef CONFIG_ARCH_OMAP1
ea6dedd7
ID		 691 case METHOD_MPUIO:
692 reg += OMAP_MPUIO_GPIO_MASKIT;
99c47707
ID		 693 mask = 0xffff;
694 inv = 1;
ea6dedd7 695 break;
e5c56ed3
DB		 696#endif
697#ifdef CONFIG_ARCH_OMAP15XX
ea6dedd7
ID		 698 case METHOD_GPIO_1510:
699 reg += OMAP1510_GPIO_INT_MASK;
99c47707
ID		 700 mask = 0xffff;
701 inv = 1;
ea6dedd7 702 break;
e5c56ed3
DB		 703#endif
704#ifdef CONFIG_ARCH_OMAP16XX
ea6dedd7
ID		 705 case METHOD_GPIO_1610:
706 reg += OMAP1610_GPIO_IRQENABLE1;
99c47707 707 mask = 0xffff;
ea6dedd7 708 break;
e5c56ed3
DB		 709#endif
710#ifdef CONFIG_ARCH_OMAP730
ea6dedd7
ID		 711 case METHOD_GPIO_730:
712 reg += OMAP730_GPIO_INT_MASK;
99c47707
ID		 713 mask = 0xffffffff;
714 inv = 1;
ea6dedd7 715 break;
e5c56ed3 716#endif
5492fb1a 717#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
ea6dedd7
ID		 718 case METHOD_GPIO_24XX:
719 reg += OMAP24XX_GPIO_IRQENABLE1;
99c47707 720 mask = 0xffffffff;
ea6dedd7 721 break;
e5c56ed3 722#endif
ea6dedd7 723 default:
e5c56ed3 724 WARN_ON(1);
ea6dedd7
ID		 725 return 0;
726 }
727
99c47707
ID		 728 l = __raw_readl(reg);
729 if (inv)
730 l = ~l;
731 l &= mask;
732 return l;
ea6dedd7
ID		 733}
734
5e1c5ff4
TL		 735static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
736{
92105bb7 737 void __iomem *reg = bank->base;
5e1c5ff4
TL		 738 u32 l;
739
740 switch (bank->method) {
e5c56ed3 741#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 742 case METHOD_MPUIO:
743 reg += OMAP_MPUIO_GPIO_MASKIT;
744 l = __raw_readl(reg);
745 if (enable)
746 l &= ~(gpio_mask);
747 else
748 l |= gpio_mask;
749 break;
e5c56ed3
DB		 750#endif
751#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 752 case METHOD_GPIO_1510:
753 reg += OMAP1510_GPIO_INT_MASK;
754 l = __raw_readl(reg);
755 if (enable)
756 l &= ~(gpio_mask);
757 else
758 l |= gpio_mask;
759 break;
e5c56ed3
DB		 760#endif
761#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 762 case METHOD_GPIO_1610:
763 if (enable)
764 reg += OMAP1610_GPIO_SET_IRQENABLE1;
765 else
766 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
767 l = gpio_mask;
768 break;
e5c56ed3
DB		 769#endif
770#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 771 case METHOD_GPIO_730:
772 reg += OMAP730_GPIO_INT_MASK;
773 l = __raw_readl(reg);
774 if (enable)
775 l &= ~(gpio_mask);
776 else
777 l |= gpio_mask;
778 break;
e5c56ed3 779#endif
5492fb1a 780#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 781 case METHOD_GPIO_24XX:
782 if (enable)
783 reg += OMAP24XX_GPIO_SETIRQENABLE1;
784 else
785 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
786 l = gpio_mask;
787 break;
e5c56ed3 788#endif
5e1c5ff4 789 default:
e5c56ed3 790 WARN_ON(1);
5e1c5ff4
TL		 791 return;
792 }
793 __raw_writel(l, reg);
794}
795
796static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
797{
798 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
799}
800
92105bb7
TL		 801/*
802 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
803 * 1510 does not seem to have a wake-up register. If JTAG is connected
804 * to the target, system will wake up always on GPIO events. While
805 * system is running all registered GPIO interrupts need to have wake-up
806 * enabled. When system is suspended, only selected GPIO interrupts need
807 * to have wake-up enabled.
808 */
809static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
810{
811 switch (bank->method) {
3ac4fa99 812#ifdef CONFIG_ARCH_OMAP16XX
11a78b79 813 case METHOD_MPUIO:
92105bb7 814 case METHOD_GPIO_1610:
92105bb7 815 spin_lock(&bank->lock);
11a78b79 816 if (enable) {
92105bb7 817 bank->suspend_wakeup |= (1 << gpio);
11a78b79
DB		 818 enable_irq_wake(bank->irq);
819 } else {
820 disable_irq_wake(bank->irq);
92105bb7 821 bank->suspend_wakeup &= ~(1 << gpio);
11a78b79 822 }
92105bb7
TL		 823 spin_unlock(&bank->lock);
824 return 0;
3ac4fa99 825#endif
5492fb1a 826#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99 827 case METHOD_GPIO_24XX:
11a78b79
DB		 828 if (bank->non_wakeup_gpios & (1 << gpio)) {
829 printk(KERN_ERR "Unable to modify wakeup on "
830 "non-wakeup GPIO%d\n",
831 (bank - gpio_bank) * 32 + gpio);
832 return -EINVAL;
833 }
3ac4fa99
JY		 834 spin_lock(&bank->lock);
835 if (enable) {
3ac4fa99 836 bank->suspend_wakeup |= (1 << gpio);
11a78b79
DB		 837 enable_irq_wake(bank->irq);
838 } else {
839 disable_irq_wake(bank->irq);
3ac4fa99 840 bank->suspend_wakeup &= ~(1 << gpio);
11a78b79 841 }
3ac4fa99
JY		 842 spin_unlock(&bank->lock);
843 return 0;
844#endif
92105bb7
TL		 845 default:
846 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
847 bank->method);
848 return -EINVAL;
849 }
850}
851
4196dd6b
TL		 852static void _reset_gpio(struct gpio_bank *bank, int gpio)
853{
854 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
855 _set_gpio_irqenable(bank, gpio, 0);
856 _clear_gpio_irqstatus(bank, gpio);
857 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
858}
859
92105bb7
TL		 860/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
861static int gpio_wake_enable(unsigned int irq, unsigned int enable)
862{
863 unsigned int gpio = irq - IH_GPIO_BASE;
864 struct gpio_bank *bank;
865 int retval;
866
867 if (check_gpio(gpio) < 0)
868 return -ENODEV;
58781016 869 bank = get_irq_chip_data(irq);
92105bb7 870 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
92105bb7
TL		 871
872 return retval;
873}
874
5e1c5ff4
TL		 875int omap_request_gpio(int gpio)
876{
877 struct gpio_bank *bank;
878
879 if (check_gpio(gpio) < 0)
880 return -EINVAL;
881
882 bank = get_gpio_bank(gpio);
883 spin_lock(&bank->lock);
884 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
885 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
886 dump_stack();
887 spin_unlock(&bank->lock);
888 return -1;
889 }
890 bank->reserved_map |= (1 << get_gpio_index(gpio));
92105bb7 891
4196dd6b
TL		 892 /* Set trigger to none. You need to enable the desired trigger with
893 * request_irq() or set_irq_type().
894 */
92105bb7
TL		 895 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
896
1a8bfa1e 897#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 898 if (bank->method == METHOD_GPIO_1510) {
92105bb7 899 void __iomem *reg;
5e1c5ff4 900
92105bb7 901 /* Claim the pin for MPU */
5e1c5ff4
TL		 902 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
903 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
904 }
905#endif
906 spin_unlock(&bank->lock);
907
908 return 0;
909}
910
911void omap_free_gpio(int gpio)
912{
913 struct gpio_bank *bank;
914
915 if (check_gpio(gpio) < 0)
916 return;
917 bank = get_gpio_bank(gpio);
918 spin_lock(&bank->lock);
919 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
920 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
921 dump_stack();
922 spin_unlock(&bank->lock);
923 return;
924 }
92105bb7
TL		 925#ifdef CONFIG_ARCH_OMAP16XX
926 if (bank->method == METHOD_GPIO_1610) {
927 /* Disable wake-up during idle for dynamic tick */
928 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
929 __raw_writel(1 << get_gpio_index(gpio), reg);
930 }
931#endif
5492fb1a 932#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 933 if (bank->method == METHOD_GPIO_24XX) {
934 /* Disable wake-up during idle for dynamic tick */
935 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
936 __raw_writel(1 << get_gpio_index(gpio), reg);
937 }
938#endif
5e1c5ff4 939 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
4196dd6b 940 _reset_gpio(bank, gpio);
5e1c5ff4
TL		 941 spin_unlock(&bank->lock);
942}
943
944/*
945 * We need to unmask the GPIO bank interrupt as soon as possible to
946 * avoid missing GPIO interrupts for other lines in the bank.
947 * Then we need to mask-read-clear-unmask the triggered GPIO lines
948 * in the bank to avoid missing nested interrupts for a GPIO line.
949 * If we wait to unmask individual GPIO lines in the bank after the
950 * line's interrupt handler has been run, we may miss some nested
951 * interrupts.
952 */
10dd5ce2 953static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 954{
92105bb7 955 void __iomem *isr_reg = NULL;
5e1c5ff4
TL		 956 u32 isr;
957 unsigned int gpio_irq;
958 struct gpio_bank *bank;
ea6dedd7
ID		 959 u32 retrigger = 0;
960 int unmasked = 0;
5e1c5ff4
TL		 961
962 desc->chip->ack(irq);
963
418ca1f0 964 bank = get_irq_data(irq);
e5c56ed3 965#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 966 if (bank->method == METHOD_MPUIO)
967 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
e5c56ed3 968#endif
1a8bfa1e 969#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 970 if (bank->method == METHOD_GPIO_1510)
971 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
972#endif
973#if defined(CONFIG_ARCH_OMAP16XX)
974 if (bank->method == METHOD_GPIO_1610)
975 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
976#endif
977#ifdef CONFIG_ARCH_OMAP730
978 if (bank->method == METHOD_GPIO_730)
979 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
980#endif
5492fb1a 981#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 982 if (bank->method == METHOD_GPIO_24XX)
983 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
984#endif
92105bb7 985 while(1) {
6e60e79a 986 u32 isr_saved, level_mask = 0;
ea6dedd7 987 u32 enabled;
6e60e79a 988
ea6dedd7
ID		 989 enabled = _get_gpio_irqbank_mask(bank);
990 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 991
992 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
993 isr &= 0x0000ffff;
994
5492fb1a 995 if (cpu_class_is_omap2()) {
6e60e79a
TL		 996 level_mask =
997 __raw_readl(bank->base +
998 OMAP24XX_GPIO_LEVELDETECT0) |
999 __raw_readl(bank->base +
1000 OMAP24XX_GPIO_LEVELDETECT1);
ea6dedd7
ID		 1001 level_mask &= enabled;
1002 }
6e60e79a
TL		 1003
1004 /* clear edge sensitive interrupts before handler(s) are
1005 called so that we don't miss any interrupt occurred while
1006 executing them */
1007 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1008 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1009 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1010
1011 /* if there is only edge sensitive GPIO pin interrupts
1012 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 1013 if (!level_mask && !unmasked) {
1014 unmasked = 1;
6e60e79a 1015 desc->chip->unmask(irq);
ea6dedd7 1016 }
92105bb7 1017
ea6dedd7
ID		 1018 isr |= retrigger;
1019 retrigger = 0;
92105bb7
TL		 1020 if (!isr)
1021 break;
1022
1023 gpio_irq = bank->virtual_irq_start;
1024 for (; isr != 0; isr >>= 1, gpio_irq++) {
10dd5ce2 1025 struct irq_desc *d;
ea6dedd7 1026 int irq_mask;
92105bb7
TL		 1027 if (!(isr & 1))
1028 continue;
1029 d = irq_desc + gpio_irq;
ea6dedd7
ID		 1030 /* Don't run the handler if it's already running
1031 * or was disabled lazely.
1032 */
29454dde
TG		 1033 if (unlikely((d->depth ||
1034 (d->status & IRQ_INPROGRESS)))) {
ea6dedd7
ID		 1035 irq_mask = 1 <<
1036 (gpio_irq - bank->virtual_irq_start);
1037 /* The unmasking will be done by
1038 * enable_irq in case it is disabled or
1039 * after returning from the handler if
1040 * it's already running.
1041 */
1042 _enable_gpio_irqbank(bank, irq_mask, 0);
29454dde 1043 if (!d->depth) {
ea6dedd7
ID		 1044 /* Level triggered interrupts
1045 * won't ever be reentered
1046 */
1047 BUG_ON(level_mask & irq_mask);
29454dde 1048 d->status |= IRQ_PENDING;
ea6dedd7
ID		 1049 }
1050 continue;
1051 }
29454dde 1052
0cd61b68 1053 desc_handle_irq(gpio_irq, d);
29454dde
TG		 1054
1055 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
ea6dedd7
ID		 1056 irq_mask = 1 <<
1057 (gpio_irq - bank->virtual_irq_start);
29454dde 1058 d->status &= ~IRQ_PENDING;
ea6dedd7
ID		 1059 _enable_gpio_irqbank(bank, irq_mask, 1);
1060 retrigger |= irq_mask;
1061 }
92105bb7 1062 }
6e60e79a 1063
5492fb1a 1064 if (cpu_class_is_omap2()) {
6e60e79a
TL		 1065 /* clear level sensitive interrupts after handler(s) */
1066 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
1067 _clear_gpio_irqbank(bank, isr_saved & level_mask);
1068 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
1069 }
1070
1a8bfa1e 1071 }
ea6dedd7
ID		 1072 /* if bank has any level sensitive GPIO pin interrupt
1073 configured, we must unmask the bank interrupt only after
1074 handler(s) are executed in order to avoid spurious bank
1075 interrupt */
1076 if (!unmasked)
1077 desc->chip->unmask(irq);
1078
5e1c5ff4
TL		 1079}
1080
4196dd6b
TL		 1081static void gpio_irq_shutdown(unsigned int irq)
1082{
1083 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1084 struct gpio_bank *bank = get_irq_chip_data(irq);
4196dd6b
TL		 1085
1086 _reset_gpio(bank, gpio);
1087}
1088
5e1c5ff4
TL		 1089static void gpio_ack_irq(unsigned int irq)
1090{
1091 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1092 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1093
1094 _clear_gpio_irqstatus(bank, gpio);
1095}
1096
1097static void gpio_mask_irq(unsigned int irq)
1098{
1099 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1100 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1101
1102 _set_gpio_irqenable(bank, gpio, 0);
1103}
1104
1105static void gpio_unmask_irq(unsigned int irq)
1106{
1107 unsigned int gpio = irq - IH_GPIO_BASE;
92105bb7 1108 unsigned int gpio_idx = get_gpio_index(gpio);
58781016 1109 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4 1110
92105bb7 1111 _set_gpio_irqenable(bank, gpio_idx, 1);
5e1c5ff4
TL		 1112}
1113
e5c56ed3
DB		 1114static struct irq_chip gpio_irq_chip = {
1115 .name = "GPIO",
1116 .shutdown = gpio_irq_shutdown,
1117 .ack = gpio_ack_irq,
1118 .mask = gpio_mask_irq,
1119 .unmask = gpio_unmask_irq,
1120 .set_type = gpio_irq_type,
1121 .set_wake = gpio_wake_enable,
1122};
1123
1124/*---------------------------------------------------------------------*/
1125
1126#ifdef CONFIG_ARCH_OMAP1
1127
1128/* MPUIO uses the always-on 32k clock */
1129
5e1c5ff4
TL		 1130static void mpuio_ack_irq(unsigned int irq)
1131{
1132 /* The ISR is reset automatically, so do nothing here. */
1133}
1134
1135static void mpuio_mask_irq(unsigned int irq)
1136{
1137 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1138 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1139
1140 _set_gpio_irqenable(bank, gpio, 0);
1141}
1142
1143static void mpuio_unmask_irq(unsigned int irq)
1144{
1145 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1146 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1147
1148 _set_gpio_irqenable(bank, gpio, 1);
1149}
1150
e5c56ed3
DB		 1151static struct irq_chip mpuio_irq_chip = {
1152 .name = "MPUIO",
1153 .ack = mpuio_ack_irq,
1154 .mask = mpuio_mask_irq,
1155 .unmask = mpuio_unmask_irq,
92105bb7 1156 .set_type = gpio_irq_type,
11a78b79
DB		 1157#ifdef CONFIG_ARCH_OMAP16XX
1158 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1159 .set_wake = gpio_wake_enable,
1160#endif
5e1c5ff4
TL		 1161};
1162
e5c56ed3
DB		 1163
1164#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1165
11a78b79
DB		 1166
1167#ifdef CONFIG_ARCH_OMAP16XX
1168
1169#include <linux/platform_device.h>
1170
1171static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1172{
1173 struct gpio_bank *bank = platform_get_drvdata(pdev);
1174 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1175
1176 spin_lock(&bank->lock);
1177 bank->saved_wakeup = __raw_readl(mask_reg);
1178 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1179 spin_unlock(&bank->lock);
1180
1181 return 0;
1182}
1183
1184static int omap_mpuio_resume_early(struct platform_device *pdev)
1185{
1186 struct gpio_bank *bank = platform_get_drvdata(pdev);
1187 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1188
1189 spin_lock(&bank->lock);
1190 __raw_writel(bank->saved_wakeup, mask_reg);
1191 spin_unlock(&bank->lock);
1192
1193 return 0;
1194}
1195
1196/* use platform_driver for this, now that there's no longer any
1197 * point to sys_device (other than not disturbing old code).
1198 */
1199static struct platform_driver omap_mpuio_driver = {
1200 .suspend_late = omap_mpuio_suspend_late,
1201 .resume_early = omap_mpuio_resume_early,
1202 .driver = {
1203 .name = "mpuio",
1204 },
1205};
1206
1207static struct platform_device omap_mpuio_device = {
1208 .name = "mpuio",
1209 .id = -1,
1210 .dev = {
1211 .driver = &omap_mpuio_driver.driver,
1212 }
1213 /* could list the /proc/iomem resources */
1214};
1215
1216static inline void mpuio_init(void)
1217{
fcf126d8
DB		 1218 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1219
11a78b79
DB		 1220 if (platform_driver_register(&omap_mpuio_driver) == 0)
1221 (void) platform_device_register(&omap_mpuio_device);
1222}
1223
1224#else
1225static inline void mpuio_init(void) {}
1226#endif /* 16xx */
1227
e5c56ed3
DB		 1228#else
1229
1230extern struct irq_chip mpuio_irq_chip;
1231
1232#define bank_is_mpuio(bank) 0
11a78b79 1233static inline void mpuio_init(void) {}
e5c56ed3
DB		 1234
1235#endif
1236
1237/*---------------------------------------------------------------------*/
5e1c5ff4 1238
1a8bfa1e 1239static int initialized;
5492fb1a 1240#if !defined(CONFIG_ARCH_OMAP3)
1a8bfa1e 1241static struct clk * gpio_ick;
5492fb1a
SMK		 1242#endif
1243
1244#if defined(CONFIG_ARCH_OMAP2)
1a8bfa1e 1245static struct clk * gpio_fck;
5492fb1a 1246#endif
5e1c5ff4 1247
5492fb1a 1248#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1249static struct clk * gpio5_ick;
1250static struct clk * gpio5_fck;
1251#endif
1252
5492fb1a
SMK		 1253#if defined(CONFIG_ARCH_OMAP3)
1254static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
1255static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1256#endif
1257
5e1c5ff4
TL		 1258static int __init _omap_gpio_init(void)
1259{
1260 int i;
1261 struct gpio_bank *bank;
5492fb1a
SMK		 1262#if defined(CONFIG_ARCH_OMAP3)
1263 char clk_name[11];
1264#endif
5e1c5ff4
TL		 1265
1266 initialized = 1;
1267
5492fb1a 1268#if defined(CONFIG_ARCH_OMAP1)
6e60e79a 1269 if (cpu_is_omap15xx()) {
1a8bfa1e
TL		 1270 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1271 if (IS_ERR(gpio_ick))
92105bb7
TL		 1272 printk("Could not get arm_gpio_ck\n");
1273 else
30ff720b 1274 clk_enable(gpio_ick);
1a8bfa1e 1275 }
5492fb1a
SMK		 1276#endif
1277#if defined(CONFIG_ARCH_OMAP2)
1278 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 1279 gpio_ick = clk_get(NULL, "gpios_ick");
1280 if (IS_ERR(gpio_ick))
1281 printk("Could not get gpios_ick\n");
1282 else
30ff720b 1283 clk_enable(gpio_ick);
1a8bfa1e 1284 gpio_fck = clk_get(NULL, "gpios_fck");
1630b52d 1285 if (IS_ERR(gpio_fck))
1a8bfa1e
TL		 1286 printk("Could not get gpios_fck\n");
1287 else
30ff720b 1288 clk_enable(gpio_fck);
56a25641
SMK		 1289
1290 /*
5492fb1a 1291 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
56a25641 1292 */
5492fb1a 1293#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1294 if (cpu_is_omap2430()) {
1295 gpio5_ick = clk_get(NULL, "gpio5_ick");
1296 if (IS_ERR(gpio5_ick))
1297 printk("Could not get gpio5_ick\n");
1298 else
1299 clk_enable(gpio5_ick);
1300 gpio5_fck = clk_get(NULL, "gpio5_fck");
1301 if (IS_ERR(gpio5_fck))
1302 printk("Could not get gpio5_fck\n");
1303 else
1304 clk_enable(gpio5_fck);
1305 }
1306#endif
5492fb1a
SMK		 1307 }
1308#endif
1309
1310#if defined(CONFIG_ARCH_OMAP3)
1311 if (cpu_is_omap34xx()) {
1312 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1313 sprintf(clk_name, "gpio%d_ick", i + 1);
1314 gpio_iclks[i] = clk_get(NULL, clk_name);
1315 if (IS_ERR(gpio_iclks[i]))
1316 printk(KERN_ERR "Could not get %s\n", clk_name);
1317 else
1318 clk_enable(gpio_iclks[i]);
1319 sprintf(clk_name, "gpio%d_fck", i + 1);
1320 gpio_fclks[i] = clk_get(NULL, clk_name);
1321 if (IS_ERR(gpio_fclks[i]))
1322 printk(KERN_ERR "Could not get %s\n", clk_name);
1323 else
1324 clk_enable(gpio_fclks[i]);
1325 }
1326 }
1327#endif
1328
92105bb7 1329
1a8bfa1e 1330#ifdef CONFIG_ARCH_OMAP15XX
6e60e79a 1331 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 1332 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1333 gpio_bank_count = 2;
1334 gpio_bank = gpio_bank_1510;
1335 }
1336#endif
1337#if defined(CONFIG_ARCH_OMAP16XX)
1338 if (cpu_is_omap16xx()) {
92105bb7 1339 u32 rev;
5e1c5ff4
TL		 1340
1341 gpio_bank_count = 5;
1342 gpio_bank = gpio_bank_1610;
1343 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1344 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1345 (rev >> 4) & 0x0f, rev & 0x0f);
1346 }
1347#endif
1348#ifdef CONFIG_ARCH_OMAP730
1349 if (cpu_is_omap730()) {
1350 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1351 gpio_bank_count = 7;
1352 gpio_bank = gpio_bank_730;
1353 }
92105bb7 1354#endif
56a25641 1355
92105bb7 1356#ifdef CONFIG_ARCH_OMAP24XX
56a25641 1357 if (cpu_is_omap242x()) {
92105bb7
TL		 1358 int rev;
1359
1360 gpio_bank_count = 4;
56a25641
SMK		 1361 gpio_bank = gpio_bank_242x;
1362 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1363 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1364 (rev >> 4) & 0x0f, rev & 0x0f);
1365 }
1366 if (cpu_is_omap243x()) {
1367 int rev;
1368
1369 gpio_bank_count = 5;
1370 gpio_bank = gpio_bank_243x;
92105bb7 1371 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
56a25641 1372 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
92105bb7
TL		 1373 (rev >> 4) & 0x0f, rev & 0x0f);
1374 }
5492fb1a
SMK		 1375#endif
1376#ifdef CONFIG_ARCH_OMAP34XX
1377 if (cpu_is_omap34xx()) {
1378 int rev;
1379
1380 gpio_bank_count = OMAP34XX_NR_GPIOS;
1381 gpio_bank = gpio_bank_34xx;
1382 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1383 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1384 (rev >> 4) & 0x0f, rev & 0x0f);
1385 }
5e1c5ff4
TL		 1386#endif
1387 for (i = 0; i < gpio_bank_count; i++) {
1388 int j, gpio_count = 16;
1389
1390 bank = &gpio_bank[i];
1391 bank->reserved_map = 0;
1392 bank->base = IO_ADDRESS(bank->base);
1393 spin_lock_init(&bank->lock);
e5c56ed3 1394 if (bank_is_mpuio(bank))
5e1c5ff4 1395 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1a8bfa1e 1396#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 1397 if (bank->method == METHOD_GPIO_1510) {
1398 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1399 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1400 }
1401#endif
1402#if defined(CONFIG_ARCH_OMAP16XX)
1403 if (bank->method == METHOD_GPIO_1610) {
1404 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1405 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
92105bb7 1406 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
5e1c5ff4
TL		 1407 }
1408#endif
1409#ifdef CONFIG_ARCH_OMAP730
1410 if (bank->method == METHOD_GPIO_730) {
1411 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1412 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1413
1414 gpio_count = 32; /* 730 has 32-bit GPIOs */
1415 }
92105bb7 1416#endif
5492fb1a 1417#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 1418 if (bank->method == METHOD_GPIO_24XX) {
3ac4fa99
JY		 1419 static const u32 non_wakeup_gpios[] = {
1420 0xe203ffc0, 0x08700040
1421 };
1422
92105bb7
TL		 1423 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1424 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
14f1c3bf
JY		 1425 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1426
1427 /* Initialize interface clock ungated, module enabled */
1428 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
3ac4fa99
JY		 1429 if (i < ARRAY_SIZE(non_wakeup_gpios))
1430 bank->non_wakeup_gpios = non_wakeup_gpios[i];
92105bb7
TL		 1431 gpio_count = 32;
1432 }
5e1c5ff4
TL		 1433#endif
1434 for (j = bank->virtual_irq_start;
1435 j < bank->virtual_irq_start + gpio_count; j++) {
58781016 1436 set_irq_chip_data(j, bank);
e5c56ed3 1437 if (bank_is_mpuio(bank))
5e1c5ff4
TL		 1438 set_irq_chip(j, &mpuio_irq_chip);
1439 else
1440 set_irq_chip(j, &gpio_irq_chip);
10dd5ce2 1441 set_irq_handler(j, handle_simple_irq);
5e1c5ff4
TL		 1442 set_irq_flags(j, IRQF_VALID);
1443 }
1444 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1445 set_irq_data(bank->irq, bank);
1446 }
1447
1448 /* Enable system clock for GPIO module.
1449 * The CAM_CLK_CTRL *is* really the right place. */
92105bb7 1450 if (cpu_is_omap16xx())
5e1c5ff4
TL		 1451 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1452
5492fb1a 1453#if defined(CONFIG_ARCH_OMAP24XX)
14f1c3bf
JY		 1454 /* Enable autoidle for the OCP interface */
1455 if (cpu_is_omap24xx())
1456 omap_writel(1 << 0, 0x48019010);
5492fb1a
SMK		 1457#elif defined(CONFIG_ARCH_OMAP34XX)
1458 if (cpu_is_omap34xx())
1459 omap_writel(1 << 0, 0x48306814);
14f1c3bf 1460#endif
5e1c5ff4
TL		 1461 return 0;
1462}
1463
5492fb1a 1464#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 1465static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1466{
1467 int i;
1468
5492fb1a 1469 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1470 return 0;
1471
1472 for (i = 0; i < gpio_bank_count; i++) {
1473 struct gpio_bank *bank = &gpio_bank[i];
1474 void __iomem *wake_status;
1475 void __iomem *wake_clear;
1476 void __iomem *wake_set;
1477
1478 switch (bank->method) {
e5c56ed3 1479#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1480 case METHOD_GPIO_1610:
1481 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1482 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1483 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1484 break;
e5c56ed3 1485#endif
5492fb1a 1486#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 1487 case METHOD_GPIO_24XX:
1488 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1489 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1490 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1491 break;
e5c56ed3 1492#endif
92105bb7
TL		 1493 default:
1494 continue;
1495 }
1496
1497 spin_lock(&bank->lock);
1498 bank->saved_wakeup = __raw_readl(wake_status);
1499 __raw_writel(0xffffffff, wake_clear);
1500 __raw_writel(bank->suspend_wakeup, wake_set);
1501 spin_unlock(&bank->lock);
1502 }
1503
1504 return 0;
1505}
1506
1507static int omap_gpio_resume(struct sys_device *dev)
1508{
1509 int i;
1510
1511 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1512 return 0;
1513
1514 for (i = 0; i < gpio_bank_count; i++) {
1515 struct gpio_bank *bank = &gpio_bank[i];
1516 void __iomem *wake_clear;
1517 void __iomem *wake_set;
1518
1519 switch (bank->method) {
e5c56ed3 1520#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1521 case METHOD_GPIO_1610:
1522 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1523 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1524 break;
e5c56ed3 1525#endif
5492fb1a 1526#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 1527 case METHOD_GPIO_24XX:
0d9356cb
TL		 1528 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1529 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 1530 break;
e5c56ed3 1531#endif
92105bb7
TL		 1532 default:
1533 continue;
1534 }
1535
1536 spin_lock(&bank->lock);
1537 __raw_writel(0xffffffff, wake_clear);
1538 __raw_writel(bank->saved_wakeup, wake_set);
1539 spin_unlock(&bank->lock);
1540 }
1541
1542 return 0;
1543}
1544
1545static struct sysdev_class omap_gpio_sysclass = {
af5ca3f4 1546 .name = "gpio",
92105bb7
TL		 1547 .suspend = omap_gpio_suspend,
1548 .resume = omap_gpio_resume,
1549};
1550
1551static struct sys_device omap_gpio_device = {
1552 .id = 0,
1553 .cls = &omap_gpio_sysclass,
1554};
3ac4fa99
JY		 1555
1556#endif
1557
5492fb1a 1558#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1559
1560static int workaround_enabled;
1561
1562void omap2_gpio_prepare_for_retention(void)
1563{
1564 int i, c = 0;
1565
1566 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1567 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1568 for (i = 0; i < gpio_bank_count; i++) {
1569 struct gpio_bank *bank = &gpio_bank[i];
1570 u32 l1, l2;
1571
1572 if (!(bank->enabled_non_wakeup_gpios))
1573 continue;
5492fb1a 1574#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1575 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1576 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1577 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1578#endif
3ac4fa99
JY		 1579 bank->saved_fallingdetect = l1;
1580 bank->saved_risingdetect = l2;
1581 l1 &= ~bank->enabled_non_wakeup_gpios;
1582 l2 &= ~bank->enabled_non_wakeup_gpios;
5492fb1a 1583#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1584 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1585 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1586#endif
3ac4fa99
JY		 1587 c++;
1588 }
1589 if (!c) {
1590 workaround_enabled = 0;
1591 return;
1592 }
1593 workaround_enabled = 1;
1594}
1595
1596void omap2_gpio_resume_after_retention(void)
1597{
1598 int i;
1599
1600 if (!workaround_enabled)
1601 return;
1602 for (i = 0; i < gpio_bank_count; i++) {
1603 struct gpio_bank *bank = &gpio_bank[i];
1604 u32 l;
1605
1606 if (!(bank->enabled_non_wakeup_gpios))
1607 continue;
5492fb1a 1608#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1609 __raw_writel(bank->saved_fallingdetect,
1610 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1611 __raw_writel(bank->saved_risingdetect,
1612 bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1613#endif
3ac4fa99
JY		 1614 /* Check if any of the non-wakeup interrupt GPIOs have changed
1615 * state. If so, generate an IRQ by software. This is
1616 * horribly racy, but it's the best we can do to work around
1617 * this silicon bug. */
5492fb1a 1618#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99 1619 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
5492fb1a 1620#endif
3ac4fa99
JY		 1621 l ^= bank->saved_datain;
1622 l &= bank->non_wakeup_gpios;
1623 if (l) {
1624 u32 old0, old1;
5492fb1a 1625#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1626 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1627 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1628 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1629 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1630 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1631 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
5492fb1a 1632#endif
3ac4fa99
JY		 1633 }
1634 }
1635
1636}
1637
92105bb7
TL		 1638#endif
1639
5e1c5ff4
TL		 1640/*
1641 * This may get called early from board specific init
1a8bfa1e 1642 * for boards that have interrupts routed via FPGA.
5e1c5ff4 1643 */
277d58ef 1644int __init omap_gpio_init(void)
5e1c5ff4
TL		 1645{
1646 if (!initialized)
1647 return _omap_gpio_init();
1648 else
1649 return 0;
1650}
1651
92105bb7
TL		 1652static int __init omap_gpio_sysinit(void)
1653{
1654 int ret = 0;
1655
1656 if (!initialized)
1657 ret = _omap_gpio_init();
1658
11a78b79
DB		 1659 mpuio_init();
1660
5492fb1a
SMK		 1661#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1662 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
92105bb7
TL		 1663 if (ret == 0) {
1664 ret = sysdev_class_register(&omap_gpio_sysclass);
1665 if (ret == 0)
1666 ret = sysdev_register(&omap_gpio_device);
1667 }
1668 }
1669#endif
1670
1671 return ret;
1672}
1673
5e1c5ff4
TL		 1674EXPORT_SYMBOL(omap_request_gpio);
1675EXPORT_SYMBOL(omap_free_gpio);
1676EXPORT_SYMBOL(omap_set_gpio_direction);
1677EXPORT_SYMBOL(omap_set_gpio_dataout);
1678EXPORT_SYMBOL(omap_get_gpio_datain);
5e1c5ff4 1679
92105bb7 1680arch_initcall(omap_gpio_sysinit);
b9772a22
DB		 1681
1682
1683#ifdef CONFIG_DEBUG_FS
1684
1685#include <linux/debugfs.h>
1686#include <linux/seq_file.h>
1687
1688static int gpio_is_input(struct gpio_bank *bank, int mask)
1689{
1690 void __iomem *reg = bank->base;
1691
1692 switch (bank->method) {
1693 case METHOD_MPUIO:
1694 reg += OMAP_MPUIO_IO_CNTL;
1695 break;
1696 case METHOD_GPIO_1510:
1697 reg += OMAP1510_GPIO_DIR_CONTROL;
1698 break;
1699 case METHOD_GPIO_1610:
1700 reg += OMAP1610_GPIO_DIRECTION;
1701 break;
1702 case METHOD_GPIO_730:
1703 reg += OMAP730_GPIO_DIR_CONTROL;
1704 break;
1705 case METHOD_GPIO_24XX:
1706 reg += OMAP24XX_GPIO_OE;
1707 break;
1708 }
1709 return __raw_readl(reg) & mask;
1710}
1711
1712
1713static int dbg_gpio_show(struct seq_file *s, void *unused)
1714{
1715 unsigned i, j, gpio;
1716
1717 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1718 struct gpio_bank *bank = gpio_bank + i;
1719 unsigned bankwidth = 16;
1720 u32 mask = 1;
1721
e5c56ed3 1722 if (bank_is_mpuio(bank))
b9772a22 1723 gpio = OMAP_MPUIO(0);
5492fb1a 1724 else if (cpu_class_is_omap2() || cpu_is_omap730())
b9772a22
DB		 1725 bankwidth = 32;
1726
1727 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1728 unsigned irq, value, is_in, irqstat;
1729
1730 if (!(bank->reserved_map & mask))
1731 continue;
1732
1733 irq = bank->virtual_irq_start + j;
1734 value = omap_get_gpio_datain(gpio);
1735 is_in = gpio_is_input(bank, mask);
1736
e5c56ed3 1737 if (bank_is_mpuio(bank))
b9772a22
DB		 1738 seq_printf(s, "MPUIO %2d: ", j);
1739 else
1740 seq_printf(s, "GPIO %3d: ", gpio);
1741 seq_printf(s, "%s %s",
1742 is_in ? "in " : "out",
1743 value ? "hi" : "lo");
1744
1745 irqstat = irq_desc[irq].status;
1746 if (is_in && ((bank->suspend_wakeup & mask)
1747 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1748 char *trigger = NULL;
1749
1750 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1751 case IRQ_TYPE_EDGE_FALLING:
1752 trigger = "falling";
1753 break;
1754 case IRQ_TYPE_EDGE_RISING:
1755 trigger = "rising";
1756 break;
1757 case IRQ_TYPE_EDGE_BOTH:
1758 trigger = "bothedge";
1759 break;
1760 case IRQ_TYPE_LEVEL_LOW:
1761 trigger = "low";
1762 break;
1763 case IRQ_TYPE_LEVEL_HIGH:
1764 trigger = "high";
1765 break;
1766 case IRQ_TYPE_NONE:
1767 trigger = "(unspecified)";
1768 break;
1769 }
1770 seq_printf(s, ", irq-%d %s%s",
1771 irq, trigger,
1772 (bank->suspend_wakeup & mask)
1773 ? " wakeup" : "");
1774 }
1775 seq_printf(s, "\n");
1776 }
1777
e5c56ed3 1778 if (bank_is_mpuio(bank)) {
b9772a22
DB		 1779 seq_printf(s, "\n");
1780 gpio = 0;
1781 }
1782 }
1783 return 0;
1784}
1785
1786static int dbg_gpio_open(struct inode *inode, struct file *file)
1787{
e5c56ed3 1788 return single_open(file, dbg_gpio_show, &inode->i_private);
b9772a22
DB		 1789}
1790
1791static const struct file_operations debug_fops = {
1792 .open = dbg_gpio_open,
1793 .read = seq_read,
1794 .llseek = seq_lseek,
1795 .release = single_release,
1796};
1797
1798static int __init omap_gpio_debuginit(void)
1799{
e5c56ed3
DB		 1800 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1801 NULL, NULL, &debug_fops);
b9772a22
DB		 1802 return 0;
1803}
1804late_initcall(omap_gpio_debuginit);
1805#endif
Linux kernel - Deliverables
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