Commit | Line | Data |
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5e1c5ff4 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/gpio.c | |
3 | * | |
4 | * Support functions for OMAP GPIO | |
5 | * | |
92105bb7 | 6 | * Copyright (C) 2003-2005 Nokia Corporation |
96de0e25 | 7 | * Written by Juha Yrjölä <juha.yrjola@nokia.com> |
5e1c5ff4 TL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
5e1c5ff4 TL |
14 | #include <linux/init.h> |
15 | #include <linux/module.h> | |
5e1c5ff4 | 16 | #include <linux/interrupt.h> |
92105bb7 TL |
17 | #include <linux/sysdev.h> |
18 | #include <linux/err.h> | |
f8ce2547 | 19 | #include <linux/clk.h> |
fced80c7 | 20 | #include <linux/io.h> |
5e1c5ff4 | 21 | |
a09e64fb | 22 | #include <mach/hardware.h> |
5e1c5ff4 | 23 | #include <asm/irq.h> |
a09e64fb RK |
24 | #include <mach/irqs.h> |
25 | #include <mach/gpio.h> | |
5e1c5ff4 TL |
26 | #include <asm/mach/irq.h> |
27 | ||
5e1c5ff4 TL |
28 | /* |
29 | * OMAP1510 GPIO registers | |
30 | */ | |
7c7095aa | 31 | #define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000) |
5e1c5ff4 TL |
32 | #define OMAP1510_GPIO_DATA_INPUT 0x00 |
33 | #define OMAP1510_GPIO_DATA_OUTPUT 0x04 | |
34 | #define OMAP1510_GPIO_DIR_CONTROL 0x08 | |
35 | #define OMAP1510_GPIO_INT_CONTROL 0x0c | |
36 | #define OMAP1510_GPIO_INT_MASK 0x10 | |
37 | #define OMAP1510_GPIO_INT_STATUS 0x14 | |
38 | #define OMAP1510_GPIO_PIN_CONTROL 0x18 | |
39 | ||
40 | #define OMAP1510_IH_GPIO_BASE 64 | |
41 | ||
42 | /* | |
43 | * OMAP1610 specific GPIO registers | |
44 | */ | |
7c7095aa RK |
45 | #define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400) |
46 | #define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00) | |
47 | #define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400) | |
48 | #define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00) | |
5e1c5ff4 TL |
49 | #define OMAP1610_GPIO_REVISION 0x0000 |
50 | #define OMAP1610_GPIO_SYSCONFIG 0x0010 | |
51 | #define OMAP1610_GPIO_SYSSTATUS 0x0014 | |
52 | #define OMAP1610_GPIO_IRQSTATUS1 0x0018 | |
53 | #define OMAP1610_GPIO_IRQENABLE1 0x001c | |
92105bb7 | 54 | #define OMAP1610_GPIO_WAKEUPENABLE 0x0028 |
5e1c5ff4 TL |
55 | #define OMAP1610_GPIO_DATAIN 0x002c |
56 | #define OMAP1610_GPIO_DATAOUT 0x0030 | |
57 | #define OMAP1610_GPIO_DIRECTION 0x0034 | |
58 | #define OMAP1610_GPIO_EDGE_CTRL1 0x0038 | |
59 | #define OMAP1610_GPIO_EDGE_CTRL2 0x003c | |
60 | #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c | |
92105bb7 | 61 | #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8 |
5e1c5ff4 TL |
62 | #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0 |
63 | #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc | |
92105bb7 | 64 | #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8 |
5e1c5ff4 TL |
65 | #define OMAP1610_GPIO_SET_DATAOUT 0x00f0 |
66 | ||
67 | /* | |
68 | * OMAP730 specific GPIO registers | |
69 | */ | |
7c7095aa RK |
70 | #define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000) |
71 | #define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800) | |
72 | #define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000) | |
73 | #define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800) | |
74 | #define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000) | |
75 | #define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800) | |
5e1c5ff4 TL |
76 | #define OMAP730_GPIO_DATA_INPUT 0x00 |
77 | #define OMAP730_GPIO_DATA_OUTPUT 0x04 | |
78 | #define OMAP730_GPIO_DIR_CONTROL 0x08 | |
79 | #define OMAP730_GPIO_INT_CONTROL 0x0c | |
80 | #define OMAP730_GPIO_INT_MASK 0x10 | |
81 | #define OMAP730_GPIO_INT_STATUS 0x14 | |
82 | ||
56739a69 ZM |
83 | /* |
84 | * OMAP850 specific GPIO registers | |
85 | */ | |
86 | #define OMAP850_GPIO1_BASE IO_ADDRESS(0xfffbc000) | |
87 | #define OMAP850_GPIO2_BASE IO_ADDRESS(0xfffbc800) | |
88 | #define OMAP850_GPIO3_BASE IO_ADDRESS(0xfffbd000) | |
89 | #define OMAP850_GPIO4_BASE IO_ADDRESS(0xfffbd800) | |
90 | #define OMAP850_GPIO5_BASE IO_ADDRESS(0xfffbe000) | |
91 | #define OMAP850_GPIO6_BASE IO_ADDRESS(0xfffbe800) | |
92 | #define OMAP850_GPIO_DATA_INPUT 0x00 | |
93 | #define OMAP850_GPIO_DATA_OUTPUT 0x04 | |
94 | #define OMAP850_GPIO_DIR_CONTROL 0x08 | |
95 | #define OMAP850_GPIO_INT_CONTROL 0x0c | |
96 | #define OMAP850_GPIO_INT_MASK 0x10 | |
97 | #define OMAP850_GPIO_INT_STATUS 0x14 | |
98 | ||
92105bb7 TL |
99 | /* |
100 | * omap24xx specific GPIO registers | |
101 | */ | |
7c7095aa RK |
102 | #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000) |
103 | #define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000) | |
104 | #define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000) | |
105 | #define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000) | |
56a25641 | 106 | |
7c7095aa RK |
107 | #define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000) |
108 | #define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000) | |
109 | #define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000) | |
110 | #define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000) | |
111 | #define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000) | |
56a25641 | 112 | |
92105bb7 TL |
113 | #define OMAP24XX_GPIO_REVISION 0x0000 |
114 | #define OMAP24XX_GPIO_SYSCONFIG 0x0010 | |
115 | #define OMAP24XX_GPIO_SYSSTATUS 0x0014 | |
116 | #define OMAP24XX_GPIO_IRQSTATUS1 0x0018 | |
bee7930f HD |
117 | #define OMAP24XX_GPIO_IRQSTATUS2 0x0028 |
118 | #define OMAP24XX_GPIO_IRQENABLE2 0x002c | |
92105bb7 | 119 | #define OMAP24XX_GPIO_IRQENABLE1 0x001c |
723fdb78 | 120 | #define OMAP24XX_GPIO_WAKE_EN 0x0020 |
92105bb7 TL |
121 | #define OMAP24XX_GPIO_CTRL 0x0030 |
122 | #define OMAP24XX_GPIO_OE 0x0034 | |
123 | #define OMAP24XX_GPIO_DATAIN 0x0038 | |
124 | #define OMAP24XX_GPIO_DATAOUT 0x003c | |
125 | #define OMAP24XX_GPIO_LEVELDETECT0 0x0040 | |
126 | #define OMAP24XX_GPIO_LEVELDETECT1 0x0044 | |
127 | #define OMAP24XX_GPIO_RISINGDETECT 0x0048 | |
128 | #define OMAP24XX_GPIO_FALLINGDETECT 0x004c | |
5eb3bb9c KH |
129 | #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050 |
130 | #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054 | |
92105bb7 TL |
131 | #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060 |
132 | #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064 | |
133 | #define OMAP24XX_GPIO_CLEARWKUENA 0x0080 | |
134 | #define OMAP24XX_GPIO_SETWKUENA 0x0084 | |
135 | #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 | |
136 | #define OMAP24XX_GPIO_SETDATAOUT 0x0094 | |
137 | ||
5492fb1a SMK |
138 | /* |
139 | * omap34xx specific GPIO registers | |
140 | */ | |
141 | ||
7c7095aa RK |
142 | #define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000) |
143 | #define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000) | |
144 | #define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000) | |
145 | #define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000) | |
146 | #define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000) | |
147 | #define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000) | |
5492fb1a | 148 | |
7c7095aa | 149 | #define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE) |
5492fb1a | 150 | |
5e1c5ff4 | 151 | struct gpio_bank { |
92105bb7 | 152 | void __iomem *base; |
5e1c5ff4 TL |
153 | u16 irq; |
154 | u16 virtual_irq_start; | |
92105bb7 | 155 | int method; |
5492fb1a | 156 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
157 | u32 suspend_wakeup; |
158 | u32 saved_wakeup; | |
3ac4fa99 | 159 | #endif |
5492fb1a | 160 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
161 | u32 non_wakeup_gpios; |
162 | u32 enabled_non_wakeup_gpios; | |
163 | ||
164 | u32 saved_datain; | |
165 | u32 saved_fallingdetect; | |
166 | u32 saved_risingdetect; | |
167 | #endif | |
b144ff6f | 168 | u32 level_mask; |
5e1c5ff4 | 169 | spinlock_t lock; |
52e31344 | 170 | struct gpio_chip chip; |
89db9482 | 171 | struct clk *dbck; |
5e1c5ff4 TL |
172 | }; |
173 | ||
174 | #define METHOD_MPUIO 0 | |
175 | #define METHOD_GPIO_1510 1 | |
176 | #define METHOD_GPIO_1610 2 | |
177 | #define METHOD_GPIO_730 3 | |
56739a69 ZM |
178 | #define METHOD_GPIO_850 4 |
179 | #define METHOD_GPIO_24XX 5 | |
5e1c5ff4 | 180 | |
92105bb7 | 181 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 182 | static struct gpio_bank gpio_bank_1610[5] = { |
7c7095aa | 183 | { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO}, |
5e1c5ff4 TL |
184 | { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 }, |
185 | { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 }, | |
186 | { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 }, | |
187 | { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 }, | |
188 | }; | |
189 | #endif | |
190 | ||
1a8bfa1e | 191 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 192 | static struct gpio_bank gpio_bank_1510[2] = { |
7c7095aa | 193 | { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, |
5e1c5ff4 TL |
194 | { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 } |
195 | }; | |
196 | #endif | |
197 | ||
198 | #ifdef CONFIG_ARCH_OMAP730 | |
199 | static struct gpio_bank gpio_bank_730[7] = { | |
7c7095aa | 200 | { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, |
5e1c5ff4 TL |
201 | { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 }, |
202 | { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 }, | |
203 | { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 }, | |
204 | { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 }, | |
205 | { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 }, | |
206 | { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 }, | |
207 | }; | |
208 | #endif | |
209 | ||
56739a69 ZM |
210 | #ifdef CONFIG_ARCH_OMAP850 |
211 | static struct gpio_bank gpio_bank_850[7] = { | |
212 | { OMAP_MPUIO_BASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, | |
213 | { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 }, | |
214 | { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 }, | |
215 | { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 }, | |
216 | { OMAP850_GPIO4_BASE, INT_850_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_850 }, | |
217 | { OMAP850_GPIO5_BASE, INT_850_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_850 }, | |
218 | { OMAP850_GPIO6_BASE, INT_850_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_850 }, | |
219 | }; | |
220 | #endif | |
221 | ||
222 | ||
92105bb7 | 223 | #ifdef CONFIG_ARCH_OMAP24XX |
56a25641 SMK |
224 | |
225 | static struct gpio_bank gpio_bank_242x[4] = { | |
226 | { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, | |
227 | { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, | |
228 | { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, | |
229 | { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, | |
92105bb7 | 230 | }; |
56a25641 SMK |
231 | |
232 | static struct gpio_bank gpio_bank_243x[5] = { | |
233 | { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, | |
234 | { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, | |
235 | { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, | |
236 | { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, | |
237 | { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX }, | |
238 | }; | |
239 | ||
92105bb7 TL |
240 | #endif |
241 | ||
5492fb1a SMK |
242 | #ifdef CONFIG_ARCH_OMAP34XX |
243 | static struct gpio_bank gpio_bank_34xx[6] = { | |
244 | { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX }, | |
245 | { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX }, | |
246 | { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX }, | |
247 | { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX }, | |
248 | { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX }, | |
249 | { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX }, | |
250 | }; | |
251 | ||
252 | #endif | |
253 | ||
5e1c5ff4 TL |
254 | static struct gpio_bank *gpio_bank; |
255 | static int gpio_bank_count; | |
256 | ||
257 | static inline struct gpio_bank *get_gpio_bank(int gpio) | |
258 | { | |
6e60e79a | 259 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
260 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
261 | return &gpio_bank[0]; | |
262 | return &gpio_bank[1]; | |
263 | } | |
5e1c5ff4 TL |
264 | if (cpu_is_omap16xx()) { |
265 | if (OMAP_GPIO_IS_MPUIO(gpio)) | |
266 | return &gpio_bank[0]; | |
267 | return &gpio_bank[1 + (gpio >> 4)]; | |
268 | } | |
56739a69 | 269 | if (cpu_is_omap7xx()) { |
5e1c5ff4 TL |
270 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
271 | return &gpio_bank[0]; | |
272 | return &gpio_bank[1 + (gpio >> 5)]; | |
273 | } | |
92105bb7 TL |
274 | if (cpu_is_omap24xx()) |
275 | return &gpio_bank[gpio >> 5]; | |
5492fb1a SMK |
276 | if (cpu_is_omap34xx()) |
277 | return &gpio_bank[gpio >> 5]; | |
e031ab23 DB |
278 | BUG(); |
279 | return NULL; | |
5e1c5ff4 TL |
280 | } |
281 | ||
282 | static inline int get_gpio_index(int gpio) | |
283 | { | |
56739a69 | 284 | if (cpu_is_omap7xx()) |
5e1c5ff4 | 285 | return gpio & 0x1f; |
92105bb7 TL |
286 | if (cpu_is_omap24xx()) |
287 | return gpio & 0x1f; | |
5492fb1a SMK |
288 | if (cpu_is_omap34xx()) |
289 | return gpio & 0x1f; | |
92105bb7 | 290 | return gpio & 0x0f; |
5e1c5ff4 TL |
291 | } |
292 | ||
293 | static inline int gpio_valid(int gpio) | |
294 | { | |
295 | if (gpio < 0) | |
296 | return -1; | |
d11ac979 | 297 | if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) { |
193e68be | 298 | if (gpio >= OMAP_MAX_GPIO_LINES + 16) |
5e1c5ff4 TL |
299 | return -1; |
300 | return 0; | |
301 | } | |
6e60e79a | 302 | if (cpu_is_omap15xx() && gpio < 16) |
5e1c5ff4 | 303 | return 0; |
5e1c5ff4 TL |
304 | if ((cpu_is_omap16xx()) && gpio < 64) |
305 | return 0; | |
56739a69 | 306 | if (cpu_is_omap7xx() && gpio < 192) |
5e1c5ff4 | 307 | return 0; |
92105bb7 TL |
308 | if (cpu_is_omap24xx() && gpio < 128) |
309 | return 0; | |
5492fb1a SMK |
310 | if (cpu_is_omap34xx() && gpio < 160) |
311 | return 0; | |
5e1c5ff4 TL |
312 | return -1; |
313 | } | |
314 | ||
315 | static int check_gpio(int gpio) | |
316 | { | |
317 | if (unlikely(gpio_valid(gpio)) < 0) { | |
318 | printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio); | |
319 | dump_stack(); | |
320 | return -1; | |
321 | } | |
322 | return 0; | |
323 | } | |
324 | ||
325 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |
326 | { | |
92105bb7 | 327 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
328 | u32 l; |
329 | ||
330 | switch (bank->method) { | |
e5c56ed3 | 331 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
332 | case METHOD_MPUIO: |
333 | reg += OMAP_MPUIO_IO_CNTL; | |
334 | break; | |
e5c56ed3 DB |
335 | #endif |
336 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
337 | case METHOD_GPIO_1510: |
338 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
339 | break; | |
e5c56ed3 DB |
340 | #endif |
341 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
342 | case METHOD_GPIO_1610: |
343 | reg += OMAP1610_GPIO_DIRECTION; | |
344 | break; | |
e5c56ed3 DB |
345 | #endif |
346 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
347 | case METHOD_GPIO_730: |
348 | reg += OMAP730_GPIO_DIR_CONTROL; | |
349 | break; | |
e5c56ed3 | 350 | #endif |
56739a69 ZM |
351 | #ifdef CONFIG_ARCH_OMAP850 |
352 | case METHOD_GPIO_850: | |
353 | reg += OMAP850_GPIO_DIR_CONTROL; | |
354 | break; | |
355 | #endif | |
5492fb1a | 356 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
357 | case METHOD_GPIO_24XX: |
358 | reg += OMAP24XX_GPIO_OE; | |
359 | break; | |
e5c56ed3 DB |
360 | #endif |
361 | default: | |
362 | WARN_ON(1); | |
363 | return; | |
5e1c5ff4 TL |
364 | } |
365 | l = __raw_readl(reg); | |
366 | if (is_input) | |
367 | l |= 1 << gpio; | |
368 | else | |
369 | l &= ~(1 << gpio); | |
370 | __raw_writel(l, reg); | |
371 | } | |
372 | ||
5e1c5ff4 TL |
373 | static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) |
374 | { | |
92105bb7 | 375 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
376 | u32 l = 0; |
377 | ||
378 | switch (bank->method) { | |
e5c56ed3 | 379 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
380 | case METHOD_MPUIO: |
381 | reg += OMAP_MPUIO_OUTPUT; | |
382 | l = __raw_readl(reg); | |
383 | if (enable) | |
384 | l |= 1 << gpio; | |
385 | else | |
386 | l &= ~(1 << gpio); | |
387 | break; | |
e5c56ed3 DB |
388 | #endif |
389 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
390 | case METHOD_GPIO_1510: |
391 | reg += OMAP1510_GPIO_DATA_OUTPUT; | |
392 | l = __raw_readl(reg); | |
393 | if (enable) | |
394 | l |= 1 << gpio; | |
395 | else | |
396 | l &= ~(1 << gpio); | |
397 | break; | |
e5c56ed3 DB |
398 | #endif |
399 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
400 | case METHOD_GPIO_1610: |
401 | if (enable) | |
402 | reg += OMAP1610_GPIO_SET_DATAOUT; | |
403 | else | |
404 | reg += OMAP1610_GPIO_CLEAR_DATAOUT; | |
405 | l = 1 << gpio; | |
406 | break; | |
e5c56ed3 DB |
407 | #endif |
408 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
409 | case METHOD_GPIO_730: |
410 | reg += OMAP730_GPIO_DATA_OUTPUT; | |
411 | l = __raw_readl(reg); | |
412 | if (enable) | |
413 | l |= 1 << gpio; | |
414 | else | |
415 | l &= ~(1 << gpio); | |
416 | break; | |
e5c56ed3 | 417 | #endif |
56739a69 ZM |
418 | #ifdef CONFIG_ARCH_OMAP850 |
419 | case METHOD_GPIO_850: | |
420 | reg += OMAP850_GPIO_DATA_OUTPUT; | |
421 | l = __raw_readl(reg); | |
422 | if (enable) | |
423 | l |= 1 << gpio; | |
424 | else | |
425 | l &= ~(1 << gpio); | |
426 | break; | |
427 | #endif | |
5492fb1a | 428 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
429 | case METHOD_GPIO_24XX: |
430 | if (enable) | |
431 | reg += OMAP24XX_GPIO_SETDATAOUT; | |
432 | else | |
433 | reg += OMAP24XX_GPIO_CLEARDATAOUT; | |
434 | l = 1 << gpio; | |
435 | break; | |
e5c56ed3 | 436 | #endif |
5e1c5ff4 | 437 | default: |
e5c56ed3 | 438 | WARN_ON(1); |
5e1c5ff4 TL |
439 | return; |
440 | } | |
441 | __raw_writel(l, reg); | |
442 | } | |
443 | ||
0b84b5ca | 444 | static int __omap_get_gpio_datain(int gpio) |
5e1c5ff4 TL |
445 | { |
446 | struct gpio_bank *bank; | |
92105bb7 | 447 | void __iomem *reg; |
5e1c5ff4 TL |
448 | |
449 | if (check_gpio(gpio) < 0) | |
e5c56ed3 | 450 | return -EINVAL; |
5e1c5ff4 TL |
451 | bank = get_gpio_bank(gpio); |
452 | reg = bank->base; | |
453 | switch (bank->method) { | |
e5c56ed3 | 454 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
455 | case METHOD_MPUIO: |
456 | reg += OMAP_MPUIO_INPUT_LATCH; | |
457 | break; | |
e5c56ed3 DB |
458 | #endif |
459 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
460 | case METHOD_GPIO_1510: |
461 | reg += OMAP1510_GPIO_DATA_INPUT; | |
462 | break; | |
e5c56ed3 DB |
463 | #endif |
464 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
465 | case METHOD_GPIO_1610: |
466 | reg += OMAP1610_GPIO_DATAIN; | |
467 | break; | |
e5c56ed3 DB |
468 | #endif |
469 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
470 | case METHOD_GPIO_730: |
471 | reg += OMAP730_GPIO_DATA_INPUT; | |
472 | break; | |
e5c56ed3 | 473 | #endif |
56739a69 ZM |
474 | #ifdef CONFIG_ARCH_OMAP850 |
475 | case METHOD_GPIO_850: | |
476 | reg += OMAP850_GPIO_DATA_INPUT; | |
477 | break; | |
478 | #endif | |
5492fb1a | 479 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
480 | case METHOD_GPIO_24XX: |
481 | reg += OMAP24XX_GPIO_DATAIN; | |
482 | break; | |
e5c56ed3 | 483 | #endif |
5e1c5ff4 | 484 | default: |
e5c56ed3 | 485 | return -EINVAL; |
5e1c5ff4 | 486 | } |
92105bb7 TL |
487 | return (__raw_readl(reg) |
488 | & (1 << get_gpio_index(gpio))) != 0; | |
5e1c5ff4 TL |
489 | } |
490 | ||
92105bb7 TL |
491 | #define MOD_REG_BIT(reg, bit_mask, set) \ |
492 | do { \ | |
493 | int l = __raw_readl(base + reg); \ | |
494 | if (set) l |= bit_mask; \ | |
495 | else l &= ~bit_mask; \ | |
496 | __raw_writel(l, base + reg); \ | |
497 | } while(0) | |
498 | ||
5eb3bb9c KH |
499 | void omap_set_gpio_debounce(int gpio, int enable) |
500 | { | |
501 | struct gpio_bank *bank; | |
502 | void __iomem *reg; | |
e031ab23 | 503 | unsigned long flags; |
5eb3bb9c KH |
504 | u32 val, l = 1 << get_gpio_index(gpio); |
505 | ||
506 | if (cpu_class_is_omap1()) | |
507 | return; | |
508 | ||
509 | bank = get_gpio_bank(gpio); | |
510 | reg = bank->base; | |
5eb3bb9c | 511 | reg += OMAP24XX_GPIO_DEBOUNCE_EN; |
e031ab23 DB |
512 | |
513 | spin_lock_irqsave(&bank->lock, flags); | |
5eb3bb9c KH |
514 | val = __raw_readl(reg); |
515 | ||
89db9482 | 516 | if (enable && !(val & l)) |
5eb3bb9c | 517 | val |= l; |
e031ab23 | 518 | else if (!enable && (val & l)) |
5eb3bb9c | 519 | val &= ~l; |
89db9482 | 520 | else |
e031ab23 | 521 | goto done; |
89db9482 | 522 | |
e031ab23 DB |
523 | if (cpu_is_omap34xx()) { |
524 | if (enable) | |
525 | clk_enable(bank->dbck); | |
526 | else | |
527 | clk_disable(bank->dbck); | |
528 | } | |
5eb3bb9c KH |
529 | |
530 | __raw_writel(val, reg); | |
e031ab23 DB |
531 | done: |
532 | spin_unlock_irqrestore(&bank->lock, flags); | |
5eb3bb9c KH |
533 | } |
534 | EXPORT_SYMBOL(omap_set_gpio_debounce); | |
535 | ||
536 | void omap_set_gpio_debounce_time(int gpio, int enc_time) | |
537 | { | |
538 | struct gpio_bank *bank; | |
539 | void __iomem *reg; | |
540 | ||
541 | if (cpu_class_is_omap1()) | |
542 | return; | |
543 | ||
544 | bank = get_gpio_bank(gpio); | |
545 | reg = bank->base; | |
546 | ||
547 | enc_time &= 0xff; | |
548 | reg += OMAP24XX_GPIO_DEBOUNCE_VAL; | |
549 | __raw_writel(enc_time, reg); | |
550 | } | |
551 | EXPORT_SYMBOL(omap_set_gpio_debounce_time); | |
552 | ||
5492fb1a | 553 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
5eb3bb9c KH |
554 | static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, |
555 | int trigger) | |
5e1c5ff4 | 556 | { |
3ac4fa99 | 557 | void __iomem *base = bank->base; |
92105bb7 TL |
558 | u32 gpio_bit = 1 << gpio; |
559 | ||
560 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, | |
6cab4860 | 561 | trigger & IRQ_TYPE_LEVEL_LOW); |
92105bb7 | 562 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, |
6cab4860 | 563 | trigger & IRQ_TYPE_LEVEL_HIGH); |
92105bb7 | 564 | MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, |
6cab4860 | 565 | trigger & IRQ_TYPE_EDGE_RISING); |
92105bb7 | 566 | MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, |
6cab4860 | 567 | trigger & IRQ_TYPE_EDGE_FALLING); |
5eb3bb9c | 568 | |
3ac4fa99 JY |
569 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { |
570 | if (trigger != 0) | |
5eb3bb9c KH |
571 | __raw_writel(1 << gpio, bank->base |
572 | + OMAP24XX_GPIO_SETWKUENA); | |
3ac4fa99 | 573 | else |
5eb3bb9c KH |
574 | __raw_writel(1 << gpio, bank->base |
575 | + OMAP24XX_GPIO_CLEARWKUENA); | |
3ac4fa99 JY |
576 | } else { |
577 | if (trigger != 0) | |
578 | bank->enabled_non_wakeup_gpios |= gpio_bit; | |
579 | else | |
580 | bank->enabled_non_wakeup_gpios &= ~gpio_bit; | |
581 | } | |
5eb3bb9c | 582 | |
b144ff6f KH |
583 | bank->level_mask = |
584 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) | | |
585 | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
92105bb7 | 586 | } |
3ac4fa99 | 587 | #endif |
92105bb7 TL |
588 | |
589 | static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) | |
590 | { | |
591 | void __iomem *reg = bank->base; | |
592 | u32 l = 0; | |
5e1c5ff4 TL |
593 | |
594 | switch (bank->method) { | |
e5c56ed3 | 595 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
596 | case METHOD_MPUIO: |
597 | reg += OMAP_MPUIO_GPIO_INT_EDGE; | |
598 | l = __raw_readl(reg); | |
6cab4860 | 599 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 600 | l |= 1 << gpio; |
6cab4860 | 601 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 602 | l &= ~(1 << gpio); |
92105bb7 TL |
603 | else |
604 | goto bad; | |
5e1c5ff4 | 605 | break; |
e5c56ed3 DB |
606 | #endif |
607 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
608 | case METHOD_GPIO_1510: |
609 | reg += OMAP1510_GPIO_INT_CONTROL; | |
610 | l = __raw_readl(reg); | |
6cab4860 | 611 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 612 | l |= 1 << gpio; |
6cab4860 | 613 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 614 | l &= ~(1 << gpio); |
92105bb7 TL |
615 | else |
616 | goto bad; | |
5e1c5ff4 | 617 | break; |
e5c56ed3 | 618 | #endif |
3ac4fa99 | 619 | #ifdef CONFIG_ARCH_OMAP16XX |
5e1c5ff4 | 620 | case METHOD_GPIO_1610: |
5e1c5ff4 TL |
621 | if (gpio & 0x08) |
622 | reg += OMAP1610_GPIO_EDGE_CTRL2; | |
623 | else | |
624 | reg += OMAP1610_GPIO_EDGE_CTRL1; | |
625 | gpio &= 0x07; | |
626 | l = __raw_readl(reg); | |
627 | l &= ~(3 << (gpio << 1)); | |
6cab4860 | 628 | if (trigger & IRQ_TYPE_EDGE_RISING) |
6e60e79a | 629 | l |= 2 << (gpio << 1); |
6cab4860 | 630 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
6e60e79a | 631 | l |= 1 << (gpio << 1); |
3ac4fa99 JY |
632 | if (trigger) |
633 | /* Enable wake-up during idle for dynamic tick */ | |
634 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA); | |
635 | else | |
636 | __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); | |
5e1c5ff4 | 637 | break; |
3ac4fa99 JY |
638 | #endif |
639 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
640 | case METHOD_GPIO_730: |
641 | reg += OMAP730_GPIO_INT_CONTROL; | |
642 | l = __raw_readl(reg); | |
6cab4860 | 643 | if (trigger & IRQ_TYPE_EDGE_RISING) |
5e1c5ff4 | 644 | l |= 1 << gpio; |
6cab4860 | 645 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
5e1c5ff4 | 646 | l &= ~(1 << gpio); |
92105bb7 TL |
647 | else |
648 | goto bad; | |
649 | break; | |
3ac4fa99 | 650 | #endif |
56739a69 ZM |
651 | #ifdef CONFIG_ARCH_OMAP850 |
652 | case METHOD_GPIO_850: | |
653 | reg += OMAP850_GPIO_INT_CONTROL; | |
654 | l = __raw_readl(reg); | |
655 | if (trigger & IRQ_TYPE_EDGE_RISING) | |
656 | l |= 1 << gpio; | |
657 | else if (trigger & IRQ_TYPE_EDGE_FALLING) | |
658 | l &= ~(1 << gpio); | |
659 | else | |
660 | goto bad; | |
661 | break; | |
662 | #endif | |
5492fb1a | 663 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 | 664 | case METHOD_GPIO_24XX: |
3ac4fa99 | 665 | set_24xx_gpio_triggering(bank, gpio, trigger); |
5e1c5ff4 | 666 | break; |
3ac4fa99 | 667 | #endif |
5e1c5ff4 | 668 | default: |
92105bb7 | 669 | goto bad; |
5e1c5ff4 | 670 | } |
92105bb7 TL |
671 | __raw_writel(l, reg); |
672 | return 0; | |
673 | bad: | |
674 | return -EINVAL; | |
5e1c5ff4 TL |
675 | } |
676 | ||
92105bb7 | 677 | static int gpio_irq_type(unsigned irq, unsigned type) |
5e1c5ff4 TL |
678 | { |
679 | struct gpio_bank *bank; | |
92105bb7 TL |
680 | unsigned gpio; |
681 | int retval; | |
a6472533 | 682 | unsigned long flags; |
92105bb7 | 683 | |
5492fb1a | 684 | if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE) |
92105bb7 TL |
685 | gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); |
686 | else | |
687 | gpio = irq - IH_GPIO_BASE; | |
5e1c5ff4 TL |
688 | |
689 | if (check_gpio(gpio) < 0) | |
92105bb7 TL |
690 | return -EINVAL; |
691 | ||
e5c56ed3 | 692 | if (type & ~IRQ_TYPE_SENSE_MASK) |
6e60e79a | 693 | return -EINVAL; |
e5c56ed3 DB |
694 | |
695 | /* OMAP1 allows only only edge triggering */ | |
5492fb1a | 696 | if (!cpu_class_is_omap2() |
e5c56ed3 | 697 | && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) |
92105bb7 TL |
698 | return -EINVAL; |
699 | ||
58781016 | 700 | bank = get_irq_chip_data(irq); |
a6472533 | 701 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 702 | retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); |
b9772a22 DB |
703 | if (retval == 0) { |
704 | irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK; | |
705 | irq_desc[irq].status |= type; | |
706 | } | |
a6472533 | 707 | spin_unlock_irqrestore(&bank->lock, flags); |
672e302e KH |
708 | |
709 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
710 | __set_irq_handler_unlocked(irq, handle_level_irq); | |
711 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
712 | __set_irq_handler_unlocked(irq, handle_edge_irq); | |
713 | ||
92105bb7 | 714 | return retval; |
5e1c5ff4 TL |
715 | } |
716 | ||
717 | static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |
718 | { | |
92105bb7 | 719 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
720 | |
721 | switch (bank->method) { | |
e5c56ed3 | 722 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
723 | case METHOD_MPUIO: |
724 | /* MPUIO irqstatus is reset by reading the status register, | |
725 | * so do nothing here */ | |
726 | return; | |
e5c56ed3 DB |
727 | #endif |
728 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
729 | case METHOD_GPIO_1510: |
730 | reg += OMAP1510_GPIO_INT_STATUS; | |
731 | break; | |
e5c56ed3 DB |
732 | #endif |
733 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
734 | case METHOD_GPIO_1610: |
735 | reg += OMAP1610_GPIO_IRQSTATUS1; | |
736 | break; | |
e5c56ed3 DB |
737 | #endif |
738 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
739 | case METHOD_GPIO_730: |
740 | reg += OMAP730_GPIO_INT_STATUS; | |
741 | break; | |
e5c56ed3 | 742 | #endif |
56739a69 ZM |
743 | #ifdef CONFIG_ARCH_OMAP850 |
744 | case METHOD_GPIO_850: | |
745 | reg += OMAP850_GPIO_INT_STATUS; | |
746 | break; | |
747 | #endif | |
5492fb1a | 748 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
749 | case METHOD_GPIO_24XX: |
750 | reg += OMAP24XX_GPIO_IRQSTATUS1; | |
751 | break; | |
e5c56ed3 | 752 | #endif |
5e1c5ff4 | 753 | default: |
e5c56ed3 | 754 | WARN_ON(1); |
5e1c5ff4 TL |
755 | return; |
756 | } | |
757 | __raw_writel(gpio_mask, reg); | |
bee7930f HD |
758 | |
759 | /* Workaround for clearing DSP GPIO interrupts to allow retention */ | |
5492fb1a SMK |
760 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
761 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
bee7930f | 762 | __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2); |
5492fb1a | 763 | #endif |
5e1c5ff4 TL |
764 | } |
765 | ||
766 | static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) | |
767 | { | |
768 | _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio)); | |
769 | } | |
770 | ||
ea6dedd7 ID |
771 | static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) |
772 | { | |
773 | void __iomem *reg = bank->base; | |
99c47707 ID |
774 | int inv = 0; |
775 | u32 l; | |
776 | u32 mask; | |
ea6dedd7 ID |
777 | |
778 | switch (bank->method) { | |
e5c56ed3 | 779 | #ifdef CONFIG_ARCH_OMAP1 |
ea6dedd7 ID |
780 | case METHOD_MPUIO: |
781 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
99c47707 ID |
782 | mask = 0xffff; |
783 | inv = 1; | |
ea6dedd7 | 784 | break; |
e5c56ed3 DB |
785 | #endif |
786 | #ifdef CONFIG_ARCH_OMAP15XX | |
ea6dedd7 ID |
787 | case METHOD_GPIO_1510: |
788 | reg += OMAP1510_GPIO_INT_MASK; | |
99c47707 ID |
789 | mask = 0xffff; |
790 | inv = 1; | |
ea6dedd7 | 791 | break; |
e5c56ed3 DB |
792 | #endif |
793 | #ifdef CONFIG_ARCH_OMAP16XX | |
ea6dedd7 ID |
794 | case METHOD_GPIO_1610: |
795 | reg += OMAP1610_GPIO_IRQENABLE1; | |
99c47707 | 796 | mask = 0xffff; |
ea6dedd7 | 797 | break; |
e5c56ed3 DB |
798 | #endif |
799 | #ifdef CONFIG_ARCH_OMAP730 | |
ea6dedd7 ID |
800 | case METHOD_GPIO_730: |
801 | reg += OMAP730_GPIO_INT_MASK; | |
99c47707 ID |
802 | mask = 0xffffffff; |
803 | inv = 1; | |
ea6dedd7 | 804 | break; |
e5c56ed3 | 805 | #endif |
56739a69 ZM |
806 | #ifdef CONFIG_ARCH_OMAP850 |
807 | case METHOD_GPIO_850: | |
808 | reg += OMAP850_GPIO_INT_MASK; | |
809 | mask = 0xffffffff; | |
810 | inv = 1; | |
811 | break; | |
812 | #endif | |
5492fb1a | 813 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
ea6dedd7 ID |
814 | case METHOD_GPIO_24XX: |
815 | reg += OMAP24XX_GPIO_IRQENABLE1; | |
99c47707 | 816 | mask = 0xffffffff; |
ea6dedd7 | 817 | break; |
e5c56ed3 | 818 | #endif |
ea6dedd7 | 819 | default: |
e5c56ed3 | 820 | WARN_ON(1); |
ea6dedd7 ID |
821 | return 0; |
822 | } | |
823 | ||
99c47707 ID |
824 | l = __raw_readl(reg); |
825 | if (inv) | |
826 | l = ~l; | |
827 | l &= mask; | |
828 | return l; | |
ea6dedd7 ID |
829 | } |
830 | ||
5e1c5ff4 TL |
831 | static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable) |
832 | { | |
92105bb7 | 833 | void __iomem *reg = bank->base; |
5e1c5ff4 TL |
834 | u32 l; |
835 | ||
836 | switch (bank->method) { | |
e5c56ed3 | 837 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
838 | case METHOD_MPUIO: |
839 | reg += OMAP_MPUIO_GPIO_MASKIT; | |
840 | l = __raw_readl(reg); | |
841 | if (enable) | |
842 | l &= ~(gpio_mask); | |
843 | else | |
844 | l |= gpio_mask; | |
845 | break; | |
e5c56ed3 DB |
846 | #endif |
847 | #ifdef CONFIG_ARCH_OMAP15XX | |
5e1c5ff4 TL |
848 | case METHOD_GPIO_1510: |
849 | reg += OMAP1510_GPIO_INT_MASK; | |
850 | l = __raw_readl(reg); | |
851 | if (enable) | |
852 | l &= ~(gpio_mask); | |
853 | else | |
854 | l |= gpio_mask; | |
855 | break; | |
e5c56ed3 DB |
856 | #endif |
857 | #ifdef CONFIG_ARCH_OMAP16XX | |
5e1c5ff4 TL |
858 | case METHOD_GPIO_1610: |
859 | if (enable) | |
860 | reg += OMAP1610_GPIO_SET_IRQENABLE1; | |
861 | else | |
862 | reg += OMAP1610_GPIO_CLEAR_IRQENABLE1; | |
863 | l = gpio_mask; | |
864 | break; | |
e5c56ed3 DB |
865 | #endif |
866 | #ifdef CONFIG_ARCH_OMAP730 | |
5e1c5ff4 TL |
867 | case METHOD_GPIO_730: |
868 | reg += OMAP730_GPIO_INT_MASK; | |
869 | l = __raw_readl(reg); | |
870 | if (enable) | |
871 | l &= ~(gpio_mask); | |
872 | else | |
873 | l |= gpio_mask; | |
874 | break; | |
e5c56ed3 | 875 | #endif |
56739a69 ZM |
876 | #ifdef CONFIG_ARCH_OMAP850 |
877 | case METHOD_GPIO_850: | |
878 | reg += OMAP850_GPIO_INT_MASK; | |
879 | l = __raw_readl(reg); | |
880 | if (enable) | |
881 | l &= ~(gpio_mask); | |
882 | else | |
883 | l |= gpio_mask; | |
884 | break; | |
885 | #endif | |
5492fb1a | 886 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
887 | case METHOD_GPIO_24XX: |
888 | if (enable) | |
889 | reg += OMAP24XX_GPIO_SETIRQENABLE1; | |
890 | else | |
891 | reg += OMAP24XX_GPIO_CLEARIRQENABLE1; | |
892 | l = gpio_mask; | |
893 | break; | |
e5c56ed3 | 894 | #endif |
5e1c5ff4 | 895 | default: |
e5c56ed3 | 896 | WARN_ON(1); |
5e1c5ff4 TL |
897 | return; |
898 | } | |
899 | __raw_writel(l, reg); | |
900 | } | |
901 | ||
902 | static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) | |
903 | { | |
904 | _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable); | |
905 | } | |
906 | ||
92105bb7 TL |
907 | /* |
908 | * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. | |
909 | * 1510 does not seem to have a wake-up register. If JTAG is connected | |
910 | * to the target, system will wake up always on GPIO events. While | |
911 | * system is running all registered GPIO interrupts need to have wake-up | |
912 | * enabled. When system is suspended, only selected GPIO interrupts need | |
913 | * to have wake-up enabled. | |
914 | */ | |
915 | static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) | |
916 | { | |
a6472533 DB |
917 | unsigned long flags; |
918 | ||
92105bb7 | 919 | switch (bank->method) { |
3ac4fa99 | 920 | #ifdef CONFIG_ARCH_OMAP16XX |
11a78b79 | 921 | case METHOD_MPUIO: |
92105bb7 | 922 | case METHOD_GPIO_1610: |
a6472533 | 923 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 924 | if (enable) { |
92105bb7 | 925 | bank->suspend_wakeup |= (1 << gpio); |
11a78b79 DB |
926 | enable_irq_wake(bank->irq); |
927 | } else { | |
928 | disable_irq_wake(bank->irq); | |
92105bb7 | 929 | bank->suspend_wakeup &= ~(1 << gpio); |
11a78b79 | 930 | } |
a6472533 | 931 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 | 932 | return 0; |
3ac4fa99 | 933 | #endif |
5492fb1a | 934 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 | 935 | case METHOD_GPIO_24XX: |
11a78b79 DB |
936 | if (bank->non_wakeup_gpios & (1 << gpio)) { |
937 | printk(KERN_ERR "Unable to modify wakeup on " | |
938 | "non-wakeup GPIO%d\n", | |
939 | (bank - gpio_bank) * 32 + gpio); | |
940 | return -EINVAL; | |
941 | } | |
a6472533 | 942 | spin_lock_irqsave(&bank->lock, flags); |
3ac4fa99 | 943 | if (enable) { |
3ac4fa99 | 944 | bank->suspend_wakeup |= (1 << gpio); |
11a78b79 DB |
945 | enable_irq_wake(bank->irq); |
946 | } else { | |
947 | disable_irq_wake(bank->irq); | |
3ac4fa99 | 948 | bank->suspend_wakeup &= ~(1 << gpio); |
11a78b79 | 949 | } |
a6472533 | 950 | spin_unlock_irqrestore(&bank->lock, flags); |
3ac4fa99 JY |
951 | return 0; |
952 | #endif | |
92105bb7 TL |
953 | default: |
954 | printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n", | |
955 | bank->method); | |
956 | return -EINVAL; | |
957 | } | |
958 | } | |
959 | ||
4196dd6b TL |
960 | static void _reset_gpio(struct gpio_bank *bank, int gpio) |
961 | { | |
962 | _set_gpio_direction(bank, get_gpio_index(gpio), 1); | |
963 | _set_gpio_irqenable(bank, gpio, 0); | |
964 | _clear_gpio_irqstatus(bank, gpio); | |
6cab4860 | 965 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); |
4196dd6b TL |
966 | } |
967 | ||
92105bb7 TL |
968 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
969 | static int gpio_wake_enable(unsigned int irq, unsigned int enable) | |
970 | { | |
971 | unsigned int gpio = irq - IH_GPIO_BASE; | |
972 | struct gpio_bank *bank; | |
973 | int retval; | |
974 | ||
975 | if (check_gpio(gpio) < 0) | |
976 | return -ENODEV; | |
58781016 | 977 | bank = get_irq_chip_data(irq); |
92105bb7 | 978 | retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); |
92105bb7 TL |
979 | |
980 | return retval; | |
981 | } | |
982 | ||
3ff164e1 | 983 | static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 984 | { |
3ff164e1 | 985 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 986 | unsigned long flags; |
52e31344 | 987 | |
a6472533 | 988 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 | 989 | |
4196dd6b TL |
990 | /* Set trigger to none. You need to enable the desired trigger with |
991 | * request_irq() or set_irq_type(). | |
992 | */ | |
3ff164e1 | 993 | _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); |
92105bb7 | 994 | |
1a8bfa1e | 995 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 996 | if (bank->method == METHOD_GPIO_1510) { |
92105bb7 | 997 | void __iomem *reg; |
5e1c5ff4 | 998 | |
92105bb7 | 999 | /* Claim the pin for MPU */ |
5e1c5ff4 | 1000 | reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; |
3ff164e1 | 1001 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
5e1c5ff4 TL |
1002 | } |
1003 | #endif | |
a6472533 | 1004 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
1005 | |
1006 | return 0; | |
1007 | } | |
1008 | ||
3ff164e1 | 1009 | static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) |
5e1c5ff4 | 1010 | { |
3ff164e1 | 1011 | struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); |
a6472533 | 1012 | unsigned long flags; |
5e1c5ff4 | 1013 | |
a6472533 | 1014 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1015 | #ifdef CONFIG_ARCH_OMAP16XX |
1016 | if (bank->method == METHOD_GPIO_1610) { | |
1017 | /* Disable wake-up during idle for dynamic tick */ | |
1018 | void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
3ff164e1 | 1019 | __raw_writel(1 << offset, reg); |
92105bb7 TL |
1020 | } |
1021 | #endif | |
5492fb1a | 1022 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
1023 | if (bank->method == METHOD_GPIO_24XX) { |
1024 | /* Disable wake-up during idle for dynamic tick */ | |
1025 | void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; | |
3ff164e1 | 1026 | __raw_writel(1 << offset, reg); |
92105bb7 TL |
1027 | } |
1028 | #endif | |
3ff164e1 | 1029 | _reset_gpio(bank, bank->chip.base + offset); |
a6472533 | 1030 | spin_unlock_irqrestore(&bank->lock, flags); |
5e1c5ff4 TL |
1031 | } |
1032 | ||
1033 | /* | |
1034 | * We need to unmask the GPIO bank interrupt as soon as possible to | |
1035 | * avoid missing GPIO interrupts for other lines in the bank. | |
1036 | * Then we need to mask-read-clear-unmask the triggered GPIO lines | |
1037 | * in the bank to avoid missing nested interrupts for a GPIO line. | |
1038 | * If we wait to unmask individual GPIO lines in the bank after the | |
1039 | * line's interrupt handler has been run, we may miss some nested | |
1040 | * interrupts. | |
1041 | */ | |
10dd5ce2 | 1042 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
5e1c5ff4 | 1043 | { |
92105bb7 | 1044 | void __iomem *isr_reg = NULL; |
5e1c5ff4 TL |
1045 | u32 isr; |
1046 | unsigned int gpio_irq; | |
1047 | struct gpio_bank *bank; | |
ea6dedd7 ID |
1048 | u32 retrigger = 0; |
1049 | int unmasked = 0; | |
5e1c5ff4 TL |
1050 | |
1051 | desc->chip->ack(irq); | |
1052 | ||
418ca1f0 | 1053 | bank = get_irq_data(irq); |
e5c56ed3 | 1054 | #ifdef CONFIG_ARCH_OMAP1 |
5e1c5ff4 TL |
1055 | if (bank->method == METHOD_MPUIO) |
1056 | isr_reg = bank->base + OMAP_MPUIO_GPIO_INT; | |
e5c56ed3 | 1057 | #endif |
1a8bfa1e | 1058 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 TL |
1059 | if (bank->method == METHOD_GPIO_1510) |
1060 | isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS; | |
1061 | #endif | |
1062 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1063 | if (bank->method == METHOD_GPIO_1610) | |
1064 | isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1; | |
1065 | #endif | |
1066 | #ifdef CONFIG_ARCH_OMAP730 | |
1067 | if (bank->method == METHOD_GPIO_730) | |
1068 | isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; | |
1069 | #endif | |
56739a69 ZM |
1070 | #ifdef CONFIG_ARCH_OMAP850 |
1071 | if (bank->method == METHOD_GPIO_850) | |
1072 | isr_reg = bank->base + OMAP850_GPIO_INT_STATUS; | |
1073 | #endif | |
5492fb1a | 1074 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
1075 | if (bank->method == METHOD_GPIO_24XX) |
1076 | isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; | |
1077 | #endif | |
92105bb7 | 1078 | while(1) { |
6e60e79a | 1079 | u32 isr_saved, level_mask = 0; |
ea6dedd7 | 1080 | u32 enabled; |
6e60e79a | 1081 | |
ea6dedd7 ID |
1082 | enabled = _get_gpio_irqbank_mask(bank); |
1083 | isr_saved = isr = __raw_readl(isr_reg) & enabled; | |
6e60e79a TL |
1084 | |
1085 | if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) | |
1086 | isr &= 0x0000ffff; | |
1087 | ||
5492fb1a | 1088 | if (cpu_class_is_omap2()) { |
b144ff6f | 1089 | level_mask = bank->level_mask & enabled; |
ea6dedd7 | 1090 | } |
6e60e79a TL |
1091 | |
1092 | /* clear edge sensitive interrupts before handler(s) are | |
1093 | called so that we don't miss any interrupt occurred while | |
1094 | executing them */ | |
1095 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0); | |
1096 | _clear_gpio_irqbank(bank, isr_saved & ~level_mask); | |
1097 | _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1); | |
1098 | ||
1099 | /* if there is only edge sensitive GPIO pin interrupts | |
1100 | configured, we could unmask GPIO bank interrupt immediately */ | |
ea6dedd7 ID |
1101 | if (!level_mask && !unmasked) { |
1102 | unmasked = 1; | |
6e60e79a | 1103 | desc->chip->unmask(irq); |
ea6dedd7 | 1104 | } |
92105bb7 | 1105 | |
ea6dedd7 ID |
1106 | isr |= retrigger; |
1107 | retrigger = 0; | |
92105bb7 TL |
1108 | if (!isr) |
1109 | break; | |
1110 | ||
1111 | gpio_irq = bank->virtual_irq_start; | |
1112 | for (; isr != 0; isr >>= 1, gpio_irq++) { | |
92105bb7 TL |
1113 | if (!(isr & 1)) |
1114 | continue; | |
29454dde | 1115 | |
d8aa0251 | 1116 | generic_handle_irq(gpio_irq); |
92105bb7 | 1117 | } |
1a8bfa1e | 1118 | } |
ea6dedd7 ID |
1119 | /* if bank has any level sensitive GPIO pin interrupt |
1120 | configured, we must unmask the bank interrupt only after | |
1121 | handler(s) are executed in order to avoid spurious bank | |
1122 | interrupt */ | |
1123 | if (!unmasked) | |
1124 | desc->chip->unmask(irq); | |
1125 | ||
5e1c5ff4 TL |
1126 | } |
1127 | ||
4196dd6b TL |
1128 | static void gpio_irq_shutdown(unsigned int irq) |
1129 | { | |
1130 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1131 | struct gpio_bank *bank = get_irq_chip_data(irq); |
4196dd6b TL |
1132 | |
1133 | _reset_gpio(bank, gpio); | |
1134 | } | |
1135 | ||
5e1c5ff4 TL |
1136 | static void gpio_ack_irq(unsigned int irq) |
1137 | { | |
1138 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1139 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1140 | |
1141 | _clear_gpio_irqstatus(bank, gpio); | |
1142 | } | |
1143 | ||
1144 | static void gpio_mask_irq(unsigned int irq) | |
1145 | { | |
1146 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1147 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1148 | |
1149 | _set_gpio_irqenable(bank, gpio, 0); | |
1150 | } | |
1151 | ||
1152 | static void gpio_unmask_irq(unsigned int irq) | |
1153 | { | |
1154 | unsigned int gpio = irq - IH_GPIO_BASE; | |
58781016 | 1155 | struct gpio_bank *bank = get_irq_chip_data(irq); |
b144ff6f KH |
1156 | unsigned int irq_mask = 1 << get_gpio_index(gpio); |
1157 | ||
1158 | /* For level-triggered GPIOs, the clearing must be done after | |
1159 | * the HW source is cleared, thus after the handler has run */ | |
1160 | if (bank->level_mask & irq_mask) { | |
1161 | _set_gpio_irqenable(bank, gpio, 0); | |
1162 | _clear_gpio_irqstatus(bank, gpio); | |
1163 | } | |
5e1c5ff4 | 1164 | |
4de8c75b | 1165 | _set_gpio_irqenable(bank, gpio, 1); |
5e1c5ff4 TL |
1166 | } |
1167 | ||
e5c56ed3 DB |
1168 | static struct irq_chip gpio_irq_chip = { |
1169 | .name = "GPIO", | |
1170 | .shutdown = gpio_irq_shutdown, | |
1171 | .ack = gpio_ack_irq, | |
1172 | .mask = gpio_mask_irq, | |
1173 | .unmask = gpio_unmask_irq, | |
1174 | .set_type = gpio_irq_type, | |
1175 | .set_wake = gpio_wake_enable, | |
1176 | }; | |
1177 | ||
1178 | /*---------------------------------------------------------------------*/ | |
1179 | ||
1180 | #ifdef CONFIG_ARCH_OMAP1 | |
1181 | ||
1182 | /* MPUIO uses the always-on 32k clock */ | |
1183 | ||
5e1c5ff4 TL |
1184 | static void mpuio_ack_irq(unsigned int irq) |
1185 | { | |
1186 | /* The ISR is reset automatically, so do nothing here. */ | |
1187 | } | |
1188 | ||
1189 | static void mpuio_mask_irq(unsigned int irq) | |
1190 | { | |
1191 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1192 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1193 | |
1194 | _set_gpio_irqenable(bank, gpio, 0); | |
1195 | } | |
1196 | ||
1197 | static void mpuio_unmask_irq(unsigned int irq) | |
1198 | { | |
1199 | unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE); | |
58781016 | 1200 | struct gpio_bank *bank = get_irq_chip_data(irq); |
5e1c5ff4 TL |
1201 | |
1202 | _set_gpio_irqenable(bank, gpio, 1); | |
1203 | } | |
1204 | ||
e5c56ed3 DB |
1205 | static struct irq_chip mpuio_irq_chip = { |
1206 | .name = "MPUIO", | |
1207 | .ack = mpuio_ack_irq, | |
1208 | .mask = mpuio_mask_irq, | |
1209 | .unmask = mpuio_unmask_irq, | |
92105bb7 | 1210 | .set_type = gpio_irq_type, |
11a78b79 DB |
1211 | #ifdef CONFIG_ARCH_OMAP16XX |
1212 | /* REVISIT: assuming only 16xx supports MPUIO wake events */ | |
1213 | .set_wake = gpio_wake_enable, | |
1214 | #endif | |
5e1c5ff4 TL |
1215 | }; |
1216 | ||
e5c56ed3 DB |
1217 | |
1218 | #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) | |
1219 | ||
11a78b79 DB |
1220 | |
1221 | #ifdef CONFIG_ARCH_OMAP16XX | |
1222 | ||
1223 | #include <linux/platform_device.h> | |
1224 | ||
1225 | static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg) | |
1226 | { | |
1227 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1228 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
a6472533 | 1229 | unsigned long flags; |
11a78b79 | 1230 | |
a6472533 | 1231 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 DB |
1232 | bank->saved_wakeup = __raw_readl(mask_reg); |
1233 | __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); | |
a6472533 | 1234 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1235 | |
1236 | return 0; | |
1237 | } | |
1238 | ||
1239 | static int omap_mpuio_resume_early(struct platform_device *pdev) | |
1240 | { | |
1241 | struct gpio_bank *bank = platform_get_drvdata(pdev); | |
1242 | void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT; | |
a6472533 | 1243 | unsigned long flags; |
11a78b79 | 1244 | |
a6472533 | 1245 | spin_lock_irqsave(&bank->lock, flags); |
11a78b79 | 1246 | __raw_writel(bank->saved_wakeup, mask_reg); |
a6472533 | 1247 | spin_unlock_irqrestore(&bank->lock, flags); |
11a78b79 DB |
1248 | |
1249 | return 0; | |
1250 | } | |
1251 | ||
1252 | /* use platform_driver for this, now that there's no longer any | |
1253 | * point to sys_device (other than not disturbing old code). | |
1254 | */ | |
1255 | static struct platform_driver omap_mpuio_driver = { | |
1256 | .suspend_late = omap_mpuio_suspend_late, | |
1257 | .resume_early = omap_mpuio_resume_early, | |
1258 | .driver = { | |
1259 | .name = "mpuio", | |
1260 | }, | |
1261 | }; | |
1262 | ||
1263 | static struct platform_device omap_mpuio_device = { | |
1264 | .name = "mpuio", | |
1265 | .id = -1, | |
1266 | .dev = { | |
1267 | .driver = &omap_mpuio_driver.driver, | |
1268 | } | |
1269 | /* could list the /proc/iomem resources */ | |
1270 | }; | |
1271 | ||
1272 | static inline void mpuio_init(void) | |
1273 | { | |
fcf126d8 DB |
1274 | platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]); |
1275 | ||
11a78b79 DB |
1276 | if (platform_driver_register(&omap_mpuio_driver) == 0) |
1277 | (void) platform_device_register(&omap_mpuio_device); | |
1278 | } | |
1279 | ||
1280 | #else | |
1281 | static inline void mpuio_init(void) {} | |
1282 | #endif /* 16xx */ | |
1283 | ||
e5c56ed3 DB |
1284 | #else |
1285 | ||
1286 | extern struct irq_chip mpuio_irq_chip; | |
1287 | ||
1288 | #define bank_is_mpuio(bank) 0 | |
11a78b79 | 1289 | static inline void mpuio_init(void) {} |
e5c56ed3 DB |
1290 | |
1291 | #endif | |
1292 | ||
1293 | /*---------------------------------------------------------------------*/ | |
5e1c5ff4 | 1294 | |
52e31344 DB |
1295 | /* REVISIT these are stupid implementations! replace by ones that |
1296 | * don't switch on METHOD_* and which mostly avoid spinlocks | |
1297 | */ | |
1298 | ||
1299 | static int gpio_input(struct gpio_chip *chip, unsigned offset) | |
1300 | { | |
1301 | struct gpio_bank *bank; | |
1302 | unsigned long flags; | |
1303 | ||
1304 | bank = container_of(chip, struct gpio_bank, chip); | |
1305 | spin_lock_irqsave(&bank->lock, flags); | |
1306 | _set_gpio_direction(bank, offset, 1); | |
1307 | spin_unlock_irqrestore(&bank->lock, flags); | |
1308 | return 0; | |
1309 | } | |
1310 | ||
1311 | static int gpio_get(struct gpio_chip *chip, unsigned offset) | |
1312 | { | |
0b84b5ca | 1313 | return __omap_get_gpio_datain(chip->base + offset); |
52e31344 DB |
1314 | } |
1315 | ||
1316 | static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) | |
1317 | { | |
1318 | struct gpio_bank *bank; | |
1319 | unsigned long flags; | |
1320 | ||
1321 | bank = container_of(chip, struct gpio_bank, chip); | |
1322 | spin_lock_irqsave(&bank->lock, flags); | |
1323 | _set_gpio_dataout(bank, offset, value); | |
1324 | _set_gpio_direction(bank, offset, 0); | |
1325 | spin_unlock_irqrestore(&bank->lock, flags); | |
1326 | return 0; | |
1327 | } | |
1328 | ||
1329 | static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
1330 | { | |
1331 | struct gpio_bank *bank; | |
1332 | unsigned long flags; | |
1333 | ||
1334 | bank = container_of(chip, struct gpio_bank, chip); | |
1335 | spin_lock_irqsave(&bank->lock, flags); | |
1336 | _set_gpio_dataout(bank, offset, value); | |
1337 | spin_unlock_irqrestore(&bank->lock, flags); | |
1338 | } | |
1339 | ||
a007b709 DB |
1340 | static int gpio_2irq(struct gpio_chip *chip, unsigned offset) |
1341 | { | |
1342 | struct gpio_bank *bank; | |
1343 | ||
1344 | bank = container_of(chip, struct gpio_bank, chip); | |
1345 | return bank->virtual_irq_start + offset; | |
1346 | } | |
1347 | ||
52e31344 DB |
1348 | /*---------------------------------------------------------------------*/ |
1349 | ||
1a8bfa1e | 1350 | static int initialized; |
5492fb1a | 1351 | #if !defined(CONFIG_ARCH_OMAP3) |
1a8bfa1e | 1352 | static struct clk * gpio_ick; |
5492fb1a SMK |
1353 | #endif |
1354 | ||
1355 | #if defined(CONFIG_ARCH_OMAP2) | |
1a8bfa1e | 1356 | static struct clk * gpio_fck; |
5492fb1a | 1357 | #endif |
5e1c5ff4 | 1358 | |
5492fb1a | 1359 | #if defined(CONFIG_ARCH_OMAP2430) |
56a25641 SMK |
1360 | static struct clk * gpio5_ick; |
1361 | static struct clk * gpio5_fck; | |
1362 | #endif | |
1363 | ||
5492fb1a | 1364 | #if defined(CONFIG_ARCH_OMAP3) |
5492fb1a SMK |
1365 | static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS]; |
1366 | #endif | |
1367 | ||
8ba55c5c DB |
1368 | /* This lock class tells lockdep that GPIO irqs are in a different |
1369 | * category than their parents, so it won't report false recursion. | |
1370 | */ | |
1371 | static struct lock_class_key gpio_lock_class; | |
1372 | ||
5e1c5ff4 TL |
1373 | static int __init _omap_gpio_init(void) |
1374 | { | |
1375 | int i; | |
52e31344 | 1376 | int gpio = 0; |
5e1c5ff4 | 1377 | struct gpio_bank *bank; |
5492fb1a | 1378 | char clk_name[11]; |
5e1c5ff4 TL |
1379 | |
1380 | initialized = 1; | |
1381 | ||
5492fb1a | 1382 | #if defined(CONFIG_ARCH_OMAP1) |
6e60e79a | 1383 | if (cpu_is_omap15xx()) { |
1a8bfa1e TL |
1384 | gpio_ick = clk_get(NULL, "arm_gpio_ck"); |
1385 | if (IS_ERR(gpio_ick)) | |
92105bb7 TL |
1386 | printk("Could not get arm_gpio_ck\n"); |
1387 | else | |
30ff720b | 1388 | clk_enable(gpio_ick); |
1a8bfa1e | 1389 | } |
5492fb1a SMK |
1390 | #endif |
1391 | #if defined(CONFIG_ARCH_OMAP2) | |
1392 | if (cpu_class_is_omap2()) { | |
1a8bfa1e TL |
1393 | gpio_ick = clk_get(NULL, "gpios_ick"); |
1394 | if (IS_ERR(gpio_ick)) | |
1395 | printk("Could not get gpios_ick\n"); | |
1396 | else | |
30ff720b | 1397 | clk_enable(gpio_ick); |
1a8bfa1e | 1398 | gpio_fck = clk_get(NULL, "gpios_fck"); |
1630b52d | 1399 | if (IS_ERR(gpio_fck)) |
1a8bfa1e TL |
1400 | printk("Could not get gpios_fck\n"); |
1401 | else | |
30ff720b | 1402 | clk_enable(gpio_fck); |
56a25641 SMK |
1403 | |
1404 | /* | |
5492fb1a | 1405 | * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK |
56a25641 | 1406 | */ |
5492fb1a | 1407 | #if defined(CONFIG_ARCH_OMAP2430) |
56a25641 SMK |
1408 | if (cpu_is_omap2430()) { |
1409 | gpio5_ick = clk_get(NULL, "gpio5_ick"); | |
1410 | if (IS_ERR(gpio5_ick)) | |
1411 | printk("Could not get gpio5_ick\n"); | |
1412 | else | |
1413 | clk_enable(gpio5_ick); | |
1414 | gpio5_fck = clk_get(NULL, "gpio5_fck"); | |
1415 | if (IS_ERR(gpio5_fck)) | |
1416 | printk("Could not get gpio5_fck\n"); | |
1417 | else | |
1418 | clk_enable(gpio5_fck); | |
1419 | } | |
1420 | #endif | |
5492fb1a SMK |
1421 | } |
1422 | #endif | |
1423 | ||
1424 | #if defined(CONFIG_ARCH_OMAP3) | |
1425 | if (cpu_is_omap34xx()) { | |
1426 | for (i = 0; i < OMAP34XX_NR_GPIOS; i++) { | |
1427 | sprintf(clk_name, "gpio%d_ick", i + 1); | |
1428 | gpio_iclks[i] = clk_get(NULL, clk_name); | |
1429 | if (IS_ERR(gpio_iclks[i])) | |
1430 | printk(KERN_ERR "Could not get %s\n", clk_name); | |
1431 | else | |
1432 | clk_enable(gpio_iclks[i]); | |
5492fb1a SMK |
1433 | } |
1434 | } | |
1435 | #endif | |
1436 | ||
92105bb7 | 1437 | |
1a8bfa1e | 1438 | #ifdef CONFIG_ARCH_OMAP15XX |
6e60e79a | 1439 | if (cpu_is_omap15xx()) { |
5e1c5ff4 TL |
1440 | printk(KERN_INFO "OMAP1510 GPIO hardware\n"); |
1441 | gpio_bank_count = 2; | |
1442 | gpio_bank = gpio_bank_1510; | |
1443 | } | |
1444 | #endif | |
1445 | #if defined(CONFIG_ARCH_OMAP16XX) | |
1446 | if (cpu_is_omap16xx()) { | |
92105bb7 | 1447 | u32 rev; |
5e1c5ff4 TL |
1448 | |
1449 | gpio_bank_count = 5; | |
1450 | gpio_bank = gpio_bank_1610; | |
7c7095aa | 1451 | rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION); |
5e1c5ff4 TL |
1452 | printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n", |
1453 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1454 | } | |
1455 | #endif | |
1456 | #ifdef CONFIG_ARCH_OMAP730 | |
1457 | if (cpu_is_omap730()) { | |
1458 | printk(KERN_INFO "OMAP730 GPIO hardware\n"); | |
1459 | gpio_bank_count = 7; | |
1460 | gpio_bank = gpio_bank_730; | |
1461 | } | |
92105bb7 | 1462 | #endif |
56739a69 ZM |
1463 | #ifdef CONFIG_ARCH_OMAP850 |
1464 | if (cpu_is_omap850()) { | |
1465 | printk(KERN_INFO "OMAP850 GPIO hardware\n"); | |
1466 | gpio_bank_count = 7; | |
1467 | gpio_bank = gpio_bank_850; | |
1468 | } | |
1469 | #endif | |
56a25641 | 1470 | |
92105bb7 | 1471 | #ifdef CONFIG_ARCH_OMAP24XX |
56a25641 | 1472 | if (cpu_is_omap242x()) { |
92105bb7 TL |
1473 | int rev; |
1474 | ||
1475 | gpio_bank_count = 4; | |
56a25641 | 1476 | gpio_bank = gpio_bank_242x; |
7c7095aa | 1477 | rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); |
56a25641 SMK |
1478 | printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n", |
1479 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1480 | } | |
1481 | if (cpu_is_omap243x()) { | |
1482 | int rev; | |
1483 | ||
1484 | gpio_bank_count = 5; | |
1485 | gpio_bank = gpio_bank_243x; | |
7c7095aa | 1486 | rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); |
56a25641 | 1487 | printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n", |
92105bb7 TL |
1488 | (rev >> 4) & 0x0f, rev & 0x0f); |
1489 | } | |
5492fb1a SMK |
1490 | #endif |
1491 | #ifdef CONFIG_ARCH_OMAP34XX | |
1492 | if (cpu_is_omap34xx()) { | |
1493 | int rev; | |
1494 | ||
1495 | gpio_bank_count = OMAP34XX_NR_GPIOS; | |
1496 | gpio_bank = gpio_bank_34xx; | |
7c7095aa | 1497 | rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); |
5492fb1a SMK |
1498 | printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n", |
1499 | (rev >> 4) & 0x0f, rev & 0x0f); | |
1500 | } | |
5e1c5ff4 TL |
1501 | #endif |
1502 | for (i = 0; i < gpio_bank_count; i++) { | |
1503 | int j, gpio_count = 16; | |
1504 | ||
1505 | bank = &gpio_bank[i]; | |
5e1c5ff4 | 1506 | spin_lock_init(&bank->lock); |
e5c56ed3 | 1507 | if (bank_is_mpuio(bank)) |
7c7095aa | 1508 | __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT); |
d11ac979 | 1509 | if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { |
5e1c5ff4 TL |
1510 | __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK); |
1511 | __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS); | |
1512 | } | |
d11ac979 | 1513 | if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { |
5e1c5ff4 TL |
1514 | __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1); |
1515 | __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); | |
92105bb7 | 1516 | __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); |
5e1c5ff4 | 1517 | } |
56739a69 | 1518 | if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) { |
5e1c5ff4 TL |
1519 | __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); |
1520 | __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); | |
1521 | ||
1522 | gpio_count = 32; /* 730 has 32-bit GPIOs */ | |
1523 | } | |
d11ac979 | 1524 | |
5492fb1a | 1525 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 | 1526 | if (bank->method == METHOD_GPIO_24XX) { |
3ac4fa99 JY |
1527 | static const u32 non_wakeup_gpios[] = { |
1528 | 0xe203ffc0, 0x08700040 | |
1529 | }; | |
1530 | ||
92105bb7 TL |
1531 | __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1); |
1532 | __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1); | |
14f1c3bf JY |
1533 | __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG); |
1534 | ||
1535 | /* Initialize interface clock ungated, module enabled */ | |
1536 | __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); | |
3ac4fa99 JY |
1537 | if (i < ARRAY_SIZE(non_wakeup_gpios)) |
1538 | bank->non_wakeup_gpios = non_wakeup_gpios[i]; | |
92105bb7 TL |
1539 | gpio_count = 32; |
1540 | } | |
5e1c5ff4 | 1541 | #endif |
52e31344 DB |
1542 | |
1543 | /* REVISIT eventually switch from OMAP-specific gpio structs | |
1544 | * over to the generic ones | |
1545 | */ | |
3ff164e1 JN |
1546 | bank->chip.request = omap_gpio_request; |
1547 | bank->chip.free = omap_gpio_free; | |
52e31344 DB |
1548 | bank->chip.direction_input = gpio_input; |
1549 | bank->chip.get = gpio_get; | |
1550 | bank->chip.direction_output = gpio_output; | |
1551 | bank->chip.set = gpio_set; | |
a007b709 | 1552 | bank->chip.to_irq = gpio_2irq; |
52e31344 DB |
1553 | if (bank_is_mpuio(bank)) { |
1554 | bank->chip.label = "mpuio"; | |
69114a47 | 1555 | #ifdef CONFIG_ARCH_OMAP16XX |
d8f388d8 DB |
1556 | bank->chip.dev = &omap_mpuio_device.dev; |
1557 | #endif | |
52e31344 DB |
1558 | bank->chip.base = OMAP_MPUIO(0); |
1559 | } else { | |
1560 | bank->chip.label = "gpio"; | |
1561 | bank->chip.base = gpio; | |
1562 | gpio += gpio_count; | |
1563 | } | |
1564 | bank->chip.ngpio = gpio_count; | |
1565 | ||
1566 | gpiochip_add(&bank->chip); | |
1567 | ||
5e1c5ff4 TL |
1568 | for (j = bank->virtual_irq_start; |
1569 | j < bank->virtual_irq_start + gpio_count; j++) { | |
8ba55c5c | 1570 | lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); |
58781016 | 1571 | set_irq_chip_data(j, bank); |
e5c56ed3 | 1572 | if (bank_is_mpuio(bank)) |
5e1c5ff4 TL |
1573 | set_irq_chip(j, &mpuio_irq_chip); |
1574 | else | |
1575 | set_irq_chip(j, &gpio_irq_chip); | |
10dd5ce2 | 1576 | set_irq_handler(j, handle_simple_irq); |
5e1c5ff4 TL |
1577 | set_irq_flags(j, IRQF_VALID); |
1578 | } | |
1579 | set_irq_chained_handler(bank->irq, gpio_irq_handler); | |
1580 | set_irq_data(bank->irq, bank); | |
89db9482 JH |
1581 | |
1582 | if (cpu_is_omap34xx()) { | |
1583 | sprintf(clk_name, "gpio%d_dbck", i + 1); | |
1584 | bank->dbck = clk_get(NULL, clk_name); | |
1585 | if (IS_ERR(bank->dbck)) | |
1586 | printk(KERN_ERR "Could not get %s\n", clk_name); | |
1587 | } | |
5e1c5ff4 TL |
1588 | } |
1589 | ||
1590 | /* Enable system clock for GPIO module. | |
1591 | * The CAM_CLK_CTRL *is* really the right place. */ | |
92105bb7 | 1592 | if (cpu_is_omap16xx()) |
5e1c5ff4 TL |
1593 | omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL); |
1594 | ||
14f1c3bf JY |
1595 | /* Enable autoidle for the OCP interface */ |
1596 | if (cpu_is_omap24xx()) | |
1597 | omap_writel(1 << 0, 0x48019010); | |
5492fb1a SMK |
1598 | if (cpu_is_omap34xx()) |
1599 | omap_writel(1 << 0, 0x48306814); | |
d11ac979 | 1600 | |
5e1c5ff4 TL |
1601 | return 0; |
1602 | } | |
1603 | ||
5492fb1a | 1604 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 TL |
1605 | static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg) |
1606 | { | |
1607 | int i; | |
1608 | ||
5492fb1a | 1609 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
1610 | return 0; |
1611 | ||
1612 | for (i = 0; i < gpio_bank_count; i++) { | |
1613 | struct gpio_bank *bank = &gpio_bank[i]; | |
1614 | void __iomem *wake_status; | |
1615 | void __iomem *wake_clear; | |
1616 | void __iomem *wake_set; | |
a6472533 | 1617 | unsigned long flags; |
92105bb7 TL |
1618 | |
1619 | switch (bank->method) { | |
e5c56ed3 | 1620 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1621 | case METHOD_GPIO_1610: |
1622 | wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; | |
1623 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1624 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1625 | break; | |
e5c56ed3 | 1626 | #endif |
5492fb1a | 1627 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 | 1628 | case METHOD_GPIO_24XX: |
723fdb78 | 1629 | wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; |
92105bb7 TL |
1630 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1631 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
1632 | break; | |
e5c56ed3 | 1633 | #endif |
92105bb7 TL |
1634 | default: |
1635 | continue; | |
1636 | } | |
1637 | ||
a6472533 | 1638 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1639 | bank->saved_wakeup = __raw_readl(wake_status); |
1640 | __raw_writel(0xffffffff, wake_clear); | |
1641 | __raw_writel(bank->suspend_wakeup, wake_set); | |
a6472533 | 1642 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
1643 | } |
1644 | ||
1645 | return 0; | |
1646 | } | |
1647 | ||
1648 | static int omap_gpio_resume(struct sys_device *dev) | |
1649 | { | |
1650 | int i; | |
1651 | ||
723fdb78 | 1652 | if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) |
92105bb7 TL |
1653 | return 0; |
1654 | ||
1655 | for (i = 0; i < gpio_bank_count; i++) { | |
1656 | struct gpio_bank *bank = &gpio_bank[i]; | |
1657 | void __iomem *wake_clear; | |
1658 | void __iomem *wake_set; | |
a6472533 | 1659 | unsigned long flags; |
92105bb7 TL |
1660 | |
1661 | switch (bank->method) { | |
e5c56ed3 | 1662 | #ifdef CONFIG_ARCH_OMAP16XX |
92105bb7 TL |
1663 | case METHOD_GPIO_1610: |
1664 | wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; | |
1665 | wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; | |
1666 | break; | |
e5c56ed3 | 1667 | #endif |
5492fb1a | 1668 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
92105bb7 | 1669 | case METHOD_GPIO_24XX: |
0d9356cb TL |
1670 | wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; |
1671 | wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; | |
92105bb7 | 1672 | break; |
e5c56ed3 | 1673 | #endif |
92105bb7 TL |
1674 | default: |
1675 | continue; | |
1676 | } | |
1677 | ||
a6472533 | 1678 | spin_lock_irqsave(&bank->lock, flags); |
92105bb7 TL |
1679 | __raw_writel(0xffffffff, wake_clear); |
1680 | __raw_writel(bank->saved_wakeup, wake_set); | |
a6472533 | 1681 | spin_unlock_irqrestore(&bank->lock, flags); |
92105bb7 TL |
1682 | } |
1683 | ||
1684 | return 0; | |
1685 | } | |
1686 | ||
1687 | static struct sysdev_class omap_gpio_sysclass = { | |
af5ca3f4 | 1688 | .name = "gpio", |
92105bb7 TL |
1689 | .suspend = omap_gpio_suspend, |
1690 | .resume = omap_gpio_resume, | |
1691 | }; | |
1692 | ||
1693 | static struct sys_device omap_gpio_device = { | |
1694 | .id = 0, | |
1695 | .cls = &omap_gpio_sysclass, | |
1696 | }; | |
3ac4fa99 JY |
1697 | |
1698 | #endif | |
1699 | ||
5492fb1a | 1700 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1701 | |
1702 | static int workaround_enabled; | |
1703 | ||
1704 | void omap2_gpio_prepare_for_retention(void) | |
1705 | { | |
1706 | int i, c = 0; | |
1707 | ||
1708 | /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious | |
1709 | * IRQs will be generated. See OMAP2420 Errata item 1.101. */ | |
1710 | for (i = 0; i < gpio_bank_count; i++) { | |
1711 | struct gpio_bank *bank = &gpio_bank[i]; | |
1712 | u32 l1, l2; | |
1713 | ||
1714 | if (!(bank->enabled_non_wakeup_gpios)) | |
1715 | continue; | |
5492fb1a | 1716 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1717 | bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
1718 | l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1719 | l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
5492fb1a | 1720 | #endif |
3ac4fa99 JY |
1721 | bank->saved_fallingdetect = l1; |
1722 | bank->saved_risingdetect = l2; | |
1723 | l1 &= ~bank->enabled_non_wakeup_gpios; | |
1724 | l2 &= ~bank->enabled_non_wakeup_gpios; | |
5492fb1a | 1725 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1726 | __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT); |
1727 | __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
5492fb1a | 1728 | #endif |
3ac4fa99 JY |
1729 | c++; |
1730 | } | |
1731 | if (!c) { | |
1732 | workaround_enabled = 0; | |
1733 | return; | |
1734 | } | |
1735 | workaround_enabled = 1; | |
1736 | } | |
1737 | ||
1738 | void omap2_gpio_resume_after_retention(void) | |
1739 | { | |
1740 | int i; | |
1741 | ||
1742 | if (!workaround_enabled) | |
1743 | return; | |
1744 | for (i = 0; i < gpio_bank_count; i++) { | |
1745 | struct gpio_bank *bank = &gpio_bank[i]; | |
1746 | u32 l; | |
1747 | ||
1748 | if (!(bank->enabled_non_wakeup_gpios)) | |
1749 | continue; | |
5492fb1a | 1750 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1751 | __raw_writel(bank->saved_fallingdetect, |
1752 | bank->base + OMAP24XX_GPIO_FALLINGDETECT); | |
1753 | __raw_writel(bank->saved_risingdetect, | |
1754 | bank->base + OMAP24XX_GPIO_RISINGDETECT); | |
5492fb1a | 1755 | #endif |
3ac4fa99 JY |
1756 | /* Check if any of the non-wakeup interrupt GPIOs have changed |
1757 | * state. If so, generate an IRQ by software. This is | |
1758 | * horribly racy, but it's the best we can do to work around | |
1759 | * this silicon bug. */ | |
5492fb1a | 1760 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 | 1761 | l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); |
5492fb1a | 1762 | #endif |
3ac4fa99 JY |
1763 | l ^= bank->saved_datain; |
1764 | l &= bank->non_wakeup_gpios; | |
1765 | if (l) { | |
1766 | u32 old0, old1; | |
5492fb1a | 1767 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
3ac4fa99 JY |
1768 | old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); |
1769 | old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
1770 | __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
1771 | __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
1772 | __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0); | |
1773 | __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1); | |
5492fb1a | 1774 | #endif |
3ac4fa99 JY |
1775 | } |
1776 | } | |
1777 | ||
1778 | } | |
1779 | ||
92105bb7 TL |
1780 | #endif |
1781 | ||
5e1c5ff4 TL |
1782 | /* |
1783 | * This may get called early from board specific init | |
1a8bfa1e | 1784 | * for boards that have interrupts routed via FPGA. |
5e1c5ff4 | 1785 | */ |
277d58ef | 1786 | int __init omap_gpio_init(void) |
5e1c5ff4 TL |
1787 | { |
1788 | if (!initialized) | |
1789 | return _omap_gpio_init(); | |
1790 | else | |
1791 | return 0; | |
1792 | } | |
1793 | ||
92105bb7 TL |
1794 | static int __init omap_gpio_sysinit(void) |
1795 | { | |
1796 | int ret = 0; | |
1797 | ||
1798 | if (!initialized) | |
1799 | ret = _omap_gpio_init(); | |
1800 | ||
11a78b79 DB |
1801 | mpuio_init(); |
1802 | ||
5492fb1a SMK |
1803 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
1804 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) { | |
92105bb7 TL |
1805 | if (ret == 0) { |
1806 | ret = sysdev_class_register(&omap_gpio_sysclass); | |
1807 | if (ret == 0) | |
1808 | ret = sysdev_register(&omap_gpio_device); | |
1809 | } | |
1810 | } | |
1811 | #endif | |
1812 | ||
1813 | return ret; | |
1814 | } | |
1815 | ||
92105bb7 | 1816 | arch_initcall(omap_gpio_sysinit); |
b9772a22 DB |
1817 | |
1818 | ||
1819 | #ifdef CONFIG_DEBUG_FS | |
1820 | ||
1821 | #include <linux/debugfs.h> | |
1822 | #include <linux/seq_file.h> | |
1823 | ||
1824 | static int gpio_is_input(struct gpio_bank *bank, int mask) | |
1825 | { | |
1826 | void __iomem *reg = bank->base; | |
1827 | ||
1828 | switch (bank->method) { | |
1829 | case METHOD_MPUIO: | |
1830 | reg += OMAP_MPUIO_IO_CNTL; | |
1831 | break; | |
1832 | case METHOD_GPIO_1510: | |
1833 | reg += OMAP1510_GPIO_DIR_CONTROL; | |
1834 | break; | |
1835 | case METHOD_GPIO_1610: | |
1836 | reg += OMAP1610_GPIO_DIRECTION; | |
1837 | break; | |
1838 | case METHOD_GPIO_730: | |
1839 | reg += OMAP730_GPIO_DIR_CONTROL; | |
1840 | break; | |
56739a69 ZM |
1841 | case METHOD_GPIO_850: |
1842 | reg += OMAP850_GPIO_DIR_CONTROL; | |
1843 | break; | |
b9772a22 DB |
1844 | case METHOD_GPIO_24XX: |
1845 | reg += OMAP24XX_GPIO_OE; | |
1846 | break; | |
1847 | } | |
1848 | return __raw_readl(reg) & mask; | |
1849 | } | |
1850 | ||
1851 | ||
1852 | static int dbg_gpio_show(struct seq_file *s, void *unused) | |
1853 | { | |
1854 | unsigned i, j, gpio; | |
1855 | ||
1856 | for (i = 0, gpio = 0; i < gpio_bank_count; i++) { | |
1857 | struct gpio_bank *bank = gpio_bank + i; | |
1858 | unsigned bankwidth = 16; | |
1859 | u32 mask = 1; | |
1860 | ||
e5c56ed3 | 1861 | if (bank_is_mpuio(bank)) |
b9772a22 | 1862 | gpio = OMAP_MPUIO(0); |
56739a69 ZM |
1863 | else if (cpu_class_is_omap2() || cpu_is_omap730() || |
1864 | cpu_is_omap850()) | |
b9772a22 DB |
1865 | bankwidth = 32; |
1866 | ||
1867 | for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { | |
1868 | unsigned irq, value, is_in, irqstat; | |
52e31344 | 1869 | const char *label; |
b9772a22 | 1870 | |
52e31344 DB |
1871 | label = gpiochip_is_requested(&bank->chip, j); |
1872 | if (!label) | |
b9772a22 DB |
1873 | continue; |
1874 | ||
1875 | irq = bank->virtual_irq_start + j; | |
0b84b5ca | 1876 | value = gpio_get_value(gpio); |
b9772a22 DB |
1877 | is_in = gpio_is_input(bank, mask); |
1878 | ||
e5c56ed3 | 1879 | if (bank_is_mpuio(bank)) |
52e31344 | 1880 | seq_printf(s, "MPUIO %2d ", j); |
b9772a22 | 1881 | else |
52e31344 | 1882 | seq_printf(s, "GPIO %3d ", gpio); |
21c867f1 | 1883 | seq_printf(s, "(%-20.20s): %s %s", |
52e31344 | 1884 | label, |
b9772a22 DB |
1885 | is_in ? "in " : "out", |
1886 | value ? "hi" : "lo"); | |
1887 | ||
52e31344 DB |
1888 | /* FIXME for at least omap2, show pullup/pulldown state */ |
1889 | ||
b9772a22 | 1890 | irqstat = irq_desc[irq].status; |
3a26e331 TL |
1891 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \ |
1892 | defined(CONFIG_ARCH_OMAP34XX) | |
b9772a22 DB |
1893 | if (is_in && ((bank->suspend_wakeup & mask) |
1894 | || irqstat & IRQ_TYPE_SENSE_MASK)) { | |
1895 | char *trigger = NULL; | |
1896 | ||
1897 | switch (irqstat & IRQ_TYPE_SENSE_MASK) { | |
1898 | case IRQ_TYPE_EDGE_FALLING: | |
1899 | trigger = "falling"; | |
1900 | break; | |
1901 | case IRQ_TYPE_EDGE_RISING: | |
1902 | trigger = "rising"; | |
1903 | break; | |
1904 | case IRQ_TYPE_EDGE_BOTH: | |
1905 | trigger = "bothedge"; | |
1906 | break; | |
1907 | case IRQ_TYPE_LEVEL_LOW: | |
1908 | trigger = "low"; | |
1909 | break; | |
1910 | case IRQ_TYPE_LEVEL_HIGH: | |
1911 | trigger = "high"; | |
1912 | break; | |
1913 | case IRQ_TYPE_NONE: | |
52e31344 | 1914 | trigger = "(?)"; |
b9772a22 DB |
1915 | break; |
1916 | } | |
52e31344 | 1917 | seq_printf(s, ", irq-%d %-8s%s", |
b9772a22 DB |
1918 | irq, trigger, |
1919 | (bank->suspend_wakeup & mask) | |
1920 | ? " wakeup" : ""); | |
1921 | } | |
3a26e331 | 1922 | #endif |
b9772a22 DB |
1923 | seq_printf(s, "\n"); |
1924 | } | |
1925 | ||
e5c56ed3 | 1926 | if (bank_is_mpuio(bank)) { |
b9772a22 DB |
1927 | seq_printf(s, "\n"); |
1928 | gpio = 0; | |
1929 | } | |
1930 | } | |
1931 | return 0; | |
1932 | } | |
1933 | ||
1934 | static int dbg_gpio_open(struct inode *inode, struct file *file) | |
1935 | { | |
e5c56ed3 | 1936 | return single_open(file, dbg_gpio_show, &inode->i_private); |
b9772a22 DB |
1937 | } |
1938 | ||
1939 | static const struct file_operations debug_fops = { | |
1940 | .open = dbg_gpio_open, | |
1941 | .read = seq_read, | |
1942 | .llseek = seq_lseek, | |
1943 | .release = single_release, | |
1944 | }; | |
1945 | ||
1946 | static int __init omap_gpio_debuginit(void) | |
1947 | { | |
e5c56ed3 DB |
1948 | (void) debugfs_create_file("omap_gpio", S_IRUGO, |
1949 | NULL, NULL, &debug_fops); | |
b9772a22 DB |
1950 | return 0; |
1951 | } | |
1952 | late_initcall(omap_gpio_debuginit); | |
1953 | #endif |