projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 4bbbc1ad JY |
1 | /* |
| 2 | * General-Purpose Memory Controller for OMAP2 | |
| 3 | * | |
| 4 | * Copyright (C) 2005-2006 Nokia Corporation | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License version 2 as | |
| 8 | * published by the Free Software Foundation. | |
| 9 | */ | |
| 10 | ||
| 11 | #ifndef __OMAP2_GPMC_H | |
| 12 | #define __OMAP2_GPMC_H | |
| 13 | ||
| fd1dc87d PW |
14 | /* Maximum Number of Chip Selects */ |
| 15 | #define GPMC_CS_NUM 8 | |
| 16 | ||
| 4bbbc1ad JY |
17 | #define GPMC_CS_CONFIG1 0x00 |
| 18 | #define GPMC_CS_CONFIG2 0x04 | |
| 19 | #define GPMC_CS_CONFIG3 0x08 | |
| 20 | #define GPMC_CS_CONFIG4 0x0c | |
| 21 | #define GPMC_CS_CONFIG5 0x10 | |
| 22 | #define GPMC_CS_CONFIG6 0x14 | |
| 23 | #define GPMC_CS_CONFIG7 0x18 | |
| 24 | #define GPMC_CS_NAND_COMMAND 0x1c | |
| 25 | #define GPMC_CS_NAND_ADDRESS 0x20 | |
| 26 | #define GPMC_CS_NAND_DATA 0x24 | |
| 27 | ||
| 28 | #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) | |
| 1c22cc13 | 29 | #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) |
| 4bbbc1ad JY |
30 | #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) |
| 31 | #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29) | |
| 1c22cc13 | 32 | #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28) |
| 4bbbc1ad JY |
33 | #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27) |
| 34 | #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27) | |
| 35 | #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25) | |
| 36 | #define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23) | |
| 37 | #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22) | |
| 38 | #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21) | |
| 39 | #define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18) | |
| 40 | #define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16) | |
| 41 | #define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12) | |
| 42 | #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) | |
| 43 | #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) | |
| 44 | #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) | |
| 45 | #define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(1) | |
| 46 | #define GPMC_CONFIG1_MUXADDDATA (1 << 9) | |
| 47 | #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) | |
| 48 | #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) | |
| 49 | #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) | |
| 50 | #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2)) | |
| 51 | #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) | |
| 52 | ||
| 53 | /* | |
| 54 | * Note that all values in this struct are in nanoseconds, while | |
| 55 | * the register values are in gpmc_fck cycles. | |
| 56 | */ | |
| 57 | struct gpmc_timings { | |
| 58 | /* Minimum clock period for synchronous mode */ | |
| 59 | u16 sync_clk; | |
| 60 | ||
| 61 | /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */ | |
| 62 | u16 cs_on; /* Assertion time */ | |
| 63 | u16 cs_rd_off; /* Read deassertion time */ | |
| 64 | u16 cs_wr_off; /* Write deassertion time */ | |
| 65 | ||
| 66 | /* ADV signal timings corresponding to GPMC_CONFIG3 */ | |
| 67 | u16 adv_on; /* Assertion time */ | |
| 68 | u16 adv_rd_off; /* Read deassertion time */ | |
| 69 | u16 adv_wr_off; /* Write deassertion time */ | |
| 70 | ||
| 71 | /* WE signals timings corresponding to GPMC_CONFIG4 */ | |
| 72 | u16 we_on; /* WE assertion time */ | |
| 73 | u16 we_off; /* WE deassertion time */ | |
| 74 | ||
| 75 | /* OE signals timings corresponding to GPMC_CONFIG4 */ | |
| 76 | u16 oe_on; /* OE assertion time */ | |
| 77 | u16 oe_off; /* OE deassertion time */ | |
| 78 | ||
| 79 | /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */ | |
| 80 | u16 page_burst_access; /* Multiple access word delay */ | |
| 81 | u16 access; /* Start-cycle to first data valid delay */ | |
| 82 | u16 rd_cycle; /* Total read cycle time */ | |
| 83 | u16 wr_cycle; /* Total write cycle time */ | |
| 84 | }; | |
| 85 | ||
| 86 | extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); | |
| fd1dc87d | 87 | extern unsigned int gpmc_ticks_to_ns(unsigned int ticks); |
| 23300597 KS |
88 | extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns); |
| 89 | extern unsigned long gpmc_get_fclk_period(void); | |
| 4bbbc1ad JY |
90 | |
| 91 | extern void gpmc_cs_write_reg(int cs, int idx, u32 val); | |
| 92 | extern u32 gpmc_cs_read_reg(int cs, int idx); | |
| 93 | extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk); | |
| 94 | extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t); | |
| f37e4580 ID |
95 | extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); |
| 96 | extern void gpmc_cs_free(int cs); | |
| 39b8e698 | 97 | extern int gpmc_cs_set_reserved(int cs, int reserved); |
| f4e4c324 | 98 | extern int gpmc_cs_reserved(int cs); |
| fd1dc87d | 99 | extern void gpmc_init(void); |
| 4bbbc1ad JY |
100 | |
| 101 | #endif |