[deliverable/linux.git] / arch / arm / plat-omap / include / mach / io.h

/*
 * arch/arm/plat-omap/include/mach/io.h
 *
 * IO definitions for TI OMAP processors and boards
 *
 * Copied from arch/arm/mach-sa1100/include/mach/io.h
 * Copyright (C) 1997-1999 Russell King
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * Modifications:
 *  06-12-1997	RMK	Created.
 *  07-04-1999	RMK	Major cleanup
 */

#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H

#include <mach/hardware.h>

#define IO_SPACE_LIMIT 0xffffffff

/*
 * We don't actually have real ISA nor PCI buses, but there is so many
 * drivers out there that might just work if we fake them...
 */
#define __io(a)		__typesafe_io(a)
#define __mem_pci(a)	(a)

/*
 * ----------------------------------------------------------------------------
 * I/O mapping
 * ----------------------------------------------------------------------------
 */

#if defined(CONFIG_ARCH_OMAP1)

#define IO_PHYS			0xFFFB0000
#define IO_OFFSET		0x01000000	/* Virtual IO = 0xfefb0000 */
#define IO_SIZE			0x40000
#define IO_VIRT			(IO_PHYS - IO_OFFSET)
#define __IO_ADDRESS(pa)	((pa) - IO_OFFSET)
#define __OMAP1_IO_ADDRESS(pa)	((pa) - IO_OFFSET)
#define io_v2p(va)		((va) + IO_OFFSET)

#elif defined(CONFIG_ARCH_OMAP2)

/* We map both L3 and L4 on OMAP2 */
#define L3_24XX_PHYS	L3_24XX_BASE	/* 0x68000000 */
#define L3_24XX_VIRT	0xf8000000
#define L3_24XX_SIZE	SZ_1M		/* 44kB of 128MB used, want 1MB sect */
#define L4_24XX_PHYS	L4_24XX_BASE	/* 0x48000000 */
#define L4_24XX_VIRT	0xd8000000
#define L4_24XX_SIZE	SZ_1M		/* 1MB of 128MB used, want 1MB sect */

#define L4_WK_243X_PHYS		L4_WK_243X_BASE		/* 0x49000000 */
#define L4_WK_243X_VIRT		0xd9000000
#define L4_WK_243X_SIZE		SZ_1M
#define OMAP243X_GPMC_PHYS	OMAP243X_GPMC_BASE	/* 0x49000000 */
#define OMAP243X_GPMC_VIRT	0xFE000000
#define OMAP243X_GPMC_SIZE	SZ_1M
#define OMAP243X_SDRC_PHYS	OMAP243X_SDRC_BASE
#define OMAP243X_SDRC_VIRT	0xFD000000
#define OMAP243X_SDRC_SIZE	SZ_1M
#define OMAP243X_SMS_PHYS	OMAP243X_SMS_BASE
#define OMAP243X_SMS_VIRT	0xFC000000
#define OMAP243X_SMS_SIZE	SZ_1M

#define IO_OFFSET		0x90000000
#define __IO_ADDRESS(pa)	((pa) + IO_OFFSET)	/* Works for L3 and L4 */
#define __OMAP2_IO_ADDRESS(pa)	((pa) + IO_OFFSET)	/* Works for L3 and L4 */
#define io_v2p(va)		((va) - IO_OFFSET)	/* Works for L3 and L4 */

/* DSP */
#define DSP_MEM_24XX_PHYS	OMAP2420_DSP_MEM_BASE	/* 0x58000000 */
#define DSP_MEM_24XX_VIRT	0xe0000000
#define DSP_MEM_24XX_SIZE	0x28000
#define DSP_IPI_24XX_PHYS	OMAP2420_DSP_IPI_BASE	/* 0x59000000 */
#define DSP_IPI_24XX_VIRT	0xe1000000
#define DSP_IPI_24XX_SIZE	SZ_4K
#define DSP_MMU_24XX_PHYS	OMAP2420_DSP_MMU_BASE	/* 0x5a000000 */
#define DSP_MMU_24XX_VIRT	0xe2000000
#define DSP_MMU_24XX_SIZE	SZ_4K

#elif defined(CONFIG_ARCH_OMAP3)

/* We map both L3 and L4 on OMAP3 */
#define L3_34XX_PHYS		L3_34XX_BASE	/* 0x68000000 */
#define L3_34XX_VIRT		0xf8000000
#define L3_34XX_SIZE		SZ_1M   /* 44kB of 128MB used, want 1MB sect */

#define L4_34XX_PHYS		L4_34XX_BASE	/* 0x48000000 */
#define L4_34XX_VIRT		0xd8000000
#define L4_34XX_SIZE		SZ_4M   /* 1MB of 128MB used, want 1MB sect */

/*
 * Need to look at the Size 4M for L4.
 * VPOM3430 was not working for Int controller
 */

#define L4_WK_34XX_PHYS		L4_WK_34XX_BASE /* 0x48300000 */
#define L4_WK_34XX_VIRT		0xd8300000
#define L4_WK_34XX_SIZE		SZ_1M

#define L4_PER_34XX_PHYS	L4_PER_34XX_BASE /* 0x49000000 */
#define L4_PER_34XX_VIRT	0xd9000000
#define L4_PER_34XX_SIZE	SZ_1M

#define L4_EMU_34XX_PHYS	L4_EMU_34XX_BASE /* 0x54000000 */
#define L4_EMU_34XX_VIRT	0xe4000000
#define L4_EMU_34XX_SIZE	SZ_64M

#define OMAP34XX_GPMC_PHYS	OMAP34XX_GPMC_BASE /* 0x6E000000 */
#define OMAP34XX_GPMC_VIRT	0xFE000000
#define OMAP34XX_GPMC_SIZE	SZ_1M

#define OMAP343X_SMS_PHYS	OMAP343X_SMS_BASE /* 0x6C000000 */
#define OMAP343X_SMS_VIRT	0xFC000000
#define OMAP343X_SMS_SIZE	SZ_1M

#define OMAP343X_SDRC_PHYS	OMAP343X_SDRC_BASE /* 0x6D000000 */
#define OMAP343X_SDRC_VIRT	0xFD000000
#define OMAP343X_SDRC_SIZE	SZ_1M


#define IO_OFFSET		0x90000000
#define __IO_ADDRESS(pa)	((pa) + IO_OFFSET)/* Works for L3 and L4 */
#define __OMAP2_IO_ADDRESS(pa)	((pa) + IO_OFFSET)/* Works for L3 and L4 */
#define io_v2p(va)		((va) - IO_OFFSET)/* Works for L3 and L4 */

/* DSP */
#define DSP_MEM_34XX_PHYS	OMAP34XX_DSP_MEM_BASE	/* 0x58000000 */
#define DSP_MEM_34XX_VIRT	0xe0000000
#define DSP_MEM_34XX_SIZE	0x28000
#define DSP_IPI_34XX_PHYS	OMAP34XX_DSP_IPI_BASE	/* 0x59000000 */
#define DSP_IPI_34XX_VIRT	0xe1000000
#define DSP_IPI_34XX_SIZE	SZ_4K
#define DSP_MMU_34XX_PHYS	OMAP34XX_DSP_MMU_BASE	/* 0x5a000000 */
#define DSP_MMU_34XX_VIRT	0xe2000000
#define DSP_MMU_34XX_SIZE	SZ_4K

#endif

#define IO_ADDRESS(pa)		IOMEM(__IO_ADDRESS(pa))
#define OMAP1_IO_ADDRESS(pa)	IOMEM(__OMAP1_IO_ADDRESS(pa))
#define OMAP2_IO_ADDRESS(pa)	IOMEM(__OMAP2_IO_ADDRESS(pa))

#ifdef __ASSEMBLER__
#define IOMEM(x)		x
#else
#define IOMEM(x)		((void __force __iomem *)(x))

/*
 * Functions to access the OMAP IO region
 *
 * NOTE: - Use omap_read/write[bwl] for physical register addresses
 *	 - Use __raw_read/write[bwl]() for virtual register addresses
 *	 - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses
 *	 - DO NOT use hardcoded virtual addresses to allow changing the
 *	   IO address space again if needed
 */
#define omap_readb(a)		__raw_readb(IO_ADDRESS(a))
#define omap_readw(a)		__raw_readw(IO_ADDRESS(a))
#define omap_readl(a)		__raw_readl(IO_ADDRESS(a))

#define omap_writeb(v,a)	__raw_writeb(v, IO_ADDRESS(a))
#define omap_writew(v,a)	__raw_writew(v, IO_ADDRESS(a))
#define omap_writel(v,a)	__raw_writel(v, IO_ADDRESS(a))

extern void omap1_map_common_io(void);
extern void omap1_init_common_hw(void);

extern void omap2_map_common_io(void);
extern void omap2_init_common_hw(void);

#define __arch_ioremap(p,s,t)	omap_ioremap(p,s,t)
#define __arch_iounmap(v)	omap_iounmap(v)

void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
void omap_iounmap(volatile void __iomem *addr);

#endif

#endif
Commit	Line	Data
1da177e4	1	/*
a09e64fb	2	* arch/arm/plat-omap/include/mach/io.h
1da177e4 LT	3	*
	4	* IO definitions for TI OMAP processors and boards
	5	*
a09e64fb	6	* Copied from arch/arm/mach-sa1100/include/mach/io.h
1da177e4 LT	7	* Copyright (C) 1997-1999 Russell King
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License as published by the
	11	* Free Software Foundation; either version 2 of the License, or (at your
	12	* option) any later version.
	13	*
	14	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
	15	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	16	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	17	* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	18	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	19	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	20	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	21	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	22	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	23	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	24	*
	25	* You should have received a copy of the GNU General Public License along
	26	* with this program; if not, write to the Free Software Foundation, Inc.,
	27	* 675 Mass Ave, Cambridge, MA 02139, USA.
	28	*
	29	* Modifications:
	30	* 06-12-1997 RMK Created.
	31	* 07-04-1999 RMK Major cleanup
	32	*/
	33
	34	#ifndef __ASM_ARM_ARCH_IO_H
	35	#define __ASM_ARM_ARCH_IO_H
	36
a09e64fb	37	#include <mach/hardware.h>
7fca0aa4	38
1da177e4 LT	39	#define IO_SPACE_LIMIT 0xffffffff
	40
	41	/*
	42	* We don't actually have real ISA nor PCI buses, but there is so many
	43	* drivers out there that might just work if we fake them...
	44	*/
0560cf5a RK	45	#define __io(a) __typesafe_io(a)
0560cf5a RK	46	#define __mem_pci(a) (a)
1da177e4 LT	47
	48	/*
	49	* ----------------------------------------------------------------------------
	50	* I/O mapping
	51	* ----------------------------------------------------------------------------
	52	*/
1da177e4	53
9839c6b8	54	#if defined(CONFIG_ARCH_OMAP1)
9ad5897c	55
e8a91c95 RK	56	#define IO_PHYS 0xFFFB0000
	57	#define IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
	58	#define IO_SIZE 0x40000
	59	#define IO_VIRT (IO_PHYS - IO_OFFSET)
	60	#define __IO_ADDRESS(pa) ((pa) - IO_OFFSET)
	61	#define __OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET)
	62	#define io_v2p(va) ((va) + IO_OFFSET)
1da177e4	63
9839c6b8	64	#elif defined(CONFIG_ARCH_OMAP2)
9839c6b8	65
9ad5897c TL	66	/* We map both L3 and L4 on OMAP2 */
	67	#define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 */
	68	#define L3_24XX_VIRT 0xf8000000
	69	#define L3_24XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
	70	#define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 */
	71	#define L4_24XX_VIRT 0xd8000000
	72	#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
72d0f1c3	73
72d0f1c3 SMK	74	#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */
	75	#define L4_WK_243X_VIRT 0xd9000000
	76	#define L4_WK_243X_SIZE SZ_1M
	77	#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE /* 0x49000000 */
	78	#define OMAP243X_GPMC_VIRT 0xFE000000
	79	#define OMAP243X_GPMC_SIZE SZ_1M
44595982 PW	80	#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
	81	#define OMAP243X_SDRC_VIRT 0xFD000000
	82	#define OMAP243X_SDRC_SIZE SZ_1M
	83	#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
	84	#define OMAP243X_SMS_VIRT 0xFC000000
	85	#define OMAP243X_SMS_SIZE SZ_1M
	86
e8a91c95 RK	87	#define IO_OFFSET 0x90000000
	88	#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
	89	#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
	90	#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
9ad5897c	91
f4e4c324	92	/* DSP */
44595982	93	#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */
f4e4c324 TL	94	#define DSP_MEM_24XX_VIRT 0xe0000000
f4e4c324 TL	95	#define DSP_MEM_24XX_SIZE 0x28000
44595982	96	#define DSP_IPI_24XX_PHYS OMAP2420_DSP_IPI_BASE /* 0x59000000 */
f4e4c324 TL	97	#define DSP_IPI_24XX_VIRT 0xe1000000
f4e4c324 TL	98	#define DSP_IPI_24XX_SIZE SZ_4K
44595982	99	#define DSP_MMU_24XX_PHYS OMAP2420_DSP_MMU_BASE /* 0x5a000000 */
f4e4c324 TL	100	#define DSP_MMU_24XX_VIRT 0xe2000000
	101	#define DSP_MMU_24XX_SIZE SZ_4K
	102
44595982 PW	103	#elif defined(CONFIG_ARCH_OMAP3)
	104
	105	/* We map both L3 and L4 on OMAP3 */
	106	#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 */
	107	#define L3_34XX_VIRT 0xf8000000
	108	#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
	109
	110	#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 */
	111	#define L4_34XX_VIRT 0xd8000000
	112	#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
	113
	114	/*
	115	* Need to look at the Size 4M for L4.
	116	* VPOM3430 was not working for Int controller
	117	*/
	118
	119	#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 */
	120	#define L4_WK_34XX_VIRT 0xd8300000
	121	#define L4_WK_34XX_SIZE SZ_1M
	122
	123	#define L4_PER_34XX_PHYS L4_PER_34XX_BASE /* 0x49000000 */
	124	#define L4_PER_34XX_VIRT 0xd9000000
	125	#define L4_PER_34XX_SIZE SZ_1M
	126
	127	#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE /* 0x54000000 */
	128	#define L4_EMU_34XX_VIRT 0xe4000000
	129	#define L4_EMU_34XX_SIZE SZ_64M
	130
	131	#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE /* 0x6E000000 */
	132	#define OMAP34XX_GPMC_VIRT 0xFE000000
	133	#define OMAP34XX_GPMC_SIZE SZ_1M
	134
	135	#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE /* 0x6C000000 */
	136	#define OMAP343X_SMS_VIRT 0xFC000000
	137	#define OMAP343X_SMS_SIZE SZ_1M
	138
	139	#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE /* 0x6D000000 */
	140	#define OMAP343X_SDRC_VIRT 0xFD000000
	141	#define OMAP343X_SDRC_SIZE SZ_1M
	142
	143
	144	#define IO_OFFSET 0x90000000
e8a91c95 RK	145	#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
e8a91c95 RK	146	#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
44595982 PW	147	#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */
	148
	149	/* DSP */
	150	#define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */
	151	#define DSP_MEM_34XX_VIRT 0xe0000000
	152	#define DSP_MEM_34XX_SIZE 0x28000
	153	#define DSP_IPI_34XX_PHYS OMAP34XX_DSP_IPI_BASE /* 0x59000000 */
	154	#define DSP_IPI_34XX_VIRT 0xe1000000
	155	#define DSP_IPI_34XX_SIZE SZ_4K
	156	#define DSP_MMU_34XX_PHYS OMAP34XX_DSP_MMU_BASE /* 0x5a000000 */
	157	#define DSP_MMU_34XX_VIRT 0xe2000000
	158	#define DSP_MMU_34XX_SIZE SZ_4K
	159
9ad5897c	160	#endif
1da177e4	161
e8a91c95 RK	162	#define IO_ADDRESS(pa) IOMEM(__IO_ADDRESS(pa))
	163	#define OMAP1_IO_ADDRESS(pa) IOMEM(__OMAP1_IO_ADDRESS(pa))
	164	#define OMAP2_IO_ADDRESS(pa) IOMEM(__OMAP2_IO_ADDRESS(pa))
	165
	166	#ifdef __ASSEMBLER__
	167	#define IOMEM(x) x
	168	#else
	169	#define IOMEM(x) ((void __force __iomem *)(x))
1da177e4 LT	170
	171	/*
	172	* Functions to access the OMAP IO region
	173	*
	174	* NOTE: - Use omap_read/write[bwl] for physical register addresses
	175	* - Use __raw_read/write[bwl]() for virtual register addresses
	176	* - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses
	177	* - DO NOT use hardcoded virtual addresses to allow changing the
	178	* IO address space again if needed
	179	*/
e8a91c95 RK	180	#define omap_readb(a) __raw_readb(IO_ADDRESS(a))
	181	#define omap_readw(a) __raw_readw(IO_ADDRESS(a))
	182	#define omap_readl(a) __raw_readl(IO_ADDRESS(a))
1da177e4	183
e8a91c95 RK	184	#define omap_writeb(v,a) __raw_writeb(v, IO_ADDRESS(a))
	185	#define omap_writew(v,a) __raw_writew(v, IO_ADDRESS(a))
	186	#define omap_writel(v,a) __raw_writel(v, IO_ADDRESS(a))
1da177e4	187
53d9cc73 TL	188	extern void omap1_map_common_io(void);
	189	extern void omap1_init_common_hw(void);
	190
	191	extern void omap2_map_common_io(void);
	192	extern void omap2_init_common_hw(void);
9839c6b8	193
690b5a13 RK	194	#define __arch_ioremap(p,s,t) omap_ioremap(p,s,t)
	195	#define __arch_iounmap(v) omap_iounmap(v)
	196
	197	void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
	198	void omap_iounmap(volatile void __iomem *addr);
	199
1da177e4 LT	200	#endif
	201
	202	#endif