[deliverable/linux.git] / arch / arm / plat-omap / include / mach / sdrc.h

#ifndef ____ASM_ARCH_SDRC_H
#define ____ASM_ARCH_SDRC_H

/*
 * OMAP2/3 SDRC/SMS register definitions
 *
 * Copyright (C) 2007-2008 Texas Instruments, Inc.
 * Copyright (C) 2007-2008 Nokia Corporation
 *
 * Tony Lindgren
 * Paul Walmsley
 * Richard Woodruff
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <mach/io.h>

/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */

#define SDRC_SYSCONFIG		0x010
#define SDRC_DLLA_CTRL		0x060
#define SDRC_DLLA_STATUS	0x064
#define SDRC_DLLB_CTRL		0x068
#define SDRC_DLLB_STATUS	0x06C
#define SDRC_POWER		0x070
#define SDRC_MR_0		0x084
#define SDRC_ACTIM_CTRL_A_0	0x09c
#define SDRC_ACTIM_CTRL_B_0	0x0a0
#define SDRC_RFR_CTRL_0		0x0a4

/*
 * These values represent the number of memory clock cycles between
 * autorefresh initiation.  They assume 1 refresh per 64 ms (JEDEC), 8192
 * rows per device, and include a subtraction of a 50 cycle window in the
 * event that the autorefresh command is delayed due to other SDRC activity.
 * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
 * counter reaches 0.
 *
 * These represent optimal values for common parts, it won't work for all.
 * As long as you scale down, most parameters are still work, they just
 * become sub-optimal. The RFR value goes in the opposite direction. If you
 * don't adjust it down as your clock period increases the refresh interval
 * will not be met. Setting all parameters for complete worst case may work,
 * but may cut memory performance by 2x. Due to errata the DLLs need to be
 * unlocked and their value needs run time calibration.	A dynamic call is
 * need for that as no single right value exists acorss production samples.
 *
 * Only the FULL speed values are given. Current code is such that rate
 * changes must be made at DPLLoutx2. The actual value adjustment for low
 * frequency operation will be handled by omap_set_performance()
 *
 * By having the boot loader boot up in the fastest L4 speed available likely
 * will result in something which you can switch between.
 */
#define SDRC_RFR_CTRL_165MHz	(0x00044c00 | 1)
#define SDRC_RFR_CTRL_133MHz	(0x0003de00 | 1)
#define SDRC_RFR_CTRL_100MHz	(0x0002da01 | 1)
#define SDRC_RFR_CTRL_110MHz	(0x0002da01 | 1) /* Need to calc */
#define SDRC_RFR_CTRL_BYPASS	(0x00005000 | 1) /* Need to calc */


/*
 * SMS register access
 */

#define OMAP242X_SMS_REGADDR(reg)					\
			(void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg)
#define OMAP243X_SMS_REGADDR(reg)					\
			(void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg)
#define OMAP343X_SMS_REGADDR(reg)					\
			(void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg)

/* SMS register offsets - read/write with sms_{read,write}_reg() */

#define SMS_SYSCONFIG		0x010
/* REVISIT: fill in other SMS registers here */


#ifndef __ASSEMBLER__

/**
 * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
 * @rate: SDRC clock rate (in Hz)
 * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
 * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
 * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
 * @mr: Value to program to SDRC_MR for this rate
 *
 * This structure holds a pre-computed set of register values for the
 * SDRC for a given SDRC clock rate and SDRAM chip.  These are
 * intended to be pre-computed and specified in an array in the board-*.c
 * files.  The structure is keyed off the 'rate' field.
 */
struct omap_sdrc_params {
	unsigned long rate;
	u32 actim_ctrla;
	u32 actim_ctrlb;
	u32 rfr_ctrl;
	u32 mr;
};

void __init omap2_sdrc_init(struct omap_sdrc_params *sp);
struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r);

#ifdef CONFIG_ARCH_OMAP2

struct memory_timings {
	u32 m_type;		/* ddr = 1, sdr = 0 */
	u32 dll_mode;		/* use lock mode = 1, unlock mode = 0 */
	u32 slow_dll_ctrl;	/* unlock mode, dll value for slow speed */
	u32 fast_dll_ctrl;	/* unlock mode, dll value for fast speed */
	u32 base_cs;		/* base chip select to use for calculations */
};

extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);

u32 omap2xxx_sdrc_dll_is_unlocked(void);
u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);

#endif  /* CONFIG_ARCH_OMAP2 */

#endif  /* __ASSEMBLER__ */

#endif
Commit	Line	Data
69d88a00 PW	1	#ifndef ____ASM_ARCH_SDRC_H
	2	#define ____ASM_ARCH_SDRC_H
	3
	4	/*
	5	* OMAP2/3 SDRC/SMS register definitions
	6	*
f2ab9977 PW	7	* Copyright (C) 2007-2008 Texas Instruments, Inc.
f2ab9977 PW	8	* Copyright (C) 2007-2008 Nokia Corporation
69d88a00	9	*
f2ab9977 PW	10	* Tony Lindgren
	11	* Paul Walmsley
	12	* Richard Woodruff
69d88a00 PW	13	*
	14	* This program is free software; you can redistribute it and/or modify
	15	* it under the terms of the GNU General Public License version 2 as
	16	* published by the Free Software Foundation.
	17	*/
	18
a09e64fb	19	#include <mach/io.h>
69d88a00 PW	20
	21	/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
	22
	23	#define SDRC_SYSCONFIG 0x010
	24	#define SDRC_DLLA_CTRL 0x060
	25	#define SDRC_DLLA_STATUS 0x064
	26	#define SDRC_DLLB_CTRL 0x068
	27	#define SDRC_DLLB_STATUS 0x06C
	28	#define SDRC_POWER 0x070
	29	#define SDRC_MR_0 0x084
cc26b3b0 SMK	30	#define SDRC_ACTIM_CTRL_A_0 0x09c
cc26b3b0 SMK	31	#define SDRC_ACTIM_CTRL_B_0 0x0a0
69d88a00 PW	32	#define SDRC_RFR_CTRL_0 0x0a4
	33
	34	/*
	35	* These values represent the number of memory clock cycles between
	36	* autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192
	37	* rows per device, and include a subtraction of a 50 cycle window in the
	38	* event that the autorefresh command is delayed due to other SDRC activity.
	39	* The '\| 1' sets the ARE field to send one autorefresh when the autorefresh
	40	* counter reaches 0.
	41	*
	42	* These represent optimal values for common parts, it won't work for all.
	43	* As long as you scale down, most parameters are still work, they just
	44	* become sub-optimal. The RFR value goes in the opposite direction. If you
	45	* don't adjust it down as your clock period increases the refresh interval
	46	* will not be met. Setting all parameters for complete worst case may work,
	47	* but may cut memory performance by 2x. Due to errata the DLLs need to be
	48	* unlocked and their value needs run time calibration. A dynamic call is
	49	* need for that as no single right value exists acorss production samples.
	50	*
	51	* Only the FULL speed values are given. Current code is such that rate
	52	* changes must be made at DPLLoutx2. The actual value adjustment for low
	53	* frequency operation will be handled by omap_set_performance()
	54	*
	55	* By having the boot loader boot up in the fastest L4 speed available likely
	56	* will result in something which you can switch between.
	57	*/
	58	#define SDRC_RFR_CTRL_165MHz (0x00044c00 \| 1)
	59	#define SDRC_RFR_CTRL_133MHz (0x0003de00 \| 1)
	60	#define SDRC_RFR_CTRL_100MHz (0x0002da01 \| 1)
	61	#define SDRC_RFR_CTRL_110MHz (0x0002da01 \| 1) /* Need to calc */
	62	#define SDRC_RFR_CTRL_BYPASS (0x00005000 \| 1) /* Need to calc */
	63
	64
	65	/*
	66	* SMS register access
	67	*/
	68
f2ab9977 PW	69	#define OMAP242X_SMS_REGADDR(reg) \
	70	(void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg)
	71	#define OMAP243X_SMS_REGADDR(reg) \
	72	(void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg)
	73	#define OMAP343X_SMS_REGADDR(reg) \
	74	(void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg)
69d88a00 PW	75
	76	/* SMS register offsets - read/write with sms_{read,write}_reg() */
	77
	78	#define SMS_SYSCONFIG 0x010
	79	/* REVISIT: fill in other SMS registers here */
	80
f2ab9977	81
f8de9b2c PW	82	#ifndef __ASSEMBLER__
f8de9b2c PW	83
87246b75 PW	84	/**
	85	* struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
	86	* @rate: SDRC clock rate (in Hz)
	87	* @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
	88	* @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
	89	* @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
	90	* @mr: Value to program to SDRC_MR for this rate
	91	*
	92	* This structure holds a pre-computed set of register values for the
	93	* SDRC for a given SDRC clock rate and SDRAM chip. These are
	94	* intended to be pre-computed and specified in an array in the board-*.c
	95	* files. The structure is keyed off the 'rate' field.
	96	*/
	97	struct omap_sdrc_params {
	98	unsigned long rate;
	99	u32 actim_ctrla;
	100	u32 actim_ctrlb;
	101	u32 rfr_ctrl;
	102	u32 mr;
	103	};
	104
	105	void __init omap2_sdrc_init(struct omap_sdrc_params *sp);
	106	struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r);
f2ab9977 PW	107
	108	#ifdef CONFIG_ARCH_OMAP2
	109
f8de9b2c PW	110	struct memory_timings {
	111	u32 m_type; /* ddr = 1, sdr = 0 */
	112	u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */
	113	u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */
	114	u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */
	115	u32 base_cs; /* base chip select to use for calculations */
	116	};
	117
f2ab9977	118	extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
f8de9b2c	119
f2ab9977 PW	120	u32 omap2xxx_sdrc_dll_is_unlocked(void);
	121	u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
	122
	123	#endif /* CONFIG_ARCH_OMAP2 */
f8de9b2c	124
f2ab9977	125	#endif /* __ASSEMBLER__ */
f8de9b2c	126
69d88a00	127	#endif