[deliverable/linux.git] / arch / arm / plat-omap / include / plat / gpio.h

/*
 * arch/arm/plat-omap/include/mach/gpio.h
 *
 * OMAP GPIO handling defines and functions
 *
 * Copyright (C) 2003-2005 Nokia Corporation
 *
 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 */

#ifndef __ASM_ARCH_OMAP_GPIO_H
#define __ASM_ARCH_OMAP_GPIO_H

#include <linux/io.h>
#include <linux/platform_device.h>
#include <mach/irqs.h>

#define OMAP1_MPUIO_BASE			0xfffb5000

/*
 * These are the omap15xx/16xx offsets. The omap7xx offset are
 * OMAP_MPUIO_ / 2 offsets below.
 */
#define OMAP_MPUIO_INPUT_LATCH		0x00
#define OMAP_MPUIO_OUTPUT		0x04
#define OMAP_MPUIO_IO_CNTL		0x08
#define OMAP_MPUIO_KBR_LATCH		0x10
#define OMAP_MPUIO_KBC			0x14
#define OMAP_MPUIO_GPIO_EVENT_MODE	0x18
#define OMAP_MPUIO_GPIO_INT_EDGE	0x1c
#define OMAP_MPUIO_KBD_INT		0x20
#define OMAP_MPUIO_GPIO_INT		0x24
#define OMAP_MPUIO_KBD_MASKIT		0x28
#define OMAP_MPUIO_GPIO_MASKIT		0x2c
#define OMAP_MPUIO_GPIO_DEBOUNCING	0x30
#define OMAP_MPUIO_LATCH		0x34

#define OMAP34XX_NR_GPIOS		6

/*
 * OMAP1510 GPIO registers
 */
#define OMAP1510_GPIO_DATA_INPUT	0x00
#define OMAP1510_GPIO_DATA_OUTPUT	0x04
#define OMAP1510_GPIO_DIR_CONTROL	0x08
#define OMAP1510_GPIO_INT_CONTROL	0x0c
#define OMAP1510_GPIO_INT_MASK		0x10
#define OMAP1510_GPIO_INT_STATUS	0x14
#define OMAP1510_GPIO_PIN_CONTROL	0x18

#define OMAP1510_IH_GPIO_BASE		64

/*
 * OMAP1610 specific GPIO registers
 */
#define OMAP1610_GPIO_REVISION		0x0000
#define OMAP1610_GPIO_SYSCONFIG		0x0010
#define OMAP1610_GPIO_SYSSTATUS		0x0014
#define OMAP1610_GPIO_IRQSTATUS1	0x0018
#define OMAP1610_GPIO_IRQENABLE1	0x001c
#define OMAP1610_GPIO_WAKEUPENABLE	0x0028
#define OMAP1610_GPIO_DATAIN		0x002c
#define OMAP1610_GPIO_DATAOUT		0x0030
#define OMAP1610_GPIO_DIRECTION		0x0034
#define OMAP1610_GPIO_EDGE_CTRL1	0x0038
#define OMAP1610_GPIO_EDGE_CTRL2	0x003c
#define OMAP1610_GPIO_CLEAR_IRQENABLE1	0x009c
#define OMAP1610_GPIO_CLEAR_WAKEUPENA	0x00a8
#define OMAP1610_GPIO_CLEAR_DATAOUT	0x00b0
#define OMAP1610_GPIO_SET_IRQENABLE1	0x00dc
#define OMAP1610_GPIO_SET_WAKEUPENA	0x00e8
#define OMAP1610_GPIO_SET_DATAOUT	0x00f0

/*
 * OMAP7XX specific GPIO registers
 */
#define OMAP7XX_GPIO_DATA_INPUT		0x00
#define OMAP7XX_GPIO_DATA_OUTPUT	0x04
#define OMAP7XX_GPIO_DIR_CONTROL	0x08
#define OMAP7XX_GPIO_INT_CONTROL	0x0c
#define OMAP7XX_GPIO_INT_MASK		0x10
#define OMAP7XX_GPIO_INT_STATUS		0x14

/*
 * omap2+ specific GPIO registers
 */
#define OMAP24XX_GPIO_REVISION		0x0000
#define OMAP24XX_GPIO_IRQSTATUS1	0x0018
#define OMAP24XX_GPIO_IRQSTATUS2	0x0028
#define OMAP24XX_GPIO_IRQENABLE2	0x002c
#define OMAP24XX_GPIO_IRQENABLE1	0x001c
#define OMAP24XX_GPIO_WAKE_EN		0x0020
#define OMAP24XX_GPIO_CTRL		0x0030
#define OMAP24XX_GPIO_OE		0x0034
#define OMAP24XX_GPIO_DATAIN		0x0038
#define OMAP24XX_GPIO_DATAOUT		0x003c
#define OMAP24XX_GPIO_LEVELDETECT0	0x0040
#define OMAP24XX_GPIO_LEVELDETECT1	0x0044
#define OMAP24XX_GPIO_RISINGDETECT	0x0048
#define OMAP24XX_GPIO_FALLINGDETECT	0x004c
#define OMAP24XX_GPIO_DEBOUNCE_EN	0x0050
#define OMAP24XX_GPIO_DEBOUNCE_VAL	0x0054
#define OMAP24XX_GPIO_CLEARIRQENABLE1	0x0060
#define OMAP24XX_GPIO_SETIRQENABLE1	0x0064
#define OMAP24XX_GPIO_CLEARWKUENA	0x0080
#define OMAP24XX_GPIO_SETWKUENA		0x0084
#define OMAP24XX_GPIO_CLEARDATAOUT	0x0090
#define OMAP24XX_GPIO_SETDATAOUT	0x0094

#define OMAP4_GPIO_REVISION		0x0000
#define OMAP4_GPIO_EOI			0x0020
#define OMAP4_GPIO_IRQSTATUSRAW0	0x0024
#define OMAP4_GPIO_IRQSTATUSRAW1	0x0028
#define OMAP4_GPIO_IRQSTATUS0		0x002c
#define OMAP4_GPIO_IRQSTATUS1		0x0030
#define OMAP4_GPIO_IRQSTATUSSET0	0x0034
#define OMAP4_GPIO_IRQSTATUSSET1	0x0038
#define OMAP4_GPIO_IRQSTATUSCLR0	0x003c
#define OMAP4_GPIO_IRQSTATUSCLR1	0x0040
#define OMAP4_GPIO_IRQWAKEN0		0x0044
#define OMAP4_GPIO_IRQWAKEN1		0x0048
#define OMAP4_GPIO_IRQENABLE1		0x011c
#define OMAP4_GPIO_WAKE_EN		0x0120
#define OMAP4_GPIO_IRQSTATUS2		0x0128
#define OMAP4_GPIO_IRQENABLE2		0x012c
#define OMAP4_GPIO_CTRL			0x0130
#define OMAP4_GPIO_OE			0x0134
#define OMAP4_GPIO_DATAIN		0x0138
#define OMAP4_GPIO_DATAOUT		0x013c
#define OMAP4_GPIO_LEVELDETECT0		0x0140
#define OMAP4_GPIO_LEVELDETECT1		0x0144
#define OMAP4_GPIO_RISINGDETECT		0x0148
#define OMAP4_GPIO_FALLINGDETECT	0x014c
#define OMAP4_GPIO_DEBOUNCENABLE	0x0150
#define OMAP4_GPIO_DEBOUNCINGTIME	0x0154
#define OMAP4_GPIO_CLEARIRQENABLE1	0x0160
#define OMAP4_GPIO_SETIRQENABLE1	0x0164
#define OMAP4_GPIO_CLEARWKUENA		0x0180
#define OMAP4_GPIO_SETWKUENA		0x0184
#define OMAP4_GPIO_CLEARDATAOUT		0x0190
#define OMAP4_GPIO_SETDATAOUT		0x0194

#define OMAP_MPUIO(nr)		(OMAP_MAX_GPIO_LINES + (nr))
#define OMAP_GPIO_IS_MPUIO(nr)	((nr) >= OMAP_MAX_GPIO_LINES)

struct omap_gpio_dev_attr {
	int bank_width;		/* GPIO bank width */
	bool dbck_flag;		/* dbck required or not - True for OMAP3&4 */
};

struct omap_gpio_reg_offs {
	u16 revision;
	u16 direction;
	u16 datain;
	u16 dataout;
	u16 set_dataout;
	u16 clr_dataout;
	u16 irqstatus;
	u16 irqstatus2;
	u16 irqstatus_raw0;
	u16 irqstatus_raw1;
	u16 irqenable;
	u16 irqenable2;
	u16 set_irqenable;
	u16 clr_irqenable;
	u16 debounce;
	u16 debounce_en;
	u16 ctrl;
	u16 wkup_en;
	u16 leveldetect0;
	u16 leveldetect1;
	u16 risingdetect;
	u16 fallingdetect;
	u16 irqctrl;
	u16 edgectrl1;
	u16 edgectrl2;
	u16 pinctrl;

	bool irqenable_inv;
};

struct omap_gpio_platform_data {
	int bank_type;
	int bank_width;		/* GPIO bank width */
	int bank_stride;	/* Only needed for omap1 MPUIO */
	bool dbck_flag;		/* dbck required or not - True for OMAP3&4 */
	bool loses_context;	/* whether the bank would ever lose context */
	bool is_mpuio;		/* whether the bank is of type MPUIO */
	u32 non_wakeup_gpios;

	struct omap_gpio_reg_offs *regs;

	/* Return context loss count due to PM states changing */
	int (*get_context_loss_count)(struct device *dev);
};

extern void omap2_gpio_prepare_for_idle(int off_mode);
extern void omap2_gpio_resume_after_idle(void);
extern void omap_set_gpio_debounce(int gpio, int enable);
extern void omap_set_gpio_debounce_time(int gpio, int enable);
/*-------------------------------------------------------------------------*/

/*
 * Wrappers for "new style" GPIO calls, using the new infrastructure
 * which lets us plug in FPGA, I2C, and other implementations.
 *
 * The original OMAP-specific calls should eventually be removed.
 */

#include <linux/errno.h>
#include <asm-generic/gpio.h>

#endif
Commit	Line	Data
1da177e4	1	/*
a09e64fb	2	* arch/arm/plat-omap/include/mach/gpio.h
1da177e4 LT	3	*
	4	* OMAP GPIO handling defines and functions
	5	*
9839c6b8	6	* Copyright (C) 2003-2005 Nokia Corporation
1da177e4	7	*
121e70b6	8	* Written by Juha Yrjölä <juha.yrjola@nokia.com>
1da177e4 LT	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	23	*
	24	*/
	25
	26	#ifndef __ASM_ARCH_OMAP_GPIO_H
	27	#define __ASM_ARCH_OMAP_GPIO_H
	28
fced80c7	29	#include <linux/io.h>
c95d10bc	30	#include <linux/platform_device.h>
a09e64fb	31	#include <mach/irqs.h>
1da177e4	32
6175556f	33	#define OMAP1_MPUIO_BASE 0xfffb5000
9839c6b8	34
5de62b86 TL	35	/*
	36	* These are the omap15xx/16xx offsets. The omap7xx offset are
	37	* OMAP_MPUIO_ / 2 offsets below.
	38	*/
1da177e4 LT	39	#define OMAP_MPUIO_INPUT_LATCH 0x00
	40	#define OMAP_MPUIO_OUTPUT 0x04
	41	#define OMAP_MPUIO_IO_CNTL 0x08
	42	#define OMAP_MPUIO_KBR_LATCH 0x10
	43	#define OMAP_MPUIO_KBC 0x14
	44	#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
	45	#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
	46	#define OMAP_MPUIO_KBD_INT 0x20
	47	#define OMAP_MPUIO_GPIO_INT 0x24
	48	#define OMAP_MPUIO_KBD_MASKIT 0x28
	49	#define OMAP_MPUIO_GPIO_MASKIT 0x2c
	50	#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
	51	#define OMAP_MPUIO_LATCH 0x34
	52
5492fb1a SMK	53	#define OMAP34XX_NR_GPIOS 6
5492fb1a SMK	54
5ee1a81b KH	55	/*
	56	* OMAP1510 GPIO registers
	57	*/
	58	#define OMAP1510_GPIO_DATA_INPUT 0x00
	59	#define OMAP1510_GPIO_DATA_OUTPUT 0x04
	60	#define OMAP1510_GPIO_DIR_CONTROL 0x08
	61	#define OMAP1510_GPIO_INT_CONTROL 0x0c
	62	#define OMAP1510_GPIO_INT_MASK 0x10
	63	#define OMAP1510_GPIO_INT_STATUS 0x14
	64	#define OMAP1510_GPIO_PIN_CONTROL 0x18
	65
	66	#define OMAP1510_IH_GPIO_BASE 64
	67
	68	/*
	69	* OMAP1610 specific GPIO registers
	70	*/
	71	#define OMAP1610_GPIO_REVISION 0x0000
	72	#define OMAP1610_GPIO_SYSCONFIG 0x0010
	73	#define OMAP1610_GPIO_SYSSTATUS 0x0014
	74	#define OMAP1610_GPIO_IRQSTATUS1 0x0018
	75	#define OMAP1610_GPIO_IRQENABLE1 0x001c
	76	#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
	77	#define OMAP1610_GPIO_DATAIN 0x002c
	78	#define OMAP1610_GPIO_DATAOUT 0x0030
	79	#define OMAP1610_GPIO_DIRECTION 0x0034
	80	#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
	81	#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
	82	#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
	83	#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
	84	#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
	85	#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
	86	#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
	87	#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
	88
	89	/*
	90	* OMAP7XX specific GPIO registers
	91	*/
	92	#define OMAP7XX_GPIO_DATA_INPUT 0x00
	93	#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
	94	#define OMAP7XX_GPIO_DIR_CONTROL 0x08
	95	#define OMAP7XX_GPIO_INT_CONTROL 0x0c
	96	#define OMAP7XX_GPIO_INT_MASK 0x10
	97	#define OMAP7XX_GPIO_INT_STATUS 0x14
	98
	99	/*
	100	* omap2+ specific GPIO registers
	101	*/
	102	#define OMAP24XX_GPIO_REVISION 0x0000
	103	#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
	104	#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
	105	#define OMAP24XX_GPIO_IRQENABLE2 0x002c
	106	#define OMAP24XX_GPIO_IRQENABLE1 0x001c
	107	#define OMAP24XX_GPIO_WAKE_EN 0x0020
	108	#define OMAP24XX_GPIO_CTRL 0x0030
	109	#define OMAP24XX_GPIO_OE 0x0034
	110	#define OMAP24XX_GPIO_DATAIN 0x0038
	111	#define OMAP24XX_GPIO_DATAOUT 0x003c
	112	#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
	113	#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
	114	#define OMAP24XX_GPIO_RISINGDETECT 0x0048
	115	#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
	116	#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
	117	#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
	118	#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
119	#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
120	#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
121	#define OMAP24XX_GPIO_SETWKUENA 0x0084
122	#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
123	#define OMAP24XX_GPIO_SETDATAOUT 0x0094
124
125	#define OMAP4_GPIO_REVISION 0x0000
126	#define OMAP4_GPIO_EOI 0x0020
127	#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
128	#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
129	#define OMAP4_GPIO_IRQSTATUS0 0x002c
130	#define OMAP4_GPIO_IRQSTATUS1 0x0030
131	#define OMAP4_GPIO_IRQSTATUSSET0 0x0034
132	#define OMAP4_GPIO_IRQSTATUSSET1 0x0038
133	#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
134	#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
135	#define OMAP4_GPIO_IRQWAKEN0 0x0044
136	#define OMAP4_GPIO_IRQWAKEN1 0x0048
137	#define OMAP4_GPIO_IRQENABLE1 0x011c
138	#define OMAP4_GPIO_WAKE_EN 0x0120
139	#define OMAP4_GPIO_IRQSTATUS2 0x0128
140	#define OMAP4_GPIO_IRQENABLE2 0x012c
141	#define OMAP4_GPIO_CTRL 0x0130
142	#define OMAP4_GPIO_OE 0x0134
143	#define OMAP4_GPIO_DATAIN 0x0138
144	#define OMAP4_GPIO_DATAOUT 0x013c
145	#define OMAP4_GPIO_LEVELDETECT0 0x0140
146	#define OMAP4_GPIO_LEVELDETECT1 0x0144
147	#define OMAP4_GPIO_RISINGDETECT 0x0148
148	#define OMAP4_GPIO_FALLINGDETECT 0x014c
149	#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
150	#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
151	#define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
152	#define OMAP4_GPIO_SETIRQENABLE1 0x0164
153	#define OMAP4_GPIO_CLEARWKUENA 0x0180
154	#define OMAP4_GPIO_SETWKUENA 0x0184
155	#define OMAP4_GPIO_CLEARDATAOUT 0x0190
156	#define OMAP4_GPIO_SETDATAOUT 0x0194
157
1da177e4 LT	158	#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
	159	#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
	160
59c348c3 VC	161	struct omap_gpio_dev_attr {
	162	int bank_width; /* GPIO bank width */
	163	bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
	164	};
	165
fa87931a	166	struct omap_gpio_reg_offs {
e5ff4440	167	u16 revision;
fa87931a KH	168	u16 direction;
	169	u16 datain;
	170	u16 dataout;
	171	u16 set_dataout;
	172	u16 clr_dataout;
eef4bec7 KH	173	u16 irqstatus;
eef4bec7 KH	174	u16 irqstatus2;
4e962e89 TKD	175	u16 irqstatus_raw0;
4e962e89 TKD	176	u16 irqstatus_raw1;
28f3b5a0	177	u16 irqenable;
ae10f233	178	u16 irqenable2;
28f3b5a0 KH	179	u16 set_irqenable;
28f3b5a0 KH	180	u16 clr_irqenable;
9942da0e KH	181	u16 debounce;
9942da0e KH	182	u16 debounce_en;
c8eef65a	183	u16 ctrl;
6ed87c5b	184	u16 wkup_en;
9ea14d8c TKD	185	u16 leveldetect0;
	186	u16 leveldetect1;
	187	u16 risingdetect;
	188	u16 fallingdetect;
5e571f38 TKD	189	u16 irqctrl;
	190	u16 edgectrl1;
	191	u16 edgectrl2;
fad96ea8	192	u16 pinctrl;
28f3b5a0 KH	193
28f3b5a0 KH	194	bool irqenable_inv;
fa87931a KH	195	};
fa87931a KH	196
c95d10bc	197	struct omap_gpio_platform_data {
c95d10bc VC	198	int bank_type;
c95d10bc VC	199	int bank_width; /* GPIO bank width */
5de62b86	200	int bank_stride; /* Only needed for omap1 MPUIO */
c95d10bc	201	bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
0cde8d03	202	bool loses_context; /* whether the bank would ever lose context */
d0d665a8	203	bool is_mpuio; /* whether the bank is of type MPUIO */
803a2434	204	u32 non_wakeup_gpios;
fa87931a KH	205
fa87931a KH	206	struct omap_gpio_reg_offs *regs;
60a3437d TKD	207
	208	/* Return context loss count due to PM states changing */
	209	int (get_context_loss_count)(struct device dev);
c95d10bc VC	210	};
c95d10bc VC	211
72e06d08	212	extern void omap2_gpio_prepare_for_idle(int off_mode);
43ffcd9a	213	extern void omap2_gpio_resume_after_idle(void);
5eb3bb9c KH	214	extern void omap_set_gpio_debounce(int gpio, int enable);
5eb3bb9c KH	215	extern void omap_set_gpio_debounce_time(int gpio, int enable);
3c729f1e DB	216	/-------------------------------------------------------------------------/
3c729f1e DB	217
25db711d BC	218	/*
25db711d BC	219	* Wrappers for "new style" GPIO calls, using the new infrastructure
52e31344	220	* which lets us plug in FPGA, I2C, and other implementations.
25db711d	221	*
25985edc	222	* The original OMAP-specific calls should eventually be removed.
3c729f1e DB	223	*/
3c729f1e DB	224
52e31344 DB	225	#include <linux/errno.h>
52e31344 DB	226	#include <asm-generic/gpio.h>
3c729f1e	227
1da177e4	228	#endif