projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 4bbbc1ad JY |
1 | /* |
| 2 | * General-Purpose Memory Controller for OMAP2 | |
| 3 | * | |
| 4 | * Copyright (C) 2005-2006 Nokia Corporation | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License version 2 as | |
| 8 | * published by the Free Software Foundation. | |
| 9 | */ | |
| 10 | ||
| 11 | #ifndef __OMAP2_GPMC_H | |
| 12 | #define __OMAP2_GPMC_H | |
| 13 | ||
| fd1dc87d PW |
14 | /* Maximum Number of Chip Selects */ |
| 15 | #define GPMC_CS_NUM 8 | |
| 16 | ||
| 4bbbc1ad JY |
17 | #define GPMC_CS_CONFIG1 0x00 |
| 18 | #define GPMC_CS_CONFIG2 0x04 | |
| 19 | #define GPMC_CS_CONFIG3 0x08 | |
| 20 | #define GPMC_CS_CONFIG4 0x0c | |
| 21 | #define GPMC_CS_CONFIG5 0x10 | |
| 22 | #define GPMC_CS_CONFIG6 0x14 | |
| 23 | #define GPMC_CS_CONFIG7 0x18 | |
| 24 | #define GPMC_CS_NAND_COMMAND 0x1c | |
| 25 | #define GPMC_CS_NAND_ADDRESS 0x20 | |
| 26 | #define GPMC_CS_NAND_DATA 0x24 | |
| 27 | ||
| 948d38e7 SG |
28 | /* Control Commands */ |
| 29 | #define GPMC_CONFIG_RDY_BSY 0x00000001 | |
| 30 | #define GPMC_CONFIG_DEV_SIZE 0x00000002 | |
| 31 | #define GPMC_CONFIG_DEV_TYPE 0x00000003 | |
| 32 | #define GPMC_SET_IRQ_STATUS 0x00000004 | |
| 33 | #define GPMC_CONFIG_WP 0x00000005 | |
| 34 | ||
| 35 | #define GPMC_GET_IRQ_STATUS 0x00000006 | |
| 36 | #define GPMC_PREFETCH_FIFO_CNT 0x00000007 /* bytes available in FIFO for r/w */ | |
| 37 | #define GPMC_PREFETCH_COUNT 0x00000008 /* remaining bytes to be read/write*/ | |
| 38 | #define GPMC_STATUS_BUFFER 0x00000009 /* 1: buffer is available to write */ | |
| 39 | ||
| 40 | #define GPMC_NAND_COMMAND 0x0000000a | |
| 41 | #define GPMC_NAND_ADDRESS 0x0000000b | |
| 42 | #define GPMC_NAND_DATA 0x0000000c | |
| 43 | ||
| db97eb7d SG |
44 | #define GPMC_ENABLE_IRQ 0x0000000d |
| 45 | ||
| 948d38e7 SG |
46 | /* ECC commands */ |
| 47 | #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ | |
| 48 | #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */ | |
| 49 | #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */ | |
| 646e3ed1 | 50 | |
| 4bbbc1ad | 51 | #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) |
| 1c22cc13 | 52 | #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) |
| 4bbbc1ad JY |
53 | #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) |
| 54 | #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29) | |
| 1c22cc13 | 55 | #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28) |
| 4bbbc1ad JY |
56 | #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27) |
| 57 | #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27) | |
| 58 | #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25) | |
| 59 | #define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23) | |
| 60 | #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22) | |
| 61 | #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21) | |
| 62 | #define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18) | |
| 63 | #define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16) | |
| 64 | #define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12) | |
| 65 | #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) | |
| 66 | #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) | |
| 67 | #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) | |
| 4bbbc1ad JY |
68 | #define GPMC_CONFIG1_MUXADDDATA (1 << 9) |
| 69 | #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) | |
| 70 | #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) | |
| 71 | #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) | |
| 72 | #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2)) | |
| 73 | #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) | |
| a2d3e7ba | 74 | #define GPMC_CONFIG7_CSVALID (1 << 6) |
| 4bbbc1ad | 75 | |
| 948d38e7 SG |
76 | #define GPMC_DEVICETYPE_NOR 0 |
| 77 | #define GPMC_DEVICETYPE_NAND 2 | |
| 78 | #define GPMC_CONFIG_WRITEPROTECT 0x00000010 | |
| 79 | #define GPMC_STATUS_BUFF_EMPTY 0x00000001 | |
| 80 | #define WR_RD_PIN_MONITORING 0x00600000 | |
| 81 | #define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) | |
| 82 | #define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) | |
| db97eb7d SG |
83 | #define GPMC_IRQ_FIFOEVENTENABLE 0x01 |
| 84 | #define GPMC_IRQ_COUNT_EVENT 0x02 | |
| 948d38e7 | 85 | |
| 4bbbc1ad | 86 | /* |
| a3551f5b AH |
87 | * Note that all values in this struct are in nanoseconds except sync_clk |
| 88 | * (which is in picoseconds), while the register values are in gpmc_fck cycles. | |
| 4bbbc1ad JY |
89 | */ |
| 90 | struct gpmc_timings { | |
| a3551f5b AH |
91 | /* Minimum clock period for synchronous mode (in picoseconds) */ |
| 92 | u32 sync_clk; | |
| 4bbbc1ad JY |
93 | |
| 94 | /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */ | |
| 95 | u16 cs_on; /* Assertion time */ | |
| 96 | u16 cs_rd_off; /* Read deassertion time */ | |
| 97 | u16 cs_wr_off; /* Write deassertion time */ | |
| 98 | ||
| 99 | /* ADV signal timings corresponding to GPMC_CONFIG3 */ | |
| 100 | u16 adv_on; /* Assertion time */ | |
| 101 | u16 adv_rd_off; /* Read deassertion time */ | |
| 102 | u16 adv_wr_off; /* Write deassertion time */ | |
| 103 | ||
| 104 | /* WE signals timings corresponding to GPMC_CONFIG4 */ | |
| 105 | u16 we_on; /* WE assertion time */ | |
| 106 | u16 we_off; /* WE deassertion time */ | |
| 107 | ||
| 108 | /* OE signals timings corresponding to GPMC_CONFIG4 */ | |
| 109 | u16 oe_on; /* OE assertion time */ | |
| 110 | u16 oe_off; /* OE deassertion time */ | |
| 111 | ||
| 112 | /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */ | |
| 113 | u16 page_burst_access; /* Multiple access word delay */ | |
| 114 | u16 access; /* Start-cycle to first data valid delay */ | |
| 115 | u16 rd_cycle; /* Total read cycle time */ | |
| 116 | u16 wr_cycle; /* Total write cycle time */ | |
| cc26b3b0 SMK |
117 | |
| 118 | /* The following are only on OMAP3430 */ | |
| 119 | u16 wr_access; /* WRACCESSTIME */ | |
| 120 | u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */ | |
| 4bbbc1ad JY |
121 | }; |
| 122 | ||
| 123 | extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); | |
| a3551f5b | 124 | extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps); |
| fd1dc87d | 125 | extern unsigned int gpmc_ticks_to_ns(unsigned int ticks); |
| 23300597 KS |
126 | extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns); |
| 127 | extern unsigned long gpmc_get_fclk_period(void); | |
| 4bbbc1ad JY |
128 | |
| 129 | extern void gpmc_cs_write_reg(int cs, int idx, u32 val); | |
| 130 | extern u32 gpmc_cs_read_reg(int cs, int idx); | |
| 131 | extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk); | |
| 132 | extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t); | |
| f37e4580 ID |
133 | extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); |
| 134 | extern void gpmc_cs_free(int cs); | |
| 39b8e698 | 135 | extern int gpmc_cs_set_reserved(int cs, int reserved); |
| f4e4c324 | 136 | extern int gpmc_cs_reserved(int cs); |
| 59e9c5ae | 137 | extern int gpmc_prefetch_enable(int cs, int dma_mode, |
| 138 | unsigned int u32_count, int is_write); | |
| 948d38e7 | 139 | extern int gpmc_prefetch_reset(int cs); |
| a2d3e7ba RN |
140 | extern void omap3_gpmc_save_context(void); |
| 141 | extern void omap3_gpmc_restore_context(void); | |
| 948d38e7 SG |
142 | extern int gpmc_read_status(int cmd); |
| 143 | extern int gpmc_cs_configure(int cs, int cmd, int wval); | |
| 144 | extern int gpmc_nand_read(int cs, int cmd); | |
| 145 | extern int gpmc_nand_write(int cs, int cmd, int wval); | |
| 4bbbc1ad | 146 | |
| 948d38e7 SG |
147 | int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size); |
| 148 | int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code); | |
| 4bbbc1ad | 149 | #endif |