[deliverable/linux.git] / arch / arm / plat-omap / include / plat / irqs.h

/*
 *  arch/arm/plat-omap/include/mach/irqs.h
 *
 *  Copyright (C) Greg Lonnon 2001
 *  Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
 *	 are different.
 */

#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
#define __ASM_ARCH_OMAP15XX_IRQS_H

/* All OMAP4 specific defines are moved to irqs-44xx.h */
#include "irqs-44xx.h"

/*
 * IRQ numbers for interrupt handler 1
 *
 * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
 *
 */
#define INT_CAMERA		1
#define INT_FIQ			3
#define INT_RTDX		6
#define INT_DSP_MMU_ABORT	7
#define INT_HOST		8
#define INT_ABORT		9
#define INT_BRIDGE_PRIV		13
#define INT_GPIO_BANK1		14
#define INT_UART3		15
#define INT_TIMER3		16
#define INT_DMA_CH0_6		19
#define INT_DMA_CH1_7		20
#define INT_DMA_CH2_8		21
#define INT_DMA_CH3		22
#define INT_DMA_CH4		23
#define INT_DMA_CH5		24
#define INT_DMA_LCD		25
#define INT_TIMER1		26
#define INT_WD_TIMER		27
#define INT_BRIDGE_PUB		28
#define INT_TIMER2		30
#define INT_LCD_CTRL		31

/*
 * OMAP-1510 specific IRQ numbers for interrupt handler 1
 */
#define INT_1510_IH2_IRQ	0
#define INT_1510_RES2		2
#define INT_1510_SPI_TX		4
#define INT_1510_SPI_RX		5
#define INT_1510_DSP_MAILBOX1	10
#define INT_1510_DSP_MAILBOX2	11
#define INT_1510_RES12		12
#define INT_1510_LB_MMU		17
#define INT_1510_RES18		18
#define INT_1510_LOCAL_BUS	29

/*
 * OMAP-1610 specific IRQ numbers for interrupt handler 1
 */
#define INT_1610_IH2_IRQ	INT_1510_IH2_IRQ
#define INT_1610_IH2_FIQ	2
#define INT_1610_McBSP2_TX	4
#define INT_1610_McBSP2_RX	5
#define INT_1610_DSP_MAILBOX1	10
#define INT_1610_DSP_MAILBOX2	11
#define INT_1610_LCD_LINE	12
#define INT_1610_GPTIMER1	17
#define INT_1610_GPTIMER2	18
#define INT_1610_SSR_FIFO_0	29

/*
 * OMAP-7xx specific IRQ numbers for interrupt handler 1
 */
#define INT_7XX_IH2_FIQ		0
#define INT_7XX_IH2_IRQ		1
#define INT_7XX_USB_NON_ISO	2
#define INT_7XX_USB_ISO		3
#define INT_7XX_ICR		4
#define INT_7XX_EAC		5
#define INT_7XX_GPIO_BANK1	6
#define INT_7XX_GPIO_BANK2	7
#define INT_7XX_GPIO_BANK3	8
#define INT_7XX_McBSP2TX	10
#define INT_7XX_McBSP2RX	11
#define INT_7XX_McBSP2RX_OVF	12
#define INT_7XX_LCD_LINE	14
#define INT_7XX_GSM_PROTECT	15
#define INT_7XX_TIMER3		16
#define INT_7XX_GPIO_BANK5	17
#define INT_7XX_GPIO_BANK6	18
#define INT_7XX_SPGIO_WR	29

/*
 * IRQ numbers for interrupt handler 2
 *
 * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
 */
#define IH2_BASE		32

#define INT_KEYBOARD		(1 + IH2_BASE)
#define INT_uWireTX		(2 + IH2_BASE)
#define INT_uWireRX		(3 + IH2_BASE)
#define INT_I2C			(4 + IH2_BASE)
#define INT_MPUIO		(5 + IH2_BASE)
#define INT_USB_HHC_1		(6 + IH2_BASE)
#define INT_McBSP3TX		(10 + IH2_BASE)
#define INT_McBSP3RX		(11 + IH2_BASE)
#define INT_McBSP1TX		(12 + IH2_BASE)
#define INT_McBSP1RX		(13 + IH2_BASE)
#define INT_UART1		(14 + IH2_BASE)
#define INT_UART2		(15 + IH2_BASE)
#define INT_BT_MCSI1TX		(16 + IH2_BASE)
#define INT_BT_MCSI1RX		(17 + IH2_BASE)
#define INT_SOSSI_MATCH		(19 + IH2_BASE)
#define INT_USB_W2FC		(20 + IH2_BASE)
#define INT_1WIRE		(21 + IH2_BASE)
#define INT_OS_TIMER		(22 + IH2_BASE)
#define INT_MMC			(23 + IH2_BASE)
#define INT_GAUGE_32K		(24 + IH2_BASE)
#define INT_RTC_TIMER		(25 + IH2_BASE)
#define INT_RTC_ALARM		(26 + IH2_BASE)
#define INT_MEM_STICK		(27 + IH2_BASE)

/*
 * OMAP-1510 specific IRQ numbers for interrupt handler 2
 */
#define INT_1510_DSP_MMU	(28 + IH2_BASE)
#define INT_1510_COM_SPI_RO	(31 + IH2_BASE)

/*
 * OMAP-1610 specific IRQ numbers for interrupt handler 2
 */
#define INT_1610_FAC		(0 + IH2_BASE)
#define INT_1610_USB_HHC_2	(7 + IH2_BASE)
#define INT_1610_USB_OTG	(8 + IH2_BASE)
#define INT_1610_SoSSI		(9 + IH2_BASE)
#define INT_1610_SoSSI_MATCH	(19 + IH2_BASE)
#define INT_1610_DSP_MMU	(28 + IH2_BASE)
#define INT_1610_McBSP2RX_OF	(31 + IH2_BASE)
#define INT_1610_STI		(32 + IH2_BASE)
#define INT_1610_STI_WAKEUP	(33 + IH2_BASE)
#define INT_1610_GPTIMER3	(34 + IH2_BASE)
#define INT_1610_GPTIMER4	(35 + IH2_BASE)
#define INT_1610_GPTIMER5	(36 + IH2_BASE)
#define INT_1610_GPTIMER6	(37 + IH2_BASE)
#define INT_1610_GPTIMER7	(38 + IH2_BASE)
#define INT_1610_GPTIMER8	(39 + IH2_BASE)
#define INT_1610_GPIO_BANK2	(40 + IH2_BASE)
#define INT_1610_GPIO_BANK3	(41 + IH2_BASE)
#define INT_1610_MMC2		(42 + IH2_BASE)
#define INT_1610_CF		(43 + IH2_BASE)
#define INT_1610_WAKE_UP_REQ	(46 + IH2_BASE)
#define INT_1610_GPIO_BANK4	(48 + IH2_BASE)
#define INT_1610_SPI		(49 + IH2_BASE)
#define INT_1610_DMA_CH6	(53 + IH2_BASE)
#define INT_1610_DMA_CH7	(54 + IH2_BASE)
#define INT_1610_DMA_CH8	(55 + IH2_BASE)
#define INT_1610_DMA_CH9	(56 + IH2_BASE)
#define INT_1610_DMA_CH10	(57 + IH2_BASE)
#define INT_1610_DMA_CH11	(58 + IH2_BASE)
#define INT_1610_DMA_CH12	(59 + IH2_BASE)
#define INT_1610_DMA_CH13	(60 + IH2_BASE)
#define INT_1610_DMA_CH14	(61 + IH2_BASE)
#define INT_1610_DMA_CH15	(62 + IH2_BASE)
#define INT_1610_NAND		(63 + IH2_BASE)
#define INT_1610_SHA1MD5	(91 + IH2_BASE)

/*
 * OMAP-7xx specific IRQ numbers for interrupt handler 2
 */
#define INT_7XX_HW_ERRORS	(0 + IH2_BASE)
#define INT_7XX_NFIQ_PWR_FAIL	(1 + IH2_BASE)
#define INT_7XX_CFCD		(2 + IH2_BASE)
#define INT_7XX_CFIREQ		(3 + IH2_BASE)
#define INT_7XX_I2C		(4 + IH2_BASE)
#define INT_7XX_PCC		(5 + IH2_BASE)
#define INT_7XX_MPU_EXT_NIRQ	(6 + IH2_BASE)
#define INT_7XX_SPI_100K_1	(7 + IH2_BASE)
#define INT_7XX_SYREN_SPI	(8 + IH2_BASE)
#define INT_7XX_VLYNQ		(9 + IH2_BASE)
#define INT_7XX_GPIO_BANK4	(10 + IH2_BASE)
#define INT_7XX_McBSP1TX	(11 + IH2_BASE)
#define INT_7XX_McBSP1RX	(12 + IH2_BASE)
#define INT_7XX_McBSP1RX_OF	(13 + IH2_BASE)
#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
#define INT_7XX_UART_MODEM_1	(15 + IH2_BASE)
#define INT_7XX_MCSI		(16 + IH2_BASE)
#define INT_7XX_uWireTX		(17 + IH2_BASE)
#define INT_7XX_uWireRX		(18 + IH2_BASE)
#define INT_7XX_SMC_CD		(19 + IH2_BASE)
#define INT_7XX_SMC_IREQ	(20 + IH2_BASE)
#define INT_7XX_HDQ_1WIRE	(21 + IH2_BASE)
#define INT_7XX_TIMER32K	(22 + IH2_BASE)
#define INT_7XX_MMC_SDIO	(23 + IH2_BASE)
#define INT_7XX_UPLD		(24 + IH2_BASE)
#define INT_7XX_USB_HHC_1	(27 + IH2_BASE)
#define INT_7XX_USB_HHC_2	(28 + IH2_BASE)
#define INT_7XX_USB_GENI	(29 + IH2_BASE)
#define INT_7XX_USB_OTG		(30 + IH2_BASE)
#define INT_7XX_CAMERA_IF	(31 + IH2_BASE)
#define INT_7XX_RNG		(32 + IH2_BASE)
#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
#define INT_7XX_DBB_RF_EN	(34 + IH2_BASE)
#define INT_7XX_MPUIO_KEYPAD	(35 + IH2_BASE)
#define INT_7XX_SHA1_MD5	(36 + IH2_BASE)
#define INT_7XX_SPI_100K_2	(37 + IH2_BASE)
#define INT_7XX_RNG_IDLE	(38 + IH2_BASE)
#define INT_7XX_MPUIO		(39 + IH2_BASE)
#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF	(40 + IH2_BASE)
#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
#define INT_7XX_LLPC_OE_RISING	(42 + IH2_BASE)
#define INT_7XX_LLPC_VSYNC	(43 + IH2_BASE)
#define INT_7XX_WAKE_UP_REQ	(46 + IH2_BASE)
#define INT_7XX_DMA_CH6		(53 + IH2_BASE)
#define INT_7XX_DMA_CH7		(54 + IH2_BASE)
#define INT_7XX_DMA_CH8		(55 + IH2_BASE)
#define INT_7XX_DMA_CH9		(56 + IH2_BASE)
#define INT_7XX_DMA_CH10	(57 + IH2_BASE)
#define INT_7XX_DMA_CH11	(58 + IH2_BASE)
#define INT_7XX_DMA_CH12	(59 + IH2_BASE)
#define INT_7XX_DMA_CH13	(60 + IH2_BASE)
#define INT_7XX_DMA_CH14	(61 + IH2_BASE)
#define INT_7XX_DMA_CH15	(62 + IH2_BASE)
#define INT_7XX_NAND		(63 + IH2_BASE)

#define INT_24XX_SYS_NIRQ	7
#define INT_24XX_SDMA_IRQ0	12
#define INT_24XX_SDMA_IRQ1	13
#define INT_24XX_SDMA_IRQ2	14
#define INT_24XX_SDMA_IRQ3	15
#define INT_24XX_CAM_IRQ	24
#define INT_24XX_DSS_IRQ	25
#define INT_24XX_MAIL_U0_MPU	26
#define INT_24XX_DSP_UMA	27
#define INT_24XX_DSP_MMU	28
#define INT_24XX_GPIO_BANK1	29
#define INT_24XX_GPIO_BANK2	30
#define INT_24XX_GPIO_BANK3	31
#define INT_24XX_GPIO_BANK4	32
#define INT_24XX_GPIO_BANK5	33
#define INT_24XX_MAIL_U3_MPU	34
#define INT_24XX_GPTIMER1	37
#define INT_24XX_GPTIMER2	38
#define INT_24XX_GPTIMER3	39
#define INT_24XX_GPTIMER4	40
#define INT_24XX_GPTIMER5	41
#define INT_24XX_GPTIMER6	42
#define INT_24XX_GPTIMER7	43
#define INT_24XX_GPTIMER8	44
#define INT_24XX_GPTIMER9	45
#define INT_24XX_GPTIMER10	46
#define INT_24XX_GPTIMER11	47
#define INT_24XX_GPTIMER12	48
#define INT_24XX_SHA1MD5	51
#define INT_24XX_MCBSP4_IRQ_TX	54
#define INT_24XX_MCBSP4_IRQ_RX	55
#define INT_24XX_I2C1_IRQ	56
#define INT_24XX_I2C2_IRQ	57
#define INT_24XX_HDQ_IRQ	58
#define INT_24XX_MCBSP1_IRQ_TX	59
#define INT_24XX_MCBSP1_IRQ_RX	60
#define INT_24XX_MCBSP2_IRQ_TX	62
#define INT_24XX_MCBSP2_IRQ_RX	63
#define INT_24XX_SPI1_IRQ	65
#define INT_24XX_SPI2_IRQ	66
#define INT_24XX_UART1_IRQ	72
#define INT_24XX_UART2_IRQ	73
#define INT_24XX_UART3_IRQ	74
#define INT_24XX_USB_IRQ_GEN	75
#define INT_24XX_USB_IRQ_NISO	76
#define INT_24XX_USB_IRQ_ISO	77
#define INT_24XX_USB_IRQ_HGEN	78
#define INT_24XX_USB_IRQ_HSOF	79
#define INT_24XX_USB_IRQ_OTG	80
#define INT_24XX_MCBSP5_IRQ_TX	81
#define INT_24XX_MCBSP5_IRQ_RX	82
#define INT_24XX_MMC_IRQ	83
#define INT_24XX_MMC2_IRQ	86
#define INT_24XX_MCBSP3_IRQ_TX	89
#define INT_24XX_MCBSP3_IRQ_RX	90
#define INT_24XX_SPI3_IRQ	91

#define INT_243X_MCBSP2_IRQ	16
#define INT_243X_MCBSP3_IRQ	17
#define INT_243X_MCBSP4_IRQ	18
#define INT_243X_MCBSP5_IRQ	19
#define INT_243X_MCBSP1_IRQ	64
#define INT_243X_HS_USB_MC	92
#define INT_243X_HS_USB_DMA	93
#define INT_243X_CARKIT_IRQ	94

#define INT_34XX_BENCH_MPU_EMUL	3
#define INT_34XX_ST_MCBSP2_IRQ	4
#define INT_34XX_ST_MCBSP3_IRQ	5
#define INT_34XX_SSM_ABORT_IRQ	6
#define INT_34XX_SYS_NIRQ	7
#define INT_34XX_D2D_FW_IRQ	8
#define INT_34XX_L3_DBG_IRQ     9
#define INT_34XX_L3_APP_IRQ     10
#define INT_34XX_PRCM_MPU_IRQ	11
#define INT_34XX_MCBSP1_IRQ	16
#define INT_34XX_MCBSP2_IRQ	17
#define INT_34XX_GPMC_IRQ	20
#define INT_34XX_MCBSP3_IRQ	22
#define INT_34XX_MCBSP4_IRQ	23
#define INT_34XX_CAM_IRQ	24
#define INT_34XX_MCBSP5_IRQ	27
#define INT_34XX_GPIO_BANK1	29
#define INT_34XX_GPIO_BANK2	30
#define INT_34XX_GPIO_BANK3	31
#define INT_34XX_GPIO_BANK4	32
#define INT_34XX_GPIO_BANK5	33
#define INT_34XX_GPIO_BANK6	34
#define INT_34XX_USIM_IRQ	35
#define INT_34XX_WDT3_IRQ	36
#define INT_34XX_SPI4_IRQ	48
#define INT_34XX_SHA1MD52_IRQ	49
#define INT_34XX_FPKA_READY_IRQ	50
#define INT_34XX_SHA1MD51_IRQ	51
#define INT_34XX_RNG_IRQ	52
#define INT_34XX_I2C3_IRQ	61
#define INT_34XX_FPKA_ERROR_IRQ	64
#define INT_34XX_PBIAS_IRQ	75
#define INT_34XX_OHCI_IRQ	76
#define INT_34XX_EHCI_IRQ	77
#define INT_34XX_TLL_IRQ	78
#define INT_34XX_PARTHASH_IRQ	79
#define INT_34XX_MMC3_IRQ	94
#define INT_34XX_GPT12_IRQ	95

#define INT_36XX_UART4_IRQ	80

#define INT_35XX_HECC0_IRQ		24
#define INT_35XX_HECC1_IRQ		28
#define INT_35XX_EMAC_C0_RXTHRESH_IRQ	67
#define INT_35XX_EMAC_C0_RX_PULSE_IRQ	68
#define INT_35XX_EMAC_C0_TX_PULSE_IRQ	69
#define INT_35XX_EMAC_C0_MISC_PULSE_IRQ	70
#define INT_35XX_USBOTG_IRQ		71
#define INT_35XX_UART4_IRQ		84
#define INT_35XX_CCDC_VD0_IRQ		88
#define INT_35XX_CCDC_VD1_IRQ		92
#define INT_35XX_CCDC_VD2_IRQ		93

/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
 * 16 MPUIO lines */
#define OMAP_MAX_GPIO_LINES	192
#define IH_GPIO_BASE		(128 + IH2_BASE)
#define IH_MPUIO_BASE		(OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
#define OMAP_IRQ_END		(IH_MPUIO_BASE + 16)

/* External FPGA handles interrupts on Innovator boards */
#define	OMAP_FPGA_IRQ_BASE	(OMAP_IRQ_END)
#ifdef	CONFIG_MACH_OMAP_INNOVATOR
#define OMAP_FPGA_NR_IRQS	24
#else
#define OMAP_FPGA_NR_IRQS	0
#endif
#define OMAP_FPGA_IRQ_END	(OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)

/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
#define	TWL4030_IRQ_BASE	(OMAP_FPGA_IRQ_END)
#ifdef	CONFIG_TWL4030_CORE
#define	TWL4030_BASE_NR_IRQS	8
#define	TWL4030_PWR_NR_IRQS	8
#else
#define	TWL4030_BASE_NR_IRQS	0
#define	TWL4030_PWR_NR_IRQS	0
#endif
#define TWL4030_IRQ_END		(TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
#define TWL4030_PWR_IRQ_BASE	TWL4030_IRQ_END
#define	TWL4030_PWR_IRQ_END	(TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)

/* External TWL4030 gpio interrupts are optional */
#define TWL4030_GPIO_IRQ_BASE	TWL4030_PWR_IRQ_END
#ifdef	CONFIG_GPIO_TWL4030
#define TWL4030_GPIO_NR_IRQS	18
#else
#define	TWL4030_GPIO_NR_IRQS	0
#endif
#define TWL4030_GPIO_IRQ_END	(TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)

#define	TWL6030_IRQ_BASE	(OMAP_FPGA_IRQ_END)
#ifdef CONFIG_TWL4030_CORE
#define	TWL6030_BASE_NR_IRQS	20
#else
#define	TWL6030_BASE_NR_IRQS	0
#endif
#define TWL6030_IRQ_END		(TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS)

#define TWL6040_CODEC_IRQ_BASE	TWL6030_IRQ_END
#ifdef CONFIG_TWL6040_CODEC
#define TWL6040_CODEC_NR_IRQS	6
#else
#define TWL6040_CODEC_NR_IRQS	0
#endif
#define TWL6040_CODEC_IRQ_END	(TWL6040_CODEC_IRQ_BASE + TWL6040_CODEC_NR_IRQS)

/* Total number of interrupts depends on the enabled blocks above */
#if (TWL4030_GPIO_IRQ_END > TWL6040_CODEC_IRQ_END)
#define TWL_IRQ_END 		TWL4030_GPIO_IRQ_END
#else
#define TWL_IRQ_END		TWL6040_CODEC_IRQ_END
#endif

/* GPMC related */
#define OMAP_GPMC_IRQ_BASE	(TWL_IRQ_END)
#define OMAP_GPMC_NR_IRQS	8
#define OMAP_GPMC_IRQ_END	(OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)

/* PRCM IRQ handler */
#ifdef CONFIG_ARCH_OMAP2PLUS
#define OMAP_PRCM_IRQ_BASE	(OMAP_GPMC_IRQ_END)
#define OMAP_PRCM_NR_IRQS	64
#define OMAP_PRCM_IRQ_END	(OMAP_PRCM_IRQ_BASE + OMAP_PRCM_NR_IRQS)
#else
#define OMAP_PRCM_IRQ_END	OMAP_GPMC_IRQ_END
#endif

#define NR_IRQS			OMAP_PRCM_IRQ_END

#define OMAP_IRQ_BIT(irq)	(1 << ((irq) % 32))

#define INTCPS_NR_MIR_REGS	3
#define INTCPS_NR_IRQS		96

#include <mach/hardware.h>

#ifdef CONFIG_FIQ
#define FIQ_START		1024
#endif

#endif
Commit	Line	Data
1da177e4	1	/*
a09e64fb	2	* arch/arm/plat-omap/include/mach/irqs.h
1da177e4 LT	3	*
	4	* Copyright (C) Greg Lonnon 2001
	5	* Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
	6	*
44169075 SS	7	* Copyright (C) 2009 Texas Instruments
	8	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
	9	*
1da177e4 LT	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	23	*
	24	* NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
	25	* are different.
	26	*/
	27
9ad5897c TL	28	#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
9ad5897c TL	29	#define __ASM_ARCH_OMAP15XX_IRQS_H
1da177e4	30
5772ca7d SS	31	/* All OMAP4 specific defines are moved to irqs-44xx.h */
	32	#include "irqs-44xx.h"
	33
1da177e4 LT	34	/*
	35	* IRQ numbers for interrupt handler 1
	36	*
	37	* NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
	38	*
	39	*/
1da177e4 LT	40	#define INT_CAMERA 1
	41	#define INT_FIQ 3
	42	#define INT_RTDX 6
	43	#define INT_DSP_MMU_ABORT 7
	44	#define INT_HOST 8
	45	#define INT_ABORT 9
1da177e4 LT	46	#define INT_BRIDGE_PRIV 13
	47	#define INT_GPIO_BANK1 14
	48	#define INT_UART3 15
	49	#define INT_TIMER3 16
	50	#define INT_DMA_CH0_6 19
	51	#define INT_DMA_CH1_7 20
	52	#define INT_DMA_CH2_8 21
	53	#define INT_DMA_CH3 22
	54	#define INT_DMA_CH4 23
	55	#define INT_DMA_CH5 24
	56	#define INT_DMA_LCD 25
	57	#define INT_TIMER1 26
	58	#define INT_WD_TIMER 27
	59	#define INT_BRIDGE_PUB 28
	60	#define INT_TIMER2 30
	61	#define INT_LCD_CTRL 31
	62
	63	/*
	64	* OMAP-1510 specific IRQ numbers for interrupt handler 1
	65	*/
9ad5897c	66	#define INT_1510_IH2_IRQ 0
1da177e4 LT	67	#define INT_1510_RES2 2
	68	#define INT_1510_SPI_TX 4
	69	#define INT_1510_SPI_RX 5
f4e4c324 TL	70	#define INT_1510_DSP_MAILBOX1 10
f4e4c324 TL	71	#define INT_1510_DSP_MAILBOX2 11
1da177e4 LT	72	#define INT_1510_RES12 12
	73	#define INT_1510_LB_MMU 17
	74	#define INT_1510_RES18 18
	75	#define INT_1510_LOCAL_BUS 29
	76
	77	/*
	78	* OMAP-1610 specific IRQ numbers for interrupt handler 1
	79	*/
03a9e512	80	#define INT_1610_IH2_IRQ INT_1510_IH2_IRQ
1da177e4 LT	81	#define INT_1610_IH2_FIQ 2
	82	#define INT_1610_McBSP2_TX 4
	83	#define INT_1610_McBSP2_RX 5
f4e4c324 TL	84	#define INT_1610_DSP_MAILBOX1 10
f4e4c324 TL	85	#define INT_1610_DSP_MAILBOX2 11
1da177e4 LT	86	#define INT_1610_LCD_LINE 12
	87	#define INT_1610_GPTIMER1 17
	88	#define INT_1610_GPTIMER2 18
	89	#define INT_1610_SSR_FIFO_0 29
	90
	91	/*
372b1c32	92	* OMAP-7xx specific IRQ numbers for interrupt handler 1
1da177e4	93	*/
372b1c32 AB	94	#define INT_7XX_IH2_FIQ 0
	95	#define INT_7XX_IH2_IRQ 1
	96	#define INT_7XX_USB_NON_ISO 2
	97	#define INT_7XX_USB_ISO 3
	98	#define INT_7XX_ICR 4
	99	#define INT_7XX_EAC 5
	100	#define INT_7XX_GPIO_BANK1 6
	101	#define INT_7XX_GPIO_BANK2 7
	102	#define INT_7XX_GPIO_BANK3 8
	103	#define INT_7XX_McBSP2TX 10
	104	#define INT_7XX_McBSP2RX 11
	105	#define INT_7XX_McBSP2RX_OVF 12
	106	#define INT_7XX_LCD_LINE 14
	107	#define INT_7XX_GSM_PROTECT 15
	108	#define INT_7XX_TIMER3 16
	109	#define INT_7XX_GPIO_BANK5 17
	110	#define INT_7XX_GPIO_BANK6 18
	111	#define INT_7XX_SPGIO_WR 29
1da177e4 LT	112
	113	/*
	114	* IRQ numbers for interrupt handler 2
	115	*
	116	* NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
	117	*/
	118	#define IH2_BASE 32
	119
	120	#define INT_KEYBOARD (1 + IH2_BASE)
	121	#define INT_uWireTX (2 + IH2_BASE)
	122	#define INT_uWireRX (3 + IH2_BASE)
	123	#define INT_I2C (4 + IH2_BASE)
	124	#define INT_MPUIO (5 + IH2_BASE)
	125	#define INT_USB_HHC_1 (6 + IH2_BASE)
	126	#define INT_McBSP3TX (10 + IH2_BASE)
	127	#define INT_McBSP3RX (11 + IH2_BASE)
	128	#define INT_McBSP1TX (12 + IH2_BASE)
	129	#define INT_McBSP1RX (13 + IH2_BASE)
	130	#define INT_UART1 (14 + IH2_BASE)
	131	#define INT_UART2 (15 + IH2_BASE)
	132	#define INT_BT_MCSI1TX (16 + IH2_BASE)
	133	#define INT_BT_MCSI1RX (17 + IH2_BASE)
646e3ed1	134	#define INT_SOSSI_MATCH (19 + IH2_BASE)
1da177e4 LT	135	#define INT_USB_W2FC (20 + IH2_BASE)
	136	#define INT_1WIRE (21 + IH2_BASE)
	137	#define INT_OS_TIMER (22 + IH2_BASE)
	138	#define INT_MMC (23 + IH2_BASE)
	139	#define INT_GAUGE_32K (24 + IH2_BASE)
	140	#define INT_RTC_TIMER (25 + IH2_BASE)
	141	#define INT_RTC_ALARM (26 + IH2_BASE)
	142	#define INT_MEM_STICK (27 + IH2_BASE)
1da177e4 LT	143
	144	/*
	145	* OMAP-1510 specific IRQ numbers for interrupt handler 2
	146	*/
f4e4c324	147	#define INT_1510_DSP_MMU (28 + IH2_BASE)
1da177e4 LT	148	#define INT_1510_COM_SPI_RO (31 + IH2_BASE)
	149
	150	/*
	151	* OMAP-1610 specific IRQ numbers for interrupt handler 2
	152	*/
	153	#define INT_1610_FAC (0 + IH2_BASE)
	154	#define INT_1610_USB_HHC_2 (7 + IH2_BASE)
	155	#define INT_1610_USB_OTG (8 + IH2_BASE)
	156	#define INT_1610_SoSSI (9 + IH2_BASE)
	157	#define INT_1610_SoSSI_MATCH (19 + IH2_BASE)
f4e4c324	158	#define INT_1610_DSP_MMU (28 + IH2_BASE)
1da177e4 LT	159	#define INT_1610_McBSP2RX_OF (31 + IH2_BASE)
	160	#define INT_1610_STI (32 + IH2_BASE)
	161	#define INT_1610_STI_WAKEUP (33 + IH2_BASE)
	162	#define INT_1610_GPTIMER3 (34 + IH2_BASE)
	163	#define INT_1610_GPTIMER4 (35 + IH2_BASE)
	164	#define INT_1610_GPTIMER5 (36 + IH2_BASE)
	165	#define INT_1610_GPTIMER6 (37 + IH2_BASE)
	166	#define INT_1610_GPTIMER7 (38 + IH2_BASE)
	167	#define INT_1610_GPTIMER8 (39 + IH2_BASE)
	168	#define INT_1610_GPIO_BANK2 (40 + IH2_BASE)
	169	#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
	170	#define INT_1610_MMC2 (42 + IH2_BASE)
	171	#define INT_1610_CF (43 + IH2_BASE)
af973d2a	172	#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE)
1da177e4 LT	173	#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
	174	#define INT_1610_SPI (49 + IH2_BASE)
	175	#define INT_1610_DMA_CH6 (53 + IH2_BASE)
	176	#define INT_1610_DMA_CH7 (54 + IH2_BASE)
	177	#define INT_1610_DMA_CH8 (55 + IH2_BASE)
	178	#define INT_1610_DMA_CH9 (56 + IH2_BASE)
	179	#define INT_1610_DMA_CH10 (57 + IH2_BASE)
	180	#define INT_1610_DMA_CH11 (58 + IH2_BASE)
	181	#define INT_1610_DMA_CH12 (59 + IH2_BASE)
	182	#define INT_1610_DMA_CH13 (60 + IH2_BASE)
	183	#define INT_1610_DMA_CH14 (61 + IH2_BASE)
	184	#define INT_1610_DMA_CH15 (62 + IH2_BASE)
	185	#define INT_1610_NAND (63 + IH2_BASE)
646e3ed1	186	#define INT_1610_SHA1MD5 (91 + IH2_BASE)
1da177e4 LT	187
1da177e4 LT	188	/*
372b1c32	189	* OMAP-7xx specific IRQ numbers for interrupt handler 2
1da177e4	190	*/
372b1c32 AB	191	#define INT_7XX_HW_ERRORS (0 + IH2_BASE)
	192	#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE)
	193	#define INT_7XX_CFCD (2 + IH2_BASE)
	194	#define INT_7XX_CFIREQ (3 + IH2_BASE)
	195	#define INT_7XX_I2C (4 + IH2_BASE)
	196	#define INT_7XX_PCC (5 + IH2_BASE)
	197	#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE)
	198	#define INT_7XX_SPI_100K_1 (7 + IH2_BASE)
	199	#define INT_7XX_SYREN_SPI (8 + IH2_BASE)
	200	#define INT_7XX_VLYNQ (9 + IH2_BASE)
	201	#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE)
	202	#define INT_7XX_McBSP1TX (11 + IH2_BASE)
	203	#define INT_7XX_McBSP1RX (12 + IH2_BASE)
	204	#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE)
	205	#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
	206	#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE)
	207	#define INT_7XX_MCSI (16 + IH2_BASE)
	208	#define INT_7XX_uWireTX (17 + IH2_BASE)
	209	#define INT_7XX_uWireRX (18 + IH2_BASE)
	210	#define INT_7XX_SMC_CD (19 + IH2_BASE)
	211	#define INT_7XX_SMC_IREQ (20 + IH2_BASE)
	212	#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE)
	213	#define INT_7XX_TIMER32K (22 + IH2_BASE)
	214	#define INT_7XX_MMC_SDIO (23 + IH2_BASE)
	215	#define INT_7XX_UPLD (24 + IH2_BASE)
	216	#define INT_7XX_USB_HHC_1 (27 + IH2_BASE)
	217	#define INT_7XX_USB_HHC_2 (28 + IH2_BASE)
	218	#define INT_7XX_USB_GENI (29 + IH2_BASE)
	219	#define INT_7XX_USB_OTG (30 + IH2_BASE)
	220	#define INT_7XX_CAMERA_IF (31 + IH2_BASE)
	221	#define INT_7XX_RNG (32 + IH2_BASE)
	222	#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
	223	#define INT_7XX_DBB_RF_EN (34 + IH2_BASE)
	224	#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE)
	225	#define INT_7XX_SHA1_MD5 (36 + IH2_BASE)
	226	#define INT_7XX_SPI_100K_2 (37 + IH2_BASE)
	227	#define INT_7XX_RNG_IDLE (38 + IH2_BASE)
	228	#define INT_7XX_MPUIO (39 + IH2_BASE)
	229	#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
	230	#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
	231	#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
	232	#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE)
	233	#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE)
	234	#define INT_7XX_DMA_CH6 (53 + IH2_BASE)
	235	#define INT_7XX_DMA_CH7 (54 + IH2_BASE)
	236	#define INT_7XX_DMA_CH8 (55 + IH2_BASE)
	237	#define INT_7XX_DMA_CH9 (56 + IH2_BASE)
	238	#define INT_7XX_DMA_CH10 (57 + IH2_BASE)
	239	#define INT_7XX_DMA_CH11 (58 + IH2_BASE)
	240	#define INT_7XX_DMA_CH12 (59 + IH2_BASE)
	241	#define INT_7XX_DMA_CH13 (60 + IH2_BASE)
	242	#define INT_7XX_DMA_CH14 (61 + IH2_BASE)
	243	#define INT_7XX_DMA_CH15 (62 + IH2_BASE)
	244	#define INT_7XX_NAND (63 + IH2_BASE)
1da177e4	245
9ad5897c TL	246	#define INT_24XX_SYS_NIRQ 7
	247	#define INT_24XX_SDMA_IRQ0 12
	248	#define INT_24XX_SDMA_IRQ1 13
	249	#define INT_24XX_SDMA_IRQ2 14
	250	#define INT_24XX_SDMA_IRQ3 15
93bda4c0	251	#define INT_24XX_CAM_IRQ 24
9ad5897c	252	#define INT_24XX_DSS_IRQ 25
f4e4c324 TL	253	#define INT_24XX_MAIL_U0_MPU 26
	254	#define INT_24XX_DSP_UMA 27
	255	#define INT_24XX_DSP_MMU 28
9839c6b8 TL	256	#define INT_24XX_GPIO_BANK1 29
	257	#define INT_24XX_GPIO_BANK2 30
	258	#define INT_24XX_GPIO_BANK3 31
	259	#define INT_24XX_GPIO_BANK4 32
f4e4c324 TL	260	#define INT_24XX_GPIO_BANK5 33
f4e4c324 TL	261	#define INT_24XX_MAIL_U3_MPU 34
77900a2f TT	262	#define INT_24XX_GPTIMER1 37
	263	#define INT_24XX_GPTIMER2 38
	264	#define INT_24XX_GPTIMER3 39
	265	#define INT_24XX_GPTIMER4 40
	266	#define INT_24XX_GPTIMER5 41
	267	#define INT_24XX_GPTIMER6 42
	268	#define INT_24XX_GPTIMER7 43
	269	#define INT_24XX_GPTIMER8 44
	270	#define INT_24XX_GPTIMER9 45
	271	#define INT_24XX_GPTIMER10 46
	272	#define INT_24XX_GPTIMER11 47
	273	#define INT_24XX_GPTIMER12 48
646e3ed1	274	#define INT_24XX_SHA1MD5 51
a468b648 TL	275	#define INT_24XX_MCBSP4_IRQ_TX 54
a468b648 TL	276	#define INT_24XX_MCBSP4_IRQ_RX 55
85d05fb3 JN	277	#define INT_24XX_I2C1_IRQ 56
85d05fb3 JN	278	#define INT_24XX_I2C2_IRQ 57
646e3ed1	279	#define INT_24XX_HDQ_IRQ 58
120db2cb TL	280	#define INT_24XX_MCBSP1_IRQ_TX 59
	281	#define INT_24XX_MCBSP1_IRQ_RX 60
	282	#define INT_24XX_MCBSP2_IRQ_TX 62
	283	#define INT_24XX_MCBSP2_IRQ_RX 63
646e3ed1 TL	284	#define INT_24XX_SPI1_IRQ 65
646e3ed1 TL	285	#define INT_24XX_SPI2_IRQ 66
22a16f39 TL	286	#define INT_24XX_UART1_IRQ 72
22a16f39 TL	287	#define INT_24XX_UART2_IRQ 73
120db2cb	288	#define INT_24XX_UART3_IRQ 74
f4e4c324 TL	289	#define INT_24XX_USB_IRQ_GEN 75
	290	#define INT_24XX_USB_IRQ_NISO 76
	291	#define INT_24XX_USB_IRQ_ISO 77
	292	#define INT_24XX_USB_IRQ_HGEN 78
	293	#define INT_24XX_USB_IRQ_HSOF 79
	294	#define INT_24XX_USB_IRQ_OTG 80
a468b648 TL	295	#define INT_24XX_MCBSP5_IRQ_TX 81
a468b648 TL	296	#define INT_24XX_MCBSP5_IRQ_RX 82
abc45e1d	297	#define INT_24XX_MMC_IRQ 83
a468b648 TL	298	#define INT_24XX_MMC2_IRQ 86
	299	#define INT_24XX_MCBSP3_IRQ_TX 89
	300	#define INT_24XX_MCBSP3_IRQ_RX 90
	301	#define INT_24XX_SPI3_IRQ 91
	302
	303	#define INT_243X_MCBSP2_IRQ 16
	304	#define INT_243X_MCBSP3_IRQ 17
	305	#define INT_243X_MCBSP4_IRQ 18
	306	#define INT_243X_MCBSP5_IRQ 19
	307	#define INT_243X_MCBSP1_IRQ 64
	308	#define INT_243X_HS_USB_MC 92
	309	#define INT_243X_HS_USB_DMA 93
	310	#define INT_243X_CARKIT_IRQ 94
9839c6b8	311
cc26b3b0 SMK	312	#define INT_34XX_BENCH_MPU_EMUL 3
	313	#define INT_34XX_ST_MCBSP2_IRQ 4
	314	#define INT_34XX_ST_MCBSP3_IRQ 5
	315	#define INT_34XX_SSM_ABORT_IRQ 6
	316	#define INT_34XX_SYS_NIRQ 7
	317	#define INT_34XX_D2D_FW_IRQ 8
4bb194dc	318	#define INT_34XX_L3_DBG_IRQ 9
4bb194dc	319	#define INT_34XX_L3_APP_IRQ 10
cc26b3b0 SMK	320	#define INT_34XX_PRCM_MPU_IRQ 11
	321	#define INT_34XX_MCBSP1_IRQ 16
	322	#define INT_34XX_MCBSP2_IRQ 17
db97eb7d	323	#define INT_34XX_GPMC_IRQ 20
cc26b3b0 SMK	324	#define INT_34XX_MCBSP3_IRQ 22
	325	#define INT_34XX_MCBSP4_IRQ 23
	326	#define INT_34XX_CAM_IRQ 24
	327	#define INT_34XX_MCBSP5_IRQ 27
	328	#define INT_34XX_GPIO_BANK1 29
	329	#define INT_34XX_GPIO_BANK2 30
	330	#define INT_34XX_GPIO_BANK3 31
	331	#define INT_34XX_GPIO_BANK4 32
	332	#define INT_34XX_GPIO_BANK5 33
	333	#define INT_34XX_GPIO_BANK6 34
	334	#define INT_34XX_USIM_IRQ 35
	335	#define INT_34XX_WDT3_IRQ 36
	336	#define INT_34XX_SPI4_IRQ 48
	337	#define INT_34XX_SHA1MD52_IRQ 49
	338	#define INT_34XX_FPKA_READY_IRQ 50
	339	#define INT_34XX_SHA1MD51_IRQ 51
	340	#define INT_34XX_RNG_IRQ 52
	341	#define INT_34XX_I2C3_IRQ 61
	342	#define INT_34XX_FPKA_ERROR_IRQ 64
	343	#define INT_34XX_PBIAS_IRQ 75
	344	#define INT_34XX_OHCI_IRQ 76
	345	#define INT_34XX_EHCI_IRQ 77
	346	#define INT_34XX_TLL_IRQ 78
	347	#define INT_34XX_PARTHASH_IRQ 79
	348	#define INT_34XX_MMC3_IRQ 94
	349	#define INT_34XX_GPT12_IRQ 95
9839c6b8	350
046465b7 KH	351	#define INT_36XX_UART4_IRQ 80
046465b7 KH	352
91fbb8c6 VH	353	#define INT_35XX_HECC0_IRQ 24
	354	#define INT_35XX_HECC1_IRQ 28
	355	#define INT_35XX_EMAC_C0_RXTHRESH_IRQ 67
	356	#define INT_35XX_EMAC_C0_RX_PULSE_IRQ 68
	357	#define INT_35XX_EMAC_C0_TX_PULSE_IRQ 69
	358	#define INT_35XX_EMAC_C0_MISC_PULSE_IRQ 70
	359	#define INT_35XX_USBOTG_IRQ 71
4bf90f65	360	#define INT_35XX_UART4_IRQ 84
91fbb8c6 VH	361	#define INT_35XX_CCDC_VD0_IRQ 88
	362	#define INT_35XX_CCDC_VD1_IRQ 92
	363	#define INT_35XX_CCDC_VD2_IRQ 93
44169075	364
59185eee	365	/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
1da177e4 LT	366	* 16 MPUIO lines */
	367	#define OMAP_MAX_GPIO_LINES 192
	368	#define IH_GPIO_BASE (128 + IH2_BASE)
	369	#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
44f78f43 TL	370	#define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
	371
	372	/* External FPGA handles interrupts on Innovator boards */
	373	#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
	374	#ifdef CONFIG_MACH_OMAP_INNOVATOR
	375	#define OMAP_FPGA_NR_IRQS 24
	376	#else
	377	#define OMAP_FPGA_NR_IRQS 0
	378	#endif
	379	#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
	380
	381	/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
	382	#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END)
	383	#ifdef CONFIG_TWL4030_CORE
	384	#define TWL4030_BASE_NR_IRQS 8
	385	#define TWL4030_PWR_NR_IRQS 8
	386	#else
	387	#define TWL4030_BASE_NR_IRQS 0
	388	#define TWL4030_PWR_NR_IRQS 0
	389	#endif
	390	#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
	391	#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END
	392	#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
	393
	394	/* External TWL4030 gpio interrupts are optional */
	395	#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END
5c32f62b	396	#ifdef CONFIG_GPIO_TWL4030
44f78f43 TL	397	#define TWL4030_GPIO_NR_IRQS 18
	398	#else
	399	#define TWL4030_GPIO_NR_IRQS 0
	400	#endif
	401	#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
	402
e8deb28c B	403	#define TWL6030_IRQ_BASE (OMAP_FPGA_IRQ_END)
	404	#ifdef CONFIG_TWL4030_CORE
	405	#define TWL6030_BASE_NR_IRQS 20
	406	#else
	407	#define TWL6030_BASE_NR_IRQS 0
	408	#endif
	409	#define TWL6030_IRQ_END (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS)
	410
f19b2823 MLC	411	#define TWL6040_CODEC_IRQ_BASE TWL6030_IRQ_END
	412	#ifdef CONFIG_TWL6040_CODEC
	413	#define TWL6040_CODEC_NR_IRQS 6
	414	#else
	415	#define TWL6040_CODEC_NR_IRQS 0
	416	#endif
	417	#define TWL6040_CODEC_IRQ_END (TWL6040_CODEC_IRQ_BASE + TWL6040_CODEC_NR_IRQS)
	418
44f78f43	419	/* Total number of interrupts depends on the enabled blocks above */
f19b2823	420	#if (TWL4030_GPIO_IRQ_END > TWL6040_CODEC_IRQ_END)
e8deb28c B	421	#define TWL_IRQ_END TWL4030_GPIO_IRQ_END
e8deb28c B	422	#else
f19b2823	423	#define TWL_IRQ_END TWL6040_CODEC_IRQ_END
e8deb28c B	424	#endif
e8deb28c B	425
db97eb7d SG	426	/* GPMC related */
db97eb7d SG	427	#define OMAP_GPMC_IRQ_BASE (TWL_IRQ_END)
77aded2f	428	#define OMAP_GPMC_NR_IRQS 8
db97eb7d SG	429	#define OMAP_GPMC_IRQ_END (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
db97eb7d SG	430
5a3ff847 CB	431	/* PRCM IRQ handler */
	432	#ifdef CONFIG_ARCH_OMAP2PLUS
	433	#define OMAP_PRCM_IRQ_BASE (OMAP_GPMC_IRQ_END)
	434	#define OMAP_PRCM_NR_IRQS 64
	435	#define OMAP_PRCM_IRQ_END (OMAP_PRCM_IRQ_BASE + OMAP_PRCM_NR_IRQS)
	436	#else
	437	#define OMAP_PRCM_IRQ_END OMAP_GPMC_IRQ_END
	438	#endif
db97eb7d	439
5a3ff847	440	#define NR_IRQS OMAP_PRCM_IRQ_END
1da177e4	441
af973d2a TL	442	#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
af973d2a TL	443
0addd61b RN	444	#define INTCPS_NR_MIR_REGS 3
	445	#define INTCPS_NR_IRQS 96
	446
a09e64fb	447	#include <mach/hardware.h>
1da177e4	448
1c4da2b7 JK	449	#ifdef CONFIG_FIQ
	450	#define FIQ_START 1024
	451	#endif
	452
1da177e4	453	#endif