[deliverable/linux.git] / arch / arm / plat-omap / include / plat / mcbsp.h

/*
 * arch/arm/plat-omap/include/mach/mcbsp.h
 *
 * Defines for Multi-Channel Buffered Serial Port
 *
 * Copyright (C) 2002 RidgeRun, Inc.
 * Author: Steve Johnson
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 */
#ifndef __ASM_ARCH_OMAP_MCBSP_H
#define __ASM_ARCH_OMAP_MCBSP_H

#include <linux/completion.h>
#include <linux/spinlock.h>

#include <mach/hardware.h>
#include <plat/clock.h>

#define OMAP7XX_MCBSP1_BASE	0xfffb1000
#define OMAP7XX_MCBSP2_BASE	0xfffb1800

#define OMAP1510_MCBSP1_BASE	0xe1011800
#define OMAP1510_MCBSP2_BASE	0xfffb1000
#define OMAP1510_MCBSP3_BASE	0xe1017000

#define OMAP1610_MCBSP1_BASE	0xe1011800
#define OMAP1610_MCBSP2_BASE	0xfffb1000
#define OMAP1610_MCBSP3_BASE	0xe1017000

#define OMAP24XX_MCBSP1_BASE	0x48074000
#define OMAP24XX_MCBSP2_BASE	0x48076000
#define OMAP2430_MCBSP3_BASE	0x4808c000
#define OMAP2430_MCBSP4_BASE	0x4808e000
#define OMAP2430_MCBSP5_BASE	0x48096000

#define OMAP34XX_MCBSP1_BASE	0x48074000
#define OMAP34XX_MCBSP2_BASE	0x49022000
#define OMAP34XX_MCBSP2_ST_BASE	0x49028000
#define OMAP34XX_MCBSP3_BASE	0x49024000
#define OMAP34XX_MCBSP3_ST_BASE	0x4902A000
#define OMAP34XX_MCBSP3_BASE	0x49024000
#define OMAP34XX_MCBSP4_BASE	0x49026000
#define OMAP34XX_MCBSP5_BASE	0x48096000

#define OMAP44XX_MCBSP1_BASE	0x49022000
#define OMAP44XX_MCBSP2_BASE	0x49024000
#define OMAP44XX_MCBSP3_BASE	0x49026000
#define OMAP44XX_MCBSP4_BASE	0x48096000

#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)

#define OMAP_MCBSP_REG_DRR2	0x00
#define OMAP_MCBSP_REG_DRR1	0x02
#define OMAP_MCBSP_REG_DXR2	0x04
#define OMAP_MCBSP_REG_DXR1	0x06
#define OMAP_MCBSP_REG_SPCR2	0x08
#define OMAP_MCBSP_REG_SPCR1	0x0a
#define OMAP_MCBSP_REG_RCR2	0x0c
#define OMAP_MCBSP_REG_RCR1	0x0e
#define OMAP_MCBSP_REG_XCR2	0x10
#define OMAP_MCBSP_REG_XCR1	0x12
#define OMAP_MCBSP_REG_SRGR2	0x14
#define OMAP_MCBSP_REG_SRGR1	0x16
#define OMAP_MCBSP_REG_MCR2	0x18
#define OMAP_MCBSP_REG_MCR1	0x1a
#define OMAP_MCBSP_REG_RCERA	0x1c
#define OMAP_MCBSP_REG_RCERB	0x1e
#define OMAP_MCBSP_REG_XCERA	0x20
#define OMAP_MCBSP_REG_XCERB	0x22
#define OMAP_MCBSP_REG_PCR0	0x24
#define OMAP_MCBSP_REG_RCERC	0x26
#define OMAP_MCBSP_REG_RCERD	0x28
#define OMAP_MCBSP_REG_XCERC	0x2A
#define OMAP_MCBSP_REG_XCERD	0x2C
#define OMAP_MCBSP_REG_RCERE	0x2E
#define OMAP_MCBSP_REG_RCERF	0x30
#define OMAP_MCBSP_REG_XCERE	0x32
#define OMAP_MCBSP_REG_XCERF	0x34
#define OMAP_MCBSP_REG_RCERG	0x36
#define OMAP_MCBSP_REG_RCERH	0x38
#define OMAP_MCBSP_REG_XCERG	0x3A
#define OMAP_MCBSP_REG_XCERH	0x3C

/* Dummy defines, these are not available on omap1 */
#define OMAP_MCBSP_REG_XCCR	0x00
#define OMAP_MCBSP_REG_RCCR	0x00

#define AUDIO_MCBSP_DATAWRITE	(OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
#define AUDIO_MCBSP_DATAREAD	(OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)

#define AUDIO_MCBSP		OMAP_MCBSP1
#define AUDIO_DMA_TX		OMAP_DMA_MCBSP1_TX
#define AUDIO_DMA_RX		OMAP_DMA_MCBSP1_RX

#else

#define OMAP_MCBSP_REG_DRR2	0x00
#define OMAP_MCBSP_REG_DRR1	0x04
#define OMAP_MCBSP_REG_DXR2	0x08
#define OMAP_MCBSP_REG_DXR1	0x0C
#define OMAP_MCBSP_REG_DRR	0x00
#define OMAP_MCBSP_REG_DXR	0x08
#define OMAP_MCBSP_REG_SPCR2	0x10
#define OMAP_MCBSP_REG_SPCR1	0x14
#define OMAP_MCBSP_REG_RCR2	0x18
#define OMAP_MCBSP_REG_RCR1	0x1C
#define OMAP_MCBSP_REG_XCR2	0x20
#define OMAP_MCBSP_REG_XCR1	0x24
#define OMAP_MCBSP_REG_SRGR2	0x28
#define OMAP_MCBSP_REG_SRGR1	0x2C
#define OMAP_MCBSP_REG_MCR2	0x30
#define OMAP_MCBSP_REG_MCR1	0x34
#define OMAP_MCBSP_REG_RCERA	0x38
#define OMAP_MCBSP_REG_RCERB	0x3C
#define OMAP_MCBSP_REG_XCERA	0x40
#define OMAP_MCBSP_REG_XCERB	0x44
#define OMAP_MCBSP_REG_PCR0	0x48
#define OMAP_MCBSP_REG_RCERC	0x4C
#define OMAP_MCBSP_REG_RCERD	0x50
#define OMAP_MCBSP_REG_XCERC	0x54
#define OMAP_MCBSP_REG_XCERD	0x58
#define OMAP_MCBSP_REG_RCERE	0x5C
#define OMAP_MCBSP_REG_RCERF	0x60
#define OMAP_MCBSP_REG_XCERE	0x64
#define OMAP_MCBSP_REG_XCERF	0x68
#define OMAP_MCBSP_REG_RCERG	0x6C
#define OMAP_MCBSP_REG_RCERH	0x70
#define OMAP_MCBSP_REG_XCERG	0x74
#define OMAP_MCBSP_REG_XCERH	0x78
#define OMAP_MCBSP_REG_SYSCON	0x8C
#define OMAP_MCBSP_REG_THRSH2	0x90
#define OMAP_MCBSP_REG_THRSH1	0x94
#define OMAP_MCBSP_REG_IRQST	0xA0
#define OMAP_MCBSP_REG_IRQEN	0xA4
#define OMAP_MCBSP_REG_WAKEUPEN	0xA8
#define OMAP_MCBSP_REG_XCCR	0xAC
#define OMAP_MCBSP_REG_RCCR	0xB0
#define OMAP_MCBSP_REG_XBUFFSTAT	0xB4
#define OMAP_MCBSP_REG_RBUFFSTAT	0xB8
#define OMAP_MCBSP_REG_SSELCR	0xBC

#define OMAP_ST_REG_REV		0x00
#define OMAP_ST_REG_SYSCONFIG	0x10
#define OMAP_ST_REG_IRQSTATUS	0x18
#define OMAP_ST_REG_IRQENABLE	0x1C
#define OMAP_ST_REG_SGAINCR	0x24
#define OMAP_ST_REG_SFIRCR	0x28
#define OMAP_ST_REG_SSELCR	0x2C

#define AUDIO_MCBSP_DATAWRITE	(OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
#define AUDIO_MCBSP_DATAREAD	(OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)

#define AUDIO_MCBSP		OMAP_MCBSP2
#define AUDIO_DMA_TX		OMAP24XX_DMA_MCBSP2_TX
#define AUDIO_DMA_RX		OMAP24XX_DMA_MCBSP2_RX

#endif

/************************** McBSP SPCR1 bit definitions ***********************/
#define RRST			0x0001
#define RRDY			0x0002
#define RFULL			0x0004
#define RSYNC_ERR		0x0008
#define RINTM(value)		((value)<<4)	/* bits 4:5 */
#define ABIS			0x0040
#define DXENA			0x0080
#define CLKSTP(value)		((value)<<11)	/* bits 11:12 */
#define RJUST(value)		((value)<<13)	/* bits 13:14 */
#define ALB			0x8000
#define DLB			0x8000

/************************** McBSP SPCR2 bit definitions ***********************/
#define XRST		0x0001
#define XRDY		0x0002
#define XEMPTY		0x0004
#define XSYNC_ERR	0x0008
#define XINTM(value)	((value)<<4)		/* bits 4:5 */
#define GRST		0x0040
#define FRST		0x0080
#define SOFT		0x0100
#define FREE		0x0200

/************************** McBSP PCR bit definitions *************************/
#define CLKRP		0x0001
#define CLKXP		0x0002
#define FSRP		0x0004
#define FSXP		0x0008
#define DR_STAT		0x0010
#define DX_STAT		0x0020
#define CLKS_STAT	0x0040
#define SCLKME		0x0080
#define CLKRM		0x0100
#define CLKXM		0x0200
#define FSRM		0x0400
#define FSXM		0x0800
#define RIOEN		0x1000
#define XIOEN		0x2000
#define IDLE_EN		0x4000

/************************** McBSP RCR1 bit definitions ************************/
#define RWDLEN1(value)		((value)<<5)	/* Bits 5:7 */
#define RFRLEN1(value)		((value)<<8)	/* Bits 8:14 */

/************************** McBSP XCR1 bit definitions ************************/
#define XWDLEN1(value)		((value)<<5)	/* Bits 5:7 */
#define XFRLEN1(value)		((value)<<8)	/* Bits 8:14 */

/*************************** McBSP RCR2 bit definitions ***********************/
#define RDATDLY(value)		(value)		/* Bits 0:1 */
#define RFIG			0x0004
#define RCOMPAND(value)		((value)<<3)	/* Bits 3:4 */
#define RWDLEN2(value)		((value)<<5)	/* Bits 5:7 */
#define RFRLEN2(value)		((value)<<8)	/* Bits 8:14 */
#define RPHASE			0x8000

/*************************** McBSP XCR2 bit definitions ***********************/
#define XDATDLY(value)		(value)		/* Bits 0:1 */
#define XFIG			0x0004
#define XCOMPAND(value)		((value)<<3)	/* Bits 3:4 */
#define XWDLEN2(value)		((value)<<5)	/* Bits 5:7 */
#define XFRLEN2(value)		((value)<<8)	/* Bits 8:14 */
#define XPHASE			0x8000

/************************* McBSP SRGR1 bit definitions ************************/
#define CLKGDV(value)		(value)		/* Bits 0:7 */
#define FWID(value)		((value)<<8)	/* Bits 8:15 */

/************************* McBSP SRGR2 bit definitions ************************/
#define FPER(value)		(value)		/* Bits 0:11 */
#define FSGM			0x1000
#define CLKSM			0x2000
#define CLKSP			0x4000
#define GSYNC			0x8000

/************************* McBSP MCR1 bit definitions *************************/
#define RMCM			0x0001
#define RCBLK(value)		((value)<<2)	/* Bits 2:4 */
#define RPABLK(value)		((value)<<5)	/* Bits 5:6 */
#define RPBBLK(value)		((value)<<7)	/* Bits 7:8 */

/************************* McBSP MCR2 bit definitions *************************/
#define XMCM(value)		(value)		/* Bits 0:1 */
#define XCBLK(value)		((value)<<2)	/* Bits 2:4 */
#define XPABLK(value)		((value)<<5)	/* Bits 5:6 */
#define XPBBLK(value)		((value)<<7)	/* Bits 7:8 */

/*********************** McBSP XCCR bit definitions *************************/
#define EXTCLKGATE		0x8000
#define PPCONNECT		0x4000
#define DXENDLY(value)		((value)<<12)	/* Bits 12:13 */
#define XFULL_CYCLE		0x0800
#define DILB			0x0020
#define XDMAEN			0x0008
#define XDISABLE		0x0001

/********************** McBSP RCCR bit definitions *************************/
#define RFULL_CYCLE		0x0800
#define RDMAEN			0x0008
#define RDISABLE		0x0001

/********************** McBSP SYSCONFIG bit definitions ********************/
#define CLOCKACTIVITY(value)	((value)<<8)
#define SIDLEMODE(value)	((value)<<3)
#define ENAWAKEUP		0x0004
#define SOFTRST			0x0002

/********************** McBSP SSELCR bit definitions ***********************/
#define SIDETONEEN		0x0400

/********************** McBSP Sidetone SYSCONFIG bit definitions ***********/
#define ST_AUTOIDLE		0x0001

/********************** McBSP Sidetone SGAINCR bit definitions *************/
#define ST_CH1GAIN(value)	((value<<16))	/* Bits 16:31 */
#define ST_CH0GAIN(value)	(value)		/* Bits 0:15 */

/********************** McBSP Sidetone SFIRCR bit definitions **************/
#define ST_FIRCOEFF(value)	(value)		/* Bits 0:15 */

/********************** McBSP Sidetone SSELCR bit definitions **************/
#define ST_COEFFWRDONE		0x0004
#define ST_COEFFWREN		0x0002
#define ST_SIDETONEEN		0x0001

/********************** McBSP DMA operating modes **************************/
#define MCBSP_DMA_MODE_ELEMENT		0
#define MCBSP_DMA_MODE_THRESHOLD	1
#define MCBSP_DMA_MODE_FRAME		2

/********************** McBSP WAKEUPEN bit definitions *********************/
#define XEMPTYEOFEN		0x4000
#define XRDYEN			0x0400
#define XEOFEN			0x0200
#define XFSXEN			0x0100
#define XSYNCERREN		0x0080
#define RRDYEN			0x0008
#define REOFEN			0x0004
#define RFSREN			0x0002
#define RSYNCERREN		0x0001

/* we don't do multichannel for now */
struct omap_mcbsp_reg_cfg {
	u16 spcr2;
	u16 spcr1;
	u16 rcr2;
	u16 rcr1;
	u16 xcr2;
	u16 xcr1;
	u16 srgr2;
	u16 srgr1;
	u16 mcr2;
	u16 mcr1;
	u16 pcr0;
	u16 rcerc;
	u16 rcerd;
	u16 xcerc;
	u16 xcerd;
	u16 rcere;
	u16 rcerf;
	u16 xcere;
	u16 xcerf;
	u16 rcerg;
	u16 rcerh;
	u16 xcerg;
	u16 xcerh;
	u16 xccr;
	u16 rccr;
};

typedef enum {
	OMAP_MCBSP1 = 0,
	OMAP_MCBSP2,
	OMAP_MCBSP3,
	OMAP_MCBSP4,
	OMAP_MCBSP5
} omap_mcbsp_id;

typedef int __bitwise omap_mcbsp_io_type_t;
#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)

typedef enum {
	OMAP_MCBSP_WORD_8 = 0,
	OMAP_MCBSP_WORD_12,
	OMAP_MCBSP_WORD_16,
	OMAP_MCBSP_WORD_20,
	OMAP_MCBSP_WORD_24,
	OMAP_MCBSP_WORD_32,
} omap_mcbsp_word_length;

typedef enum {
	OMAP_MCBSP_CLK_RISING = 0,
	OMAP_MCBSP_CLK_FALLING,
} omap_mcbsp_clk_polarity;

typedef enum {
	OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
	OMAP_MCBSP_FS_ACTIVE_LOW,
} omap_mcbsp_fs_polarity;

typedef enum {
	OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
	OMAP_MCBSP_CLK_STP_MODE_DELAY,
} omap_mcbsp_clk_stp_mode;


/******* SPI specific mode **********/
typedef enum {
	OMAP_MCBSP_SPI_MASTER = 0,
	OMAP_MCBSP_SPI_SLAVE,
} omap_mcbsp_spi_mode;

struct omap_mcbsp_spi_cfg {
	omap_mcbsp_spi_mode		spi_mode;
	omap_mcbsp_clk_polarity		rx_clock_polarity;
	omap_mcbsp_clk_polarity		tx_clock_polarity;
	omap_mcbsp_fs_polarity		fsx_polarity;
	u8				clk_div;
	omap_mcbsp_clk_stp_mode		clk_stp_mode;
	omap_mcbsp_word_length		word_length;
};

/* Platform specific configuration */
struct omap_mcbsp_ops {
	void (*request)(unsigned int);
	void (*free)(unsigned int);
};

struct omap_mcbsp_platform_data {
	unsigned long phys_base;
	u8 dma_rx_sync, dma_tx_sync;
	u16 rx_irq, tx_irq;
	struct omap_mcbsp_ops *ops;
#ifdef CONFIG_ARCH_OMAP3
	/* Sidetone block for McBSP 2 and 3 */
	unsigned long phys_base_st;
	u16 buffer_size;
#endif
};

struct omap_mcbsp_st_data {
	void __iomem *io_base_st;
	bool running;
	bool enabled;
	s16 taps[128];	/* Sidetone filter coefficients */
	int nr_taps;	/* Number of filter coefficients in use */
	s16 ch0gain;
	s16 ch1gain;
};

struct omap_mcbsp {
	struct device *dev;
	unsigned long phys_base;
	void __iomem *io_base;
	u8 id;
	u8 free;
	omap_mcbsp_word_length rx_word_length;
	omap_mcbsp_word_length tx_word_length;

	omap_mcbsp_io_type_t io_type; /* IRQ or poll */
	/* IRQ based TX/RX */
	int rx_irq;
	int tx_irq;

	/* DMA stuff */
	u8 dma_rx_sync;
	short dma_rx_lch;
	u8 dma_tx_sync;
	short dma_tx_lch;

	/* Completion queues */
	struct completion tx_irq_completion;
	struct completion rx_irq_completion;
	struct completion tx_dma_completion;
	struct completion rx_dma_completion;

	/* Protect the field .free, while checking if the mcbsp is in use */
	spinlock_t lock;
	struct omap_mcbsp_platform_data *pdata;
	struct clk *iclk;
	struct clk *fclk;
#ifdef CONFIG_ARCH_OMAP3
	struct omap_mcbsp_st_data *st_data;
	int dma_op_mode;
	u16 max_tx_thres;
	u16 max_rx_thres;
#endif
	void *reg_cache;
};
extern struct omap_mcbsp **mcbsp_ptr;
extern int omap_mcbsp_count, omap_mcbsp_cache_size;

int omap_mcbsp_init(void);
void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
					int size);
void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
#ifdef CONFIG_ARCH_OMAP3
void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
u16 omap_mcbsp_get_fifo_size(unsigned int id);
u16 omap_mcbsp_get_tx_delay(unsigned int id);
u16 omap_mcbsp_get_rx_delay(unsigned int id);
int omap_mcbsp_get_dma_op_mode(unsigned int id);
#else
static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
{ }
static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
{ }
static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
static inline u16 omap_mcbsp_get_fifo_size(unsigned int id) { return 0; }
static inline u16 omap_mcbsp_get_tx_delay(unsigned int id) { return 0; }
static inline u16 omap_mcbsp_get_rx_delay(unsigned int id) { return 0; }
static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
#endif
int omap_mcbsp_request(unsigned int id);
void omap_mcbsp_free(unsigned int id);
void omap_mcbsp_start(unsigned int id, int tx, int rx);
void omap_mcbsp_stop(unsigned int id, int tx, int rx);
void omap_mcbsp_xmit_word(unsigned int id, u32 word);
u32 omap_mcbsp_recv_word(unsigned int id);

int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);


/* SPI specific API */
void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);

/* Polled read/write functions */
int omap_mcbsp_pollread(unsigned int id, u16 * buf);
int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);

#ifdef CONFIG_ARCH_OMAP3
/* Sidetone specific API */
int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
int omap_st_enable(unsigned int id);
int omap_st_disable(unsigned int id);
int omap_st_is_enabled(unsigned int id);
#else
static inline int omap_st_set_chgain(unsigned int id, int channel,
				     s16 chgain) { return 0; }
static inline int omap_st_get_chgain(unsigned int id, int channel,
				     s16 *chgain) { return 0; }
static inline int omap_st_enable(unsigned int id) { return 0; }
static inline int omap_st_disable(unsigned int id) { return 0; }
static inline int omap_st_is_enabled(unsigned int id) {  return 0; }
#endif

#endif
Commit	Line	Data
1da177e4	1	/*
a09e64fb	2	* arch/arm/plat-omap/include/mach/mcbsp.h
1da177e4 LT	3	*
	4	* Defines for Multi-Channel Buffered Serial Port
	5	*
	6	* Copyright (C) 2002 RidgeRun, Inc.
	7	* Author: Steve Johnson
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	*/
	24	#ifndef __ASM_ARCH_OMAP_MCBSP_H
	25	#define __ASM_ARCH_OMAP_MCBSP_H
	26
bc5d0c89 EV	27	#include <linux/completion.h>
	28	#include <linux/spinlock.h>
	29
a09e64fb	30	#include <mach/hardware.h>
ce491cf8	31	#include <plat/clock.h>
1da177e4	32
7c006926 AB	33	#define OMAP7XX_MCBSP1_BASE 0xfffb1000
7c006926 AB	34	#define OMAP7XX_MCBSP2_BASE 0xfffb1800
1da177e4 LT	35
	36	#define OMAP1510_MCBSP1_BASE 0xe1011800
	37	#define OMAP1510_MCBSP2_BASE 0xfffb1000
	38	#define OMAP1510_MCBSP3_BASE 0xe1017000
	39
	40	#define OMAP1610_MCBSP1_BASE 0xe1011800
	41	#define OMAP1610_MCBSP2_BASE 0xfffb1000
	42	#define OMAP1610_MCBSP3_BASE 0xe1017000
	43
120db2cb TL	44	#define OMAP24XX_MCBSP1_BASE 0x48074000
120db2cb TL	45	#define OMAP24XX_MCBSP2_BASE 0x48076000
05228c35 JN	46	#define OMAP2430_MCBSP3_BASE 0x4808c000
	47	#define OMAP2430_MCBSP4_BASE 0x4808e000
	48	#define OMAP2430_MCBSP5_BASE 0x48096000
120db2cb	49
bc5d0c89 EV	50	#define OMAP34XX_MCBSP1_BASE 0x48074000
bc5d0c89 EV	51	#define OMAP34XX_MCBSP2_BASE 0x49022000
d912fa92 EN	52	#define OMAP34XX_MCBSP2_ST_BASE 0x49028000
	53	#define OMAP34XX_MCBSP3_BASE 0x49024000
	54	#define OMAP34XX_MCBSP3_ST_BASE 0x4902A000
9c8e3a0f CS	55	#define OMAP34XX_MCBSP3_BASE 0x49024000
	56	#define OMAP34XX_MCBSP4_BASE 0x49026000
	57	#define OMAP34XX_MCBSP5_BASE 0x48096000
bc5d0c89	58
a5b92cc3 SR	59	#define OMAP44XX_MCBSP1_BASE 0x49022000
	60	#define OMAP44XX_MCBSP2_BASE 0x49024000
	61	#define OMAP44XX_MCBSP3_BASE 0x49026000
aee44c30	62	#define OMAP44XX_MCBSP4_BASE 0x48096000
a5b92cc3	63
bf1cb7eb	64	#if defined(CONFIG_ARCH_OMAP15XX) \|\| defined(CONFIG_ARCH_OMAP16XX) \|\| defined(CONFIG_ARCH_OMAP730) \|\| defined(CONFIG_ARCH_OMAP850)
120db2cb	65
1da177e4 LT	66	#define OMAP_MCBSP_REG_DRR2 0x00
	67	#define OMAP_MCBSP_REG_DRR1 0x02
	68	#define OMAP_MCBSP_REG_DXR2 0x04
	69	#define OMAP_MCBSP_REG_DXR1 0x06
	70	#define OMAP_MCBSP_REG_SPCR2 0x08
	71	#define OMAP_MCBSP_REG_SPCR1 0x0a
	72	#define OMAP_MCBSP_REG_RCR2 0x0c
	73	#define OMAP_MCBSP_REG_RCR1 0x0e
	74	#define OMAP_MCBSP_REG_XCR2 0x10
	75	#define OMAP_MCBSP_REG_XCR1 0x12
	76	#define OMAP_MCBSP_REG_SRGR2 0x14
	77	#define OMAP_MCBSP_REG_SRGR1 0x16
	78	#define OMAP_MCBSP_REG_MCR2 0x18
	79	#define OMAP_MCBSP_REG_MCR1 0x1a
	80	#define OMAP_MCBSP_REG_RCERA 0x1c
	81	#define OMAP_MCBSP_REG_RCERB 0x1e
	82	#define OMAP_MCBSP_REG_XCERA 0x20
	83	#define OMAP_MCBSP_REG_XCERB 0x22
	84	#define OMAP_MCBSP_REG_PCR0 0x24
	85	#define OMAP_MCBSP_REG_RCERC 0x26
	86	#define OMAP_MCBSP_REG_RCERD 0x28
	87	#define OMAP_MCBSP_REG_XCERC 0x2A
	88	#define OMAP_MCBSP_REG_XCERD 0x2C
	89	#define OMAP_MCBSP_REG_RCERE 0x2E
	90	#define OMAP_MCBSP_REG_RCERF 0x30
	91	#define OMAP_MCBSP_REG_XCERE 0x32
	92	#define OMAP_MCBSP_REG_XCERF 0x34
	93	#define OMAP_MCBSP_REG_RCERG 0x36
	94	#define OMAP_MCBSP_REG_RCERH 0x38
	95	#define OMAP_MCBSP_REG_XCERG 0x3A
	96	#define OMAP_MCBSP_REG_XCERH 0x3C
	97
3127f8f8 TL	98	/* Dummy defines, these are not available on omap1 */
	99	#define OMAP_MCBSP_REG_XCCR 0x00
	100	#define OMAP_MCBSP_REG_RCCR 0x00
	101
120db2cb TL	102	#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
	103	#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
	104
	105	#define AUDIO_MCBSP OMAP_MCBSP1
	106	#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
	107	#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
	108
140455fa	109	#else
120db2cb TL	110
	111	#define OMAP_MCBSP_REG_DRR2 0x00
	112	#define OMAP_MCBSP_REG_DRR1 0x04
	113	#define OMAP_MCBSP_REG_DXR2 0x08
	114	#define OMAP_MCBSP_REG_DXR1 0x0C
b4b58f58 CS	115	#define OMAP_MCBSP_REG_DRR 0x00
b4b58f58 CS	116	#define OMAP_MCBSP_REG_DXR 0x08
120db2cb TL	117	#define OMAP_MCBSP_REG_SPCR2 0x10
	118	#define OMAP_MCBSP_REG_SPCR1 0x14
	119	#define OMAP_MCBSP_REG_RCR2 0x18
	120	#define OMAP_MCBSP_REG_RCR1 0x1C
	121	#define OMAP_MCBSP_REG_XCR2 0x20
	122	#define OMAP_MCBSP_REG_XCR1 0x24
	123	#define OMAP_MCBSP_REG_SRGR2 0x28
	124	#define OMAP_MCBSP_REG_SRGR1 0x2C
	125	#define OMAP_MCBSP_REG_MCR2 0x30
	126	#define OMAP_MCBSP_REG_MCR1 0x34
	127	#define OMAP_MCBSP_REG_RCERA 0x38
	128	#define OMAP_MCBSP_REG_RCERB 0x3C
	129	#define OMAP_MCBSP_REG_XCERA 0x40
	130	#define OMAP_MCBSP_REG_XCERB 0x44
	131	#define OMAP_MCBSP_REG_PCR0 0x48
	132	#define OMAP_MCBSP_REG_RCERC 0x4C
	133	#define OMAP_MCBSP_REG_RCERD 0x50
	134	#define OMAP_MCBSP_REG_XCERC 0x54
	135	#define OMAP_MCBSP_REG_XCERD 0x58
	136	#define OMAP_MCBSP_REG_RCERE 0x5C
	137	#define OMAP_MCBSP_REG_RCERF 0x60
	138	#define OMAP_MCBSP_REG_XCERE 0x64
	139	#define OMAP_MCBSP_REG_XCERF 0x68
	140	#define OMAP_MCBSP_REG_RCERG 0x6C
	141	#define OMAP_MCBSP_REG_RCERH 0x70
	142	#define OMAP_MCBSP_REG_XCERG 0x74
	143	#define OMAP_MCBSP_REG_XCERH 0x78
b4b58f58	144	#define OMAP_MCBSP_REG_SYSCON 0x8C
946a49a9 EV	145	#define OMAP_MCBSP_REG_THRSH2 0x90
	146	#define OMAP_MCBSP_REG_THRSH1 0x94
	147	#define OMAP_MCBSP_REG_IRQST 0xA0
	148	#define OMAP_MCBSP_REG_IRQEN 0xA4
2122fdc6	149	#define OMAP_MCBSP_REG_WAKEUPEN 0xA8
b4b58f58 CS	150	#define OMAP_MCBSP_REG_XCCR 0xAC
b4b58f58 CS	151	#define OMAP_MCBSP_REG_RCCR 0xB0
7dc976ed PU	152	#define OMAP_MCBSP_REG_XBUFFSTAT 0xB4
7dc976ed PU	153	#define OMAP_MCBSP_REG_RBUFFSTAT 0xB8
d912fa92 EN	154	#define OMAP_MCBSP_REG_SSELCR 0xBC
	155
	156	#define OMAP_ST_REG_REV 0x00
	157	#define OMAP_ST_REG_SYSCONFIG 0x10
	158	#define OMAP_ST_REG_IRQSTATUS 0x18
	159	#define OMAP_ST_REG_IRQENABLE 0x1C
	160	#define OMAP_ST_REG_SGAINCR 0x24
	161	#define OMAP_ST_REG_SFIRCR 0x28
	162	#define OMAP_ST_REG_SSELCR 0x2C
120db2cb TL	163
	164	#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
	165	#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
	166
	167	#define AUDIO_MCBSP OMAP_MCBSP2
	168	#define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX
	169	#define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX
	170
	171	#endif
	172
1da177e4 LT	173	/************************ McBSP SPCR1 bit definitions *********************/
	174	#define RRST 0x0001
	175	#define RRDY 0x0002
	176	#define RFULL 0x0004
	177	#define RSYNC_ERR 0x0008
	178	#define RINTM(value) ((value)<<4) /* bits 4:5 */
	179	#define ABIS 0x0040
	180	#define DXENA 0x0080
	181	#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
	182	#define RJUST(value) ((value)<<13) /* bits 13:14 */
b4b58f58	183	#define ALB 0x8000
1da177e4 LT	184	#define DLB 0x8000
	185
	186	/************************ McBSP SPCR2 bit definitions *********************/
	187	#define XRST 0x0001
	188	#define XRDY 0x0002
	189	#define XEMPTY 0x0004
	190	#define XSYNC_ERR 0x0008
	191	#define XINTM(value) ((value)<<4) /* bits 4:5 */
	192	#define GRST 0x0040
	193	#define FRST 0x0080
	194	#define SOFT 0x0100
	195	#define FREE 0x0200
	196
	197	/************************ McBSP PCR bit definitions ***********************/
	198	#define CLKRP 0x0001
	199	#define CLKXP 0x0002
	200	#define FSRP 0x0004
	201	#define FSXP 0x0008
	202	#define DR_STAT 0x0010
	203	#define DX_STAT 0x0020
	204	#define CLKS_STAT 0x0040
	205	#define SCLKME 0x0080
	206	#define CLKRM 0x0100
	207	#define CLKXM 0x0200
	208	#define FSRM 0x0400
	209	#define FSXM 0x0800
	210	#define RIOEN 0x1000
	211	#define XIOEN 0x2000
	212	#define IDLE_EN 0x4000
	213
	214	/************************ McBSP RCR1 bit definitions **********************/
	215	#define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
	216	#define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
	217
	218	/************************ McBSP XCR1 bit definitions **********************/
	219	#define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
	220	#define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
	221
	222	/************************* McBSP RCR2 bit definitions *********************/
	223	#define RDATDLY(value) (value) /* Bits 0:1 */
	224	#define RFIG 0x0004
	225	#define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
	226	#define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
	227	#define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
	228	#define RPHASE 0x8000
	229
	230	/************************* McBSP XCR2 bit definitions *********************/
	231	#define XDATDLY(value) (value) /* Bits 0:1 */
	232	#define XFIG 0x0004
	233	#define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
	234	#define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
	235	#define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
	236	#define XPHASE 0x8000
	237
	238	/*********************** McBSP SRGR1 bit definitions **********************/
	239	#define CLKGDV(value) (value) /* Bits 0:7 */
	240	#define FWID(value) ((value)<<8) /* Bits 8:15 */
	241
	242	/*********************** McBSP SRGR2 bit definitions **********************/
	243	#define FPER(value) (value) /* Bits 0:11 */
	244	#define FSGM 0x1000
	245	#define CLKSM 0x2000
	246	#define CLKSP 0x4000
	247	#define GSYNC 0x8000
248
249	/*********************** McBSP MCR1 bit definitions ***********************/
250	#define RMCM 0x0001
251	#define RCBLK(value) ((value)<<2) /* Bits 2:4 */
252	#define RPABLK(value) ((value)<<5) /* Bits 5:6 */
253	#define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
254
255	/*********************** McBSP MCR2 bit definitions ***********************/
256	#define XMCM(value) (value) /* Bits 0:1 */
257	#define XCBLK(value) ((value)<<2) /* Bits 2:4 */
258	#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
259	#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
260
b4b58f58	261	/********************* McBSP XCCR bit definitions ***********************/
3127f8f8 TL	262	#define EXTCLKGATE 0x8000
	263	#define PPCONNECT 0x4000
	264	#define DXENDLY(value) ((value)<<12) /* Bits 12:13 */
	265	#define XFULL_CYCLE 0x0800
b4b58f58 CS	266	#define DILB 0x0020
	267	#define XDMAEN 0x0008
	268	#define XDISABLE 0x0001
	269
	270	/******************** McBSP RCCR bit definitions ***********************/
3127f8f8	271	#define RFULL_CYCLE 0x0800
b4b58f58 CS	272	#define RDMAEN 0x0008
	273	#define RDISABLE 0x0001
	274
	275	/******************** McBSP SYSCONFIG bit definitions ******************/
2ba93f8f	276	#define CLOCKACTIVITY(value) ((value)<<8)
2122fdc6 EN	277	#define SIDLEMODE(value) ((value)<<3)
2122fdc6 EN	278	#define ENAWAKEUP 0x0004
b4b58f58	279	#define SOFTRST 0x0002
1da177e4	280
d912fa92 EN	281	/******************** McBSP SSELCR bit definitions *********************/
	282	#define SIDETONEEN 0x0400
	283
	284	/******************** McBSP Sidetone SYSCONFIG bit definitions *********/
	285	#define ST_AUTOIDLE 0x0001
	286
	287	/******************** McBSP Sidetone SGAINCR bit definitions ***********/
	288	#define ST_CH1GAIN(value) ((value<<16)) /* Bits 16:31 */
	289	#define ST_CH0GAIN(value) (value) /* Bits 0:15 */
	290
	291	/******************** McBSP Sidetone SFIRCR bit definitions ************/
	292	#define ST_FIRCOEFF(value) (value) /* Bits 0:15 */
	293
	294	/******************** McBSP Sidetone SSELCR bit definitions ************/
	295	#define ST_COEFFWRDONE 0x0004
	296	#define ST_COEFFWREN 0x0002
	297	#define ST_SIDETONEEN 0x0001
	298
98cb20e8 PU	299	/******************** McBSP DMA operating modes ************************/
	300	#define MCBSP_DMA_MODE_ELEMENT 0
	301	#define MCBSP_DMA_MODE_THRESHOLD 1
	302	#define MCBSP_DMA_MODE_FRAME 2
	303
2122fdc6 EN	304	/******************** McBSP WAKEUPEN bit definitions *******************/
	305	#define XEMPTYEOFEN 0x4000
	306	#define XRDYEN 0x0400
	307	#define XEOFEN 0x0200
	308	#define XFSXEN 0x0100
	309	#define XSYNCERREN 0x0080
	310	#define RRDYEN 0x0008
	311	#define REOFEN 0x0004
	312	#define RFSREN 0x0002
	313	#define RSYNCERREN 0x0001
2122fdc6	314
1da177e4 LT	315	/* we don't do multichannel for now */
	316	struct omap_mcbsp_reg_cfg {
	317	u16 spcr2;
	318	u16 spcr1;
	319	u16 rcr2;
	320	u16 rcr1;
	321	u16 xcr2;
	322	u16 xcr1;
	323	u16 srgr2;
	324	u16 srgr1;
	325	u16 mcr2;
	326	u16 mcr1;
	327	u16 pcr0;
	328	u16 rcerc;
	329	u16 rcerd;
	330	u16 xcerc;
	331	u16 xcerd;
	332	u16 rcere;
	333	u16 rcerf;
	334	u16 xcere;
	335	u16 xcerf;
	336	u16 rcerg;
	337	u16 rcerh;
	338	u16 xcerg;
	339	u16 xcerh;
3127f8f8 TL	340	u16 xccr;
3127f8f8 TL	341	u16 rccr;
1da177e4 LT	342	};
	343
	344	typedef enum {
	345	OMAP_MCBSP1 = 0,
	346	OMAP_MCBSP2,
	347	OMAP_MCBSP3,
9c8e3a0f CS	348	OMAP_MCBSP4,
9c8e3a0f CS	349	OMAP_MCBSP5
1da177e4 LT	350	} omap_mcbsp_id;
1da177e4 LT	351
120db2cb TL	352	typedef int __bitwise omap_mcbsp_io_type_t;
	353	#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
	354	#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
	355
1da177e4 LT	356	typedef enum {
	357	OMAP_MCBSP_WORD_8 = 0,
	358	OMAP_MCBSP_WORD_12,
	359	OMAP_MCBSP_WORD_16,
	360	OMAP_MCBSP_WORD_20,
	361	OMAP_MCBSP_WORD_24,
	362	OMAP_MCBSP_WORD_32,
	363	} omap_mcbsp_word_length;
	364
	365	typedef enum {
	366	OMAP_MCBSP_CLK_RISING = 0,
	367	OMAP_MCBSP_CLK_FALLING,
	368	} omap_mcbsp_clk_polarity;
	369
	370	typedef enum {
	371	OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
	372	OMAP_MCBSP_FS_ACTIVE_LOW,
	373	} omap_mcbsp_fs_polarity;
	374
	375	typedef enum {
	376	OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
	377	OMAP_MCBSP_CLK_STP_MODE_DELAY,
	378	} omap_mcbsp_clk_stp_mode;
	379
	380
	381	/***** SPI specific mode ********/
	382	typedef enum {
	383	OMAP_MCBSP_SPI_MASTER = 0,
	384	OMAP_MCBSP_SPI_SLAVE,
	385	} omap_mcbsp_spi_mode;
	386
	387	struct omap_mcbsp_spi_cfg {
	388	omap_mcbsp_spi_mode spi_mode;
	389	omap_mcbsp_clk_polarity rx_clock_polarity;
	390	omap_mcbsp_clk_polarity tx_clock_polarity;
	391	omap_mcbsp_fs_polarity fsx_polarity;
	392	u8 clk_div;
	393	omap_mcbsp_clk_stp_mode clk_stp_mode;
	394	omap_mcbsp_word_length word_length;
	395	};
	396
bc5d0c89 EV	397	/* Platform specific configuration */
	398	struct omap_mcbsp_ops {
	399	void (*request)(unsigned int);
	400	void (*free)(unsigned int);
bc5d0c89 EV	401	};
	402
	403	struct omap_mcbsp_platform_data {
65846909	404	unsigned long phys_base;
bc5d0c89 EV	405	u8 dma_rx_sync, dma_tx_sync;
	406	u16 rx_irq, tx_irq;
	407	struct omap_mcbsp_ops *ops;
a8eb7ca0	408	#ifdef CONFIG_ARCH_OMAP3
d912fa92 EN	409	/* Sidetone block for McBSP 2 and 3 */
d912fa92 EN	410	unsigned long phys_base_st;
a1a56f5f EV	411	u16 buffer_size;
a1a56f5f EV	412	#endif
bc5d0c89 EV	413	};
bc5d0c89 EV	414
d912fa92 EN	415	struct omap_mcbsp_st_data {
	416	void __iomem *io_base_st;
	417	bool running;
	418	bool enabled;
	419	s16 taps[128]; /* Sidetone filter coefficients */
	420	int nr_taps; /* Number of filter coefficients in use */
	421	s16 ch0gain;
	422	s16 ch1gain;
	423	};
	424
bc5d0c89 EV	425	struct omap_mcbsp {
bc5d0c89 EV	426	struct device *dev;
65846909	427	unsigned long phys_base;
d592dd1a	428	void __iomem *io_base;
bc5d0c89 EV	429	u8 id;
	430	u8 free;
	431	omap_mcbsp_word_length rx_word_length;
	432	omap_mcbsp_word_length tx_word_length;
	433
	434	omap_mcbsp_io_type_t io_type; /* IRQ or poll */
	435	/* IRQ based TX/RX */
	436	int rx_irq;
	437	int tx_irq;
	438
	439	/* DMA stuff */
	440	u8 dma_rx_sync;
	441	short dma_rx_lch;
	442	u8 dma_tx_sync;
	443	short dma_tx_lch;
	444
	445	/* Completion queues */
	446	struct completion tx_irq_completion;
	447	struct completion rx_irq_completion;
	448	struct completion tx_dma_completion;
	449	struct completion rx_dma_completion;
	450
	451	/* Protect the field .free, while checking if the mcbsp is in use */
	452	spinlock_t lock;
	453	struct omap_mcbsp_platform_data *pdata;
b820ce4e RK	454	struct clk *iclk;
b820ce4e RK	455	struct clk *fclk;
a8eb7ca0	456	#ifdef CONFIG_ARCH_OMAP3
d912fa92	457	struct omap_mcbsp_st_data *st_data;
98cb20e8	458	int dma_op_mode;
a1a56f5f EV	459	u16 max_tx_thres;
	460	u16 max_rx_thres;
	461	#endif
c8c99699	462	void *reg_cache;
bc5d0c89	463	};
b4b58f58	464	extern struct omap_mcbsp **mcbsp_ptr;
c8c99699	465	extern int omap_mcbsp_count, omap_mcbsp_cache_size;
bc5d0c89 EV	466
	467	int omap_mcbsp_init(void);
	468	void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
	469	int size);
1da177e4	470	void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
a8eb7ca0	471	#ifdef CONFIG_ARCH_OMAP3
7aa9ff56 EV	472	void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
7aa9ff56 EV	473	void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
a1a56f5f EV	474	u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
a1a56f5f EV	475	u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
0acce82b	476	u16 omap_mcbsp_get_fifo_size(unsigned int id);
7dc976ed PU	477	u16 omap_mcbsp_get_tx_delay(unsigned int id);
7dc976ed PU	478	u16 omap_mcbsp_get_rx_delay(unsigned int id);
98cb20e8	479	int omap_mcbsp_get_dma_op_mode(unsigned int id);
7aa9ff56 EV	480	#else
	481	static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
	482	{ }
	483	static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
	484	{ }
a1a56f5f EV	485	static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
a1a56f5f EV	486	static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
0acce82b	487	static inline u16 omap_mcbsp_get_fifo_size(unsigned int id) { return 0; }
7dc976ed PU	488	static inline u16 omap_mcbsp_get_tx_delay(unsigned int id) { return 0; }
7dc976ed PU	489	static inline u16 omap_mcbsp_get_rx_delay(unsigned int id) { return 0; }
98cb20e8	490	static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
7aa9ff56	491	#endif
1da177e4 LT	492	int omap_mcbsp_request(unsigned int id);
1da177e4 LT	493	void omap_mcbsp_free(unsigned int id);
c12abc01 JN	494	void omap_mcbsp_start(unsigned int id, int tx, int rx);
c12abc01 JN	495	void omap_mcbsp_stop(unsigned int id, int tx, int rx);
1da177e4 LT	496	void omap_mcbsp_xmit_word(unsigned int id, u32 word);
	497	u32 omap_mcbsp_recv_word(unsigned int id);
	498
	499	int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
	500	int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
120db2cb TL	501	int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
	502	int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
	503
1da177e4 LT	504
	505	/* SPI specific API */
	506	void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
	507
	508	/* Polled read/write functions */
	509	int omap_mcbsp_pollread(unsigned int id, u16 * buf);
	510	int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
b4b58f58	511	int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
1da177e4	512
d912fa92 EN	513	#ifdef CONFIG_ARCH_OMAP3
	514	/* Sidetone specific API */
	515	int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
	516	int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
	517	int omap_st_enable(unsigned int id);
	518	int omap_st_disable(unsigned int id);
	519	int omap_st_is_enabled(unsigned int id);
	520	#else
	521	static inline int omap_st_set_chgain(unsigned int id, int channel,
	522	s16 chgain) { return 0; }
	523	static inline int omap_st_get_chgain(unsigned int id, int channel,
	524	s16 *chgain) { return 0; }
	525	static inline int omap_st_enable(unsigned int id) { return 0; }
	526	static inline int omap_st_disable(unsigned int id) { return 0; }
	527	static inline int omap_st_is_enabled(unsigned int id) { return 0; }
	528	#endif
	529
1da177e4	530	#endif