OMAP: PM constraints: add return values; add requesting device param to omap_pm_set_m...
[deliverable/linux.git] / arch / arm / plat-omap / include / plat / omap-pm.h
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1/*
2 * omap-pm.h - OMAP power management interface
3 *
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4 * Copyright (C) 2008-2010 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation
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6 * Paul Walmsley
7 *
8 * Interface developed by (in alphabetical order): Karthik Dasu, Jouni
9 * Högander, Tony Lindgren, Rajendra Nayak, Sakari Poussa,
10 * Veeramanikandan Raju, Anand Sawant, Igor Stoppa, Paul Walmsley,
11 * Richard Woodruff
12 */
13
14#ifndef ASM_ARM_ARCH_OMAP_OMAP_PM_H
15#define ASM_ARM_ARCH_OMAP_OMAP_PM_H
16
17#include <linux/device.h>
18#include <linux/cpufreq.h>
19
20#include "powerdomain.h"
21
22/**
23 * struct omap_opp - clock frequency-to-OPP ID table for DSP, MPU
24 * @rate: target clock rate
25 * @opp_id: OPP ID
26 * @min_vdd: minimum VDD1 voltage (in millivolts) for this OPP
27 *
28 * Operating performance point data. Can vary by OMAP chip and board.
29 */
30struct omap_opp {
31 unsigned long rate;
32 u8 opp_id;
33 u16 min_vdd;
34};
35
36extern struct omap_opp *mpu_opps;
37extern struct omap_opp *dsp_opps;
38extern struct omap_opp *l3_opps;
39
40/*
41 * agent_id values for use with omap_pm_set_min_bus_tput():
42 *
43 * OCP_INITIATOR_AGENT is only valid for devices that can act as
44 * initiators -- it represents the device's L3 interconnect
45 * connection. OCP_TARGET_AGENT represents the device's L4
46 * interconnect connection.
47 */
48#define OCP_TARGET_AGENT 1
49#define OCP_INITIATOR_AGENT 2
50
51/**
52 * omap_pm_if_early_init - OMAP PM init code called before clock fw init
53 * @mpu_opp_table: array ptr to struct omap_opp for MPU
54 * @dsp_opp_table: array ptr to struct omap_opp for DSP
55 * @l3_opp_table : array ptr to struct omap_opp for CORE
56 *
57 * Initialize anything that must be configured before the clock
58 * framework starts. The "_if_" is to avoid name collisions with the
59 * PM idle-loop code.
60 */
61int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
62 struct omap_opp *dsp_opp_table,
63 struct omap_opp *l3_opp_table);
64
65/**
66 * omap_pm_if_init - OMAP PM init code called after clock fw init
67 *
68 * The main initialization code. OPP tables are passed in here. The
69 * "_if_" is to avoid name collisions with the PM idle-loop code.
70 */
71int __init omap_pm_if_init(void);
72
73/**
74 * omap_pm_if_exit - OMAP PM exit code
75 *
76 * Exit code; currently unused. The "_if_" is to avoid name
77 * collisions with the PM idle-loop code.
78 */
79void omap_pm_if_exit(void);
80
81/*
82 * Device-driver-originated constraints (via board-*.c files, platform_data)
83 */
84
85
86/**
87 * omap_pm_set_max_mpu_wakeup_lat - set the maximum MPU wakeup latency
88 * @dev: struct device * requesting the constraint
89 * @t: maximum MPU wakeup latency in microseconds
90 *
91 * Request that the maximum interrupt latency for the MPU to be no
564889c1 92 * greater than @t microseconds. "Interrupt latency" in this case is
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93 * defined as the elapsed time from the occurrence of a hardware or
94 * timer interrupt to the time when the device driver's interrupt
95 * service routine has been entered by the MPU.
96 *
97 * It is intended that underlying PM code will use this information to
98 * determine what power state to put the MPU powerdomain into, and
99 * possibly the CORE powerdomain as well, since interrupt handling
100 * code currently runs from SDRAM. Advanced PM or board*.c code may
101 * also configure interrupt controller priorities, OCP bus priorities,
102 * CPU speed(s), etc.
103 *
104 * This function will not affect device wakeup latency, e.g., time
105 * elapsed from when a device driver enables a hardware device with
106 * clk_enable(), to when the device is ready for register access or
107 * other use. To control this device wakeup latency, use
564889c1 108 * omap_pm_set_max_dev_wakeup_lat()
c0407a96 109 *
564889c1 110 * Multiple calls to omap_pm_set_max_mpu_wakeup_lat() will replace the
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111 * previous t value. To remove the latency target for the MPU, call
112 * with t = -1.
113 *
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114 * XXX This constraint will be deprecated soon in favor of the more
115 * general omap_pm_set_max_dev_wakeup_lat()
116 *
117 * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
118 * is not satisfiable, or 0 upon success.
c0407a96 119 */
564889c1 120int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t);
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121
122
123/**
124 * omap_pm_set_min_bus_tput - set minimum bus throughput needed by device
125 * @dev: struct device * requesting the constraint
126 * @tbus_id: interconnect to operate on (OCP_{INITIATOR,TARGET}_AGENT)
127 * @r: minimum throughput (in KiB/s)
128 *
129 * Request that the minimum data throughput on the OCP interconnect
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130 * attached to device @dev interconnect agent @tbus_id be no less
131 * than @r KiB/s.
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132 *
133 * It is expected that the OMAP PM or bus code will use this
134 * information to set the interconnect clock to run at the lowest
135 * possible speed that satisfies all current system users. The PM or
136 * bus code will adjust the estimate based on its model of the bus, so
137 * device driver authors should attempt to specify an accurate
138 * quantity for their device use case, and let the PM or bus code
139 * overestimate the numbers as necessary to handle request/response
140 * latency, other competing users on the system, etc. On OMAP2/3, if
141 * a driver requests a minimum L4 interconnect speed constraint, the
142 * code will also need to add an minimum L3 interconnect speed
143 * constraint,
144 *
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145 * Multiple calls to omap_pm_set_min_bus_tput() will replace the
146 * previous rate value for this device. To remove the interconnect
147 * throughput restriction for this device, call with r = 0.
c0407a96 148 *
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149 * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
150 * is not satisfiable, or 0 upon success.
c0407a96 151 */
564889c1 152int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r);
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153
154
155/**
156 * omap_pm_set_max_dev_wakeup_lat - set the maximum device enable latency
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157 * @req_dev: struct device * requesting the constraint, or NULL if none
158 * @dev: struct device * to set the constraint one
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159 * @t: maximum device wakeup latency in microseconds
160 *
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161 * Request that the maximum amount of time necessary for a device @dev
162 * to become accessible after its clocks are enabled should be no
163 * greater than @t microseconds. Specifically, this represents the
164 * time from when a device driver enables device clocks with
165 * clk_enable(), to when the register reads and writes on the device
166 * will succeed. This function should be called before clk_disable()
167 * is called, since the power state transition decision may be made
168 * during clk_disable().
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169 *
170 * It is intended that underlying PM code will use this information to
171 * determine what power state to put the powerdomain enclosing this
172 * device into.
173 *
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174 * Multiple calls to omap_pm_set_max_dev_wakeup_lat() will replace the
175 * previous wakeup latency values for this device. To remove the
176 * wakeup latency restriction for this device, call with t = -1.
c0407a96 177 *
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178 * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
179 * is not satisfiable, or 0 upon success.
c0407a96 180 */
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181int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
182 long t);
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183
184
185/**
186 * omap_pm_set_max_sdma_lat - set the maximum system DMA transfer start latency
187 * @dev: struct device *
188 * @t: maximum DMA transfer start latency in microseconds
189 *
190 * Request that the maximum system DMA transfer start latency for this
191 * device 'dev' should be no greater than 't' microseconds. "DMA
192 * transfer start latency" here is defined as the elapsed time from
193 * when a device (e.g., McBSP) requests that a system DMA transfer
194 * start or continue, to the time at which data starts to flow into
195 * that device from the system DMA controller.
196 *
197 * It is intended that underlying PM code will use this information to
198 * determine what power state to put the CORE powerdomain into.
199 *
200 * Since system DMA transfers may not involve the MPU, this function
201 * will not affect MPU wakeup latency. Use set_max_cpu_lat() to do
202 * so. Similarly, this function will not affect device wakeup latency
203 * -- use set_max_dev_wakeup_lat() to affect that.
204 *
205 * Multiple calls to set_max_sdma_lat() will replace the previous t
206 * value for this device. To remove the maximum DMA latency for this
207 * device, call with t = -1.
208 *
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209 * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
210 * is not satisfiable, or 0 upon success.
c0407a96 211 */
564889c1 212int omap_pm_set_max_sdma_lat(struct device *dev, long t);
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213
214
215/*
216 * DSP Bridge-specific constraints
217 */
218
219/**
220 * omap_pm_dsp_get_opp_table - get OPP->DSP clock frequency table
221 *
222 * Intended for use by DSPBridge. Returns an array of OPP->DSP clock
223 * frequency entries. The final item in the array should have .rate =
224 * .opp_id = 0.
225 */
226const struct omap_opp *omap_pm_dsp_get_opp_table(void);
227
228/**
229 * omap_pm_dsp_set_min_opp - receive desired OPP target ID from DSP Bridge
230 * @opp_id: target DSP OPP ID
231 *
232 * Set a minimum OPP ID for the DSP. This is intended to be called
233 * only from the DSP Bridge MPU-side driver. Unfortunately, the only
234 * information that code receives from the DSP/BIOS load estimator is the
235 * target OPP ID; hence, this interface. No return value.
236 */
237void omap_pm_dsp_set_min_opp(u8 opp_id);
238
239/**
240 * omap_pm_dsp_get_opp - report the current DSP OPP ID
241 *
242 * Report the current OPP for the DSP. Since on OMAP3, the DSP and
243 * MPU share a single voltage domain, the OPP ID returned back may
244 * represent a higher DSP speed than the OPP requested via
245 * omap_pm_dsp_set_min_opp().
246 *
247 * Returns the current VDD1 OPP ID, or 0 upon error.
248 */
249u8 omap_pm_dsp_get_opp(void);
250
251
252/*
253 * CPUFreq-originated constraint
254 *
255 * In the future, this should be handled by custom OPP clocktype
256 * functions.
257 */
258
259/**
260 * omap_pm_cpu_get_freq_table - return a cpufreq_frequency_table array ptr
261 *
262 * Provide a frequency table usable by CPUFreq for the current chip/board.
263 * Returns a pointer to a struct cpufreq_frequency_table array or NULL
264 * upon error.
265 */
266struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void);
267
268/**
269 * omap_pm_cpu_set_freq - set the current minimum MPU frequency
270 * @f: MPU frequency in Hz
271 *
272 * Set the current minimum CPU frequency. The actual CPU frequency
273 * used could end up higher if the DSP requested a higher OPP.
274 * Intended to be called by plat-omap/cpu_omap.c:omap_target(). No
275 * return value.
276 */
277void omap_pm_cpu_set_freq(unsigned long f);
278
279/**
280 * omap_pm_cpu_get_freq - report the current CPU frequency
281 *
282 * Returns the current MPU frequency, or 0 upon error.
283 */
284unsigned long omap_pm_cpu_get_freq(void);
285
286
287/*
288 * Device context loss tracking
289 */
290
291/**
292 * omap_pm_get_dev_context_loss_count - return count of times dev has lost ctx
293 * @dev: struct device *
294 *
295 * This function returns the number of times that the device @dev has
296 * lost its internal context. This generally occurs on a powerdomain
297 * transition to OFF. Drivers use this as an optimization to avoid restoring
298 * context if the device hasn't lost it. To use, drivers should initially
299 * call this in their context save functions and store the result. Early in
300 * the driver's context restore function, the driver should call this function
301 * again, and compare the result to the stored counter. If they differ, the
302 * driver must restore device context. If the number of context losses
303 * exceeds the maximum positive integer, the function will wrap to 0 and
304 * continue counting. Returns the number of context losses for this device,
305 * or -EINVAL upon error.
306 */
307int omap_pm_get_dev_context_loss_count(struct device *dev);
308
309
310#endif
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