[deliverable/linux.git] / arch / arm / plat-omap / include / plat / omap-serial.h

/*
 * Driver for OMAP-UART controller.
 * Based on drivers/serial/8250.c
 *
 * Copyright (C) 2010 Texas Instruments.
 *
 * Authors:
 *	Govindraj R	<govindraj.raja@ti.com>
 *	Thara Gopinath	<thara@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef __OMAP_SERIAL_H__
#define __OMAP_SERIAL_H__

#include <linux/serial_core.h>
#include <linux/device.h>
#include <linux/pm_qos.h>

#include <plat/mux.h>

#define DRIVER_NAME	"omap_uart"

/*
 * Use tty device name as ttyO, [O -> OMAP]
 * in bootargs we specify as console=ttyO0 if uart1
 * is used as console uart.
 */
#define OMAP_SERIAL_NAME	"ttyO"

#define OMAP_MODE13X_SPEED	230400

#define OMAP_UART_SCR_TX_EMPTY	0x08

/* WER = 0x7F
 * Enable module level wakeup in WER reg
 */
#define OMAP_UART_WER_MOD_WKUP	0X7F

/* Enable XON/XOFF flow control on output */
#define OMAP_UART_SW_TX		0x04

/* Enable XON/XOFF flow control on input */
#define OMAP_UART_SW_RX		0x04

#define OMAP_UART_SYSC_RESET	0X07
#define OMAP_UART_TCR_TRIG	0X0F
#define OMAP_UART_SW_CLR	0XF0
#define OMAP_UART_FIFO_CLR	0X06

#define OMAP_UART_DMA_CH_FREE	-1

#define OMAP_MAX_HSUART_PORTS	4

#define MSR_SAVE_FLAGS		UART_MSR_ANY_DELTA

#define UART_ERRATA_i202_MDR1_ACCESS	BIT(0)
#define UART_ERRATA_i291_DMA_FORCEIDLE	BIT(1)

struct omap_uart_port_info {
	bool			dma_enabled;	/* To specify DMA Mode */
	unsigned int		uartclk;	/* UART clock rate */
	upf_t			flags;		/* UPF_* flags */
	unsigned int		dma_rx_buf_size;
	unsigned int		dma_rx_timeout;
	unsigned int		autosuspend_timeout;
	unsigned int		dma_rx_poll_rate;
	int			DTR_gpio;
	int			DTR_inverted;
	int			DTR_present;

	int (*get_context_loss_count)(struct device *);
	void (*set_forceidle)(struct device *);
	void (*set_noidle)(struct device *);
	void (*enable_wakeup)(struct device *, bool);
};

struct uart_omap_dma {
	u8			uart_dma_tx;
	u8			uart_dma_rx;
	int			rx_dma_channel;
	int			tx_dma_channel;
	dma_addr_t		rx_buf_dma_phys;
	dma_addr_t		tx_buf_dma_phys;
	unsigned int		uart_base;
	/*
	 * Buffer for rx dma.It is not required for tx because the buffer
	 * comes from port structure.
	 */
	unsigned char		*rx_buf;
	unsigned int		prev_rx_dma_pos;
	int			tx_buf_size;
	int			tx_dma_used;
	int			rx_dma_used;
	spinlock_t		tx_lock;
	spinlock_t		rx_lock;
	/* timer to poll activity on rx dma */
	struct timer_list	rx_timer;
	unsigned int		rx_buf_size;
	unsigned int		rx_poll_rate;
	unsigned int		rx_timeout;
};

struct uart_omap_port {
	struct uart_port	port;
	struct uart_omap_dma	uart_dma;
	struct device		*dev;

	unsigned char		ier;
	unsigned char		lcr;
	unsigned char		mcr;
	unsigned char		fcr;
	unsigned char		efr;
	unsigned char		dll;
	unsigned char		dlh;
	unsigned char		mdr1;
	unsigned char		scr;

	int			use_dma;
	/*
	 * Some bits in registers are cleared on a read, so they must
	 * be saved whenever the register is read but the bits will not
	 * be immediately processed.
	 */
	unsigned int		lsr_break_flag;
	unsigned char		msr_saved_flags;
	char			name[20];
	unsigned long		port_activity;
	u32			context_loss_cnt;
	u32			errata;
	u8			wakeups_enabled;

	int			DTR_gpio;
	int			DTR_inverted;
	int			DTR_active;

	struct pm_qos_request	pm_qos_request;
	u32			latency;
	u32			calc_latency;
	struct work_struct	qos_work;
};

#define to_uart_omap_port(p)	((container_of((p), struct uart_omap_port, port)))

#endif /* __OMAP_SERIAL_H__ */
Commit	Line	Data
b612633b G	1	/*
	2	* Driver for OMAP-UART controller.
	3	* Based on drivers/serial/8250.c
	4	*
	5	* Copyright (C) 2010 Texas Instruments.
	6	*
	7	* Authors:
	8	* Govindraj R <govindraj.raja@ti.com>
	9	* Thara Gopinath <thara@ti.com>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*/
	16
	17	#ifndef __OMAP_SERIAL_H__
	18	#define __OMAP_SERIAL_H__
	19
	20	#include <linux/serial_core.h>
d8ee4ea6	21	#include <linux/device.h>
2fd14964	22	#include <linux/pm_qos.h>
b612633b	23
b612633b G	24	#include <plat/mux.h>
b612633b G	25
374b8cfd	26	#define DRIVER_NAME "omap_uart"
b612633b G	27
	28	/*
	29	* Use tty device name as ttyO, [O -> OMAP]
	30	* in bootargs we specify as console=ttyO0 if uart1
	31	* is used as console uart.
	32	*/
	33	#define OMAP_SERIAL_NAME "ttyO"
	34
b612633b G	35	#define OMAP_MODE13X_SPEED 230400
b612633b G	36
32212897 G	37	#define OMAP_UART_SCR_TX_EMPTY 0x08
32212897 G	38
b612633b G	39	/* WER = 0x7F
	40	* Enable module level wakeup in WER reg
	41	*/
	42	#define OMAP_UART_WER_MOD_WKUP 0X7F
	43
	44	/* Enable XON/XOFF flow control on output */
	45	#define OMAP_UART_SW_TX 0x04
	46
	47	/* Enable XON/XOFF flow control on input */
	48	#define OMAP_UART_SW_RX 0x04
	49
	50	#define OMAP_UART_SYSC_RESET 0X07
	51	#define OMAP_UART_TCR_TRIG 0X0F
	52	#define OMAP_UART_SW_CLR 0XF0
	53	#define OMAP_UART_FIFO_CLR 0X06
	54
	55	#define OMAP_UART_DMA_CH_FREE -1
	56
b612633b G	57	#define OMAP_MAX_HSUART_PORTS 4
	58
	59	#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
	60
94734749 G	61	#define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
	62	#define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
	63
b612633b G	64	struct omap_uart_port_info {
	65	bool dma_enabled; /* To specify DMA Mode */
	66	unsigned int uartclk; /* UART clock rate */
b612633b	67	upf_t flags; /* UPF_* flags */
c86845db D	68	unsigned int dma_rx_buf_size;
	69	unsigned int dma_rx_timeout;
	70	unsigned int autosuspend_timeout;
a9e210e0	71	unsigned int dma_rx_poll_rate;
9574f36f N	72	int DTR_gpio;
	73	int DTR_inverted;
	74	int DTR_present;
ec3bebc6 G	75
ec3bebc6 G	76	int (get_context_loss_count)(struct device );
d8ee4ea6 FB	77	void (set_forceidle)(struct device );
	78	void (set_noidle)(struct device );
	79	void (enable_wakeup)(struct device , bool);
b612633b G	80	};
	81
	82	struct uart_omap_dma {
	83	u8 uart_dma_tx;
	84	u8 uart_dma_rx;
	85	int rx_dma_channel;
	86	int tx_dma_channel;
	87	dma_addr_t rx_buf_dma_phys;
	88	dma_addr_t tx_buf_dma_phys;
	89	unsigned int uart_base;
	90	/*
	91	* Buffer for rx dma.It is not required for tx because the buffer
	92	* comes from port structure.
	93	*/
	94	unsigned char *rx_buf;
	95	unsigned int prev_rx_dma_pos;
	96	int tx_buf_size;
	97	int tx_dma_used;
	98	int rx_dma_used;
	99	spinlock_t tx_lock;
	100	spinlock_t rx_lock;
	101	/* timer to poll activity on rx dma */
	102	struct timer_list rx_timer;
c86845db	103	unsigned int rx_buf_size;
a9e210e0	104	unsigned int rx_poll_rate;
c86845db	105	unsigned int rx_timeout;
b612633b G	106	};
	107
	108	struct uart_omap_port {
	109	struct uart_port port;
	110	struct uart_omap_dma uart_dma;
d8ee4ea6	111	struct device *dev;
b612633b G	112
	113	unsigned char ier;
	114	unsigned char lcr;
	115	unsigned char mcr;
	116	unsigned char fcr;
	117	unsigned char efr;
c538d20c G	118	unsigned char dll;
	119	unsigned char dlh;
	120	unsigned char mdr1;
	121	unsigned char scr;
b612633b G	122
	123	int use_dma;
	124	/*
	125	* Some bits in registers are cleared on a read, so they must
	126	* be saved whenever the register is read but the bits will not
	127	* be immediately processed.
	128	*/
	129	unsigned int lsr_break_flag;
	130	unsigned char msr_saved_flags;
	131	char name[20];
	132	unsigned long port_activity;
ec3bebc6	133	u32 context_loss_cnt;
94734749	134	u32 errata;
62f3ec5f	135	u8 wakeups_enabled;
2fd14964	136
9574f36f N	137	int DTR_gpio;
	138	int DTR_inverted;
	139	int DTR_active;
	140
2fd14964 G	141	struct pm_qos_request pm_qos_request;
	142	u32 latency;
	143	u32 calc_latency;
	144	struct work_struct qos_work;
b612633b G	145	};
b612633b G	146
c990f351 FB	147	#define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
c990f351 FB	148
b612633b	149	#endif /* __OMAP_SERIAL_H__ */