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63c85238 PW |
1 | /* |
2 | * omap_hwmod macros, structures | |
3 | * | |
db2a60bf | 4 | * Copyright (C) 2009-2010 Nokia Corporation |
63c85238 PW |
5 | * Paul Walmsley |
6 | * | |
43b40992 | 7 | * Created in collaboration with (alphabetical order): Benoît Cousson, |
63c85238 PW |
8 | * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari |
9 | * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
15 | * These headers and macros are used to define OMAP on-chip module | |
16 | * data and their integration with other OMAP modules and Linux. | |
74ff3a68 PW |
17 | * Copious documentation and references can also be found in the |
18 | * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this | |
19 | * writing). | |
63c85238 PW |
20 | * |
21 | * To do: | |
22 | * - add interconnect error log structures | |
23 | * - add pinmuxing | |
24 | * - init_conn_id_bit (CONNID_BIT_VECTOR) | |
25 | * - implement default hwmod SMS/SDRC flags? | |
b56b7bc8 | 26 | * - move Linux-specific data ("non-ROM data") out |
63c85238 PW |
27 | * |
28 | */ | |
29 | #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H | |
30 | #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H | |
31 | ||
32 | #include <linux/kernel.h> | |
358f0e63 | 33 | #include <linux/list.h> |
63c85238 | 34 | #include <linux/ioport.h> |
dc6d1cda | 35 | #include <linux/spinlock.h> |
ce491cf8 | 36 | #include <plat/cpu.h> |
63c85238 PW |
37 | |
38 | struct omap_device; | |
39 | ||
358f0e63 TG |
40 | extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1; |
41 | extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2; | |
42 | ||
43 | /* | |
44 | * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant | |
45 | * with the original PRCM protocol defined for OMAP2420 | |
46 | */ | |
47 | #define SYSC_TYPE1_MIDLEMODE_SHIFT 12 | |
48 | #define SYSC_TYPE1_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT) | |
49 | #define SYSC_TYPE1_CLOCKACTIVITY_SHIFT 8 | |
50 | #define SYSC_TYPE1_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT) | |
51 | #define SYSC_TYPE1_SIDLEMODE_SHIFT 3 | |
52 | #define SYSC_TYPE1_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT) | |
53 | #define SYSC_TYPE1_ENAWAKEUP_SHIFT 2 | |
54 | #define SYSC_TYPE1_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT) | |
55 | #define SYSC_TYPE1_SOFTRESET_SHIFT 1 | |
56 | #define SYSC_TYPE1_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT) | |
57 | #define SYSC_TYPE1_AUTOIDLE_SHIFT 0 | |
58 | #define SYSC_TYPE1_AUTOIDLE_MASK (1 << SYSC_AUTOIDLE_SHIFT) | |
59 | ||
60 | /* | |
61 | * OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant | |
62 | * with the new PRCM protocol defined for new OMAP4 IPs. | |
63 | */ | |
64 | #define SYSC_TYPE2_SOFTRESET_SHIFT 0 | |
65 | #define SYSC_TYPE2_SOFTRESET_MASK (1 << SYSC_TYPE2_SOFTRESET_SHIFT) | |
66 | #define SYSC_TYPE2_SIDLEMODE_SHIFT 2 | |
67 | #define SYSC_TYPE2_SIDLEMODE_MASK (0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT) | |
68 | #define SYSC_TYPE2_MIDLEMODE_SHIFT 4 | |
69 | #define SYSC_TYPE2_MIDLEMODE_MASK (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT) | |
63c85238 PW |
70 | |
71 | /* OCP SYSSTATUS bit shifts/masks */ | |
72 | #define SYSS_RESETDONE_SHIFT 0 | |
73 | #define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT) | |
74 | ||
75 | /* Master standby/slave idle mode flags */ | |
76 | #define HWMOD_IDLEMODE_FORCE (1 << 0) | |
77 | #define HWMOD_IDLEMODE_NO (1 << 1) | |
78 | #define HWMOD_IDLEMODE_SMART (1 << 2) | |
86009eb3 BC |
79 | /* Slave idle mode flag only */ |
80 | #define HWMOD_IDLEMODE_SMART_WKUP (1 << 3) | |
63c85238 | 81 | |
63c85238 | 82 | /** |
718bfd76 PW |
83 | * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod |
84 | * @name: name of the IRQ channel (module local name) | |
85 | * @irq_ch: IRQ channel ID | |
86 | * | |
87 | * @name should be something short, e.g., "tx" or "rx". It is for use | |
88 | * by platform_get_resource_byname(). It is defined locally to the | |
89 | * hwmod. | |
90 | */ | |
91 | struct omap_hwmod_irq_info { | |
92 | const char *name; | |
93 | u16 irq; | |
94 | }; | |
95 | ||
96 | /** | |
97 | * struct omap_hwmod_dma_info - DMA channels used by the hwmod | |
63c85238 | 98 | * @name: name of the DMA channel (module local name) |
9ee9fff9 | 99 | * @dma_req: DMA request ID |
63c85238 PW |
100 | * |
101 | * @name should be something short, e.g., "tx" or "rx". It is for use | |
102 | * by platform_get_resource_byname(). It is defined locally to the | |
103 | * hwmod. | |
104 | */ | |
105 | struct omap_hwmod_dma_info { | |
106 | const char *name; | |
9ee9fff9 | 107 | u16 dma_req; |
63c85238 PW |
108 | }; |
109 | ||
5365efbe BC |
110 | /** |
111 | * struct omap_hwmod_rst_info - IPs reset lines use by hwmod | |
112 | * @name: name of the reset line (module local name) | |
113 | * @rst_shift: Offset of the reset bit | |
114 | * | |
115 | * @name should be something short, e.g., "cpu0" or "rst". It is defined | |
116 | * locally to the hwmod. | |
117 | */ | |
118 | struct omap_hwmod_rst_info { | |
119 | const char *name; | |
120 | u8 rst_shift; | |
121 | }; | |
122 | ||
63c85238 PW |
123 | /** |
124 | * struct omap_hwmod_opt_clk - optional clocks used by this hwmod | |
125 | * @role: "sys", "32k", "tv", etc -- for use in clk_get() | |
50ebdac2 | 126 | * @clk: opt clock: OMAP clock name |
63c85238 PW |
127 | * @_clk: pointer to the struct clk (filled in at runtime) |
128 | * | |
129 | * The module's interface clock and main functional clock should not | |
130 | * be added as optional clocks. | |
131 | */ | |
132 | struct omap_hwmod_opt_clk { | |
133 | const char *role; | |
50ebdac2 | 134 | const char *clk; |
63c85238 PW |
135 | struct clk *_clk; |
136 | }; | |
137 | ||
138 | ||
139 | /* omap_hwmod_omap2_firewall.flags bits */ | |
140 | #define OMAP_FIREWALL_L3 (1 << 0) | |
141 | #define OMAP_FIREWALL_L4 (1 << 1) | |
142 | ||
143 | /** | |
144 | * struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data | |
145 | * @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_* | |
146 | * @l4_fw_region: L4 firewall region ID | |
147 | * @l4_prot_group: L4 protection group ID | |
148 | * @flags: (see omap_hwmod_omap2_firewall.flags macros above) | |
149 | */ | |
150 | struct omap_hwmod_omap2_firewall { | |
151 | u8 l3_perm_bit; | |
152 | u8 l4_fw_region; | |
153 | u8 l4_prot_group; | |
154 | u8 flags; | |
155 | }; | |
156 | ||
157 | ||
158 | /* | |
159 | * omap_hwmod_addr_space.flags bits | |
160 | * | |
161 | * ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init. | |
162 | * ADDR_TYPE_RT: Address space contains module register target data. | |
163 | */ | |
b56b7bc8 | 164 | #define ADDR_MAP_ON_INIT (1 << 0) /* XXX does not belong */ |
63c85238 PW |
165 | #define ADDR_TYPE_RT (1 << 1) |
166 | ||
167 | /** | |
168 | * struct omap_hwmod_addr_space - MPU address space handled by the hwmod | |
169 | * @pa_start: starting physical address | |
170 | * @pa_end: ending physical address | |
171 | * @flags: (see omap_hwmod_addr_space.flags macros above) | |
172 | * | |
173 | * Address space doesn't necessarily follow physical interconnect | |
174 | * structure. GPMC is one example. | |
175 | */ | |
176 | struct omap_hwmod_addr_space { | |
177 | u32 pa_start; | |
178 | u32 pa_end; | |
179 | u8 flags; | |
180 | }; | |
181 | ||
182 | ||
183 | /* | |
184 | * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this | |
185 | * interface to interact with the hwmod. Used to add sleep dependencies | |
186 | * when the module is enabled or disabled. | |
187 | */ | |
188 | #define OCP_USER_MPU (1 << 0) | |
189 | #define OCP_USER_SDMA (1 << 1) | |
190 | ||
191 | /* omap_hwmod_ocp_if.flags bits */ | |
33f7ec81 BC |
192 | #define OCPIF_SWSUP_IDLE (1 << 0) |
193 | #define OCPIF_CAN_BURST (1 << 1) | |
63c85238 PW |
194 | |
195 | /** | |
196 | * struct omap_hwmod_ocp_if - OCP interface data | |
197 | * @master: struct omap_hwmod that initiates OCP transactions on this link | |
198 | * @slave: struct omap_hwmod that responds to OCP transactions on this link | |
199 | * @addr: address space associated with this link | |
50ebdac2 | 200 | * @clk: interface clock: OMAP clock name |
63c85238 PW |
201 | * @_clk: pointer to the interface struct clk (filled in at runtime) |
202 | * @fw: interface firewall data | |
203 | * @addr_cnt: ARRAY_SIZE(@addr) | |
204 | * @width: OCP data width | |
63c85238 PW |
205 | * @user: initiators using this interface (see OCP_USER_* macros above) |
206 | * @flags: OCP interface flags (see OCPIF_* macros above) | |
207 | * | |
208 | * It may also be useful to add a tag_cnt field for OCP2.x devices. | |
209 | * | |
210 | * Parameter names beginning with an underscore are managed internally by | |
211 | * the omap_hwmod code and should not be set during initialization. | |
212 | */ | |
213 | struct omap_hwmod_ocp_if { | |
214 | struct omap_hwmod *master; | |
215 | struct omap_hwmod *slave; | |
216 | struct omap_hwmod_addr_space *addr; | |
50ebdac2 | 217 | const char *clk; |
63c85238 PW |
218 | struct clk *_clk; |
219 | union { | |
220 | struct omap_hwmod_omap2_firewall omap2; | |
221 | } fw; | |
222 | u8 addr_cnt; | |
223 | u8 width; | |
63c85238 PW |
224 | u8 user; |
225 | u8 flags; | |
226 | }; | |
227 | ||
228 | ||
229 | /* Macros for use in struct omap_hwmod_sysconfig */ | |
230 | ||
231 | /* Flags for use in omap_hwmod_sysconfig.idlemodes */ | |
86009eb3 | 232 | #define MASTER_STANDBY_SHIFT 4 |
63c85238 PW |
233 | #define SLAVE_IDLE_SHIFT 0 |
234 | #define SIDLE_FORCE (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT) | |
235 | #define SIDLE_NO (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT) | |
236 | #define SIDLE_SMART (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT) | |
86009eb3 | 237 | #define SIDLE_SMART_WKUP (HWMOD_IDLEMODE_SMART_WKUP << SLAVE_IDLE_SHIFT) |
63c85238 PW |
238 | #define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT) |
239 | #define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT) | |
240 | #define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT) | |
241 | ||
242 | /* omap_hwmod_sysconfig.sysc_flags capability flags */ | |
243 | #define SYSC_HAS_AUTOIDLE (1 << 0) | |
244 | #define SYSC_HAS_SOFTRESET (1 << 1) | |
245 | #define SYSC_HAS_ENAWAKEUP (1 << 2) | |
246 | #define SYSC_HAS_EMUFREE (1 << 3) | |
247 | #define SYSC_HAS_CLOCKACTIVITY (1 << 4) | |
248 | #define SYSC_HAS_SIDLEMODE (1 << 5) | |
249 | #define SYSC_HAS_MIDLEMODE (1 << 6) | |
2cb06814 | 250 | #define SYSS_HAS_RESET_STATUS (1 << 7) |
883edfdd | 251 | #define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */ |
2cb06814 | 252 | #define SYSC_HAS_RESET_STATUS (1 << 9) |
63c85238 PW |
253 | |
254 | /* omap_hwmod_sysconfig.clockact flags */ | |
255 | #define CLOCKACT_TEST_BOTH 0x0 | |
256 | #define CLOCKACT_TEST_MAIN 0x1 | |
257 | #define CLOCKACT_TEST_ICLK 0x2 | |
258 | #define CLOCKACT_TEST_NONE 0x3 | |
259 | ||
358f0e63 TG |
260 | /** |
261 | * struct omap_hwmod_sysc_fields - hwmod OCP_SYSCONFIG register field offsets. | |
262 | * @midle_shift: Offset of the midle bit | |
263 | * @clkact_shift: Offset of the clockactivity bit | |
264 | * @sidle_shift: Offset of the sidle bit | |
265 | * @enwkup_shift: Offset of the enawakeup bit | |
266 | * @srst_shift: Offset of the softreset bit | |
43b40992 | 267 | * @autoidle_shift: Offset of the autoidle bit |
358f0e63 TG |
268 | */ |
269 | struct omap_hwmod_sysc_fields { | |
270 | u8 midle_shift; | |
271 | u8 clkact_shift; | |
272 | u8 sidle_shift; | |
273 | u8 enwkup_shift; | |
274 | u8 srst_shift; | |
275 | u8 autoidle_shift; | |
276 | }; | |
277 | ||
63c85238 | 278 | /** |
43b40992 | 279 | * struct omap_hwmod_class_sysconfig - hwmod class OCP_SYS* data |
63c85238 PW |
280 | * @rev_offs: IP block revision register offset (from module base addr) |
281 | * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr) | |
282 | * @syss_offs: OCP_SYSSTATUS register offset (from module base addr) | |
283 | * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART} | |
284 | * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported | |
285 | * @clockact: the default value of the module CLOCKACTIVITY bits | |
286 | * | |
287 | * @clockact describes to the module which clocks are likely to be | |
288 | * disabled when the PRCM issues its idle request to the module. Some | |
289 | * modules have separate clockdomains for the interface clock and main | |
290 | * functional clock, and can check whether they should acknowledge the | |
291 | * idle request based on the internal module functionality that has | |
292 | * been associated with the clocks marked in @clockact. This field is | |
293 | * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below) | |
294 | * | |
358f0e63 TG |
295 | * @sysc_fields: structure containing the offset positions of various bits in |
296 | * SYSCONFIG register. This can be populated using omap_hwmod_sysc_type1 or | |
297 | * omap_hwmod_sysc_type2 defined in omap_hwmod_common_data.c depending on | |
298 | * whether the device ip is compliant with the original PRCM protocol | |
43b40992 PW |
299 | * defined for OMAP2420 or the new PRCM protocol for new OMAP4 IPs. |
300 | * If the device follows a different scheme for the sysconfig register , | |
358f0e63 | 301 | * then this field has to be populated with the correct offset structure. |
63c85238 | 302 | */ |
43b40992 | 303 | struct omap_hwmod_class_sysconfig { |
63c85238 PW |
304 | u16 rev_offs; |
305 | u16 sysc_offs; | |
306 | u16 syss_offs; | |
56dc79ab | 307 | u16 sysc_flags; |
63c85238 | 308 | u8 idlemodes; |
63c85238 | 309 | u8 clockact; |
358f0e63 | 310 | struct omap_hwmod_sysc_fields *sysc_fields; |
63c85238 PW |
311 | }; |
312 | ||
313 | /** | |
314 | * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data | |
315 | * @module_offs: PRCM submodule offset from the start of the PRM/CM | |
316 | * @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3) | |
317 | * @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs | |
318 | * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3) | |
319 | * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit | |
320 | * @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit | |
321 | * | |
322 | * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST, | |
323 | * WKEN, GRPSEL registers. In an ideal world, no extra information | |
324 | * would be needed for IDLEST information, but alas, there are some | |
325 | * exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit | |
326 | * are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST) | |
327 | */ | |
328 | struct omap_hwmod_omap2_prcm { | |
329 | s16 module_offs; | |
330 | u8 prcm_reg_id; | |
331 | u8 module_bit; | |
332 | u8 idlest_reg_id; | |
333 | u8 idlest_idle_bit; | |
334 | u8 idlest_stdby_bit; | |
335 | }; | |
336 | ||
337 | ||
338 | /** | |
339 | * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data | |
53934aa7 | 340 | * @clkctrl_reg: PRCM address of the clock control register |
5365efbe | 341 | * @rstctrl_reg: adress of the XXX_RSTCTRL register located in the PRM |
63c85238 PW |
342 | * @submodule_wkdep_bit: bit shift of the WKDEP range |
343 | */ | |
344 | struct omap_hwmod_omap4_prcm { | |
53934aa7 | 345 | void __iomem *clkctrl_reg; |
5365efbe | 346 | void __iomem *rstctrl_reg; |
53934aa7 | 347 | u8 submodule_wkdep_bit; |
63c85238 PW |
348 | }; |
349 | ||
350 | ||
351 | /* | |
352 | * omap_hwmod.flags definitions | |
353 | * | |
354 | * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out | |
355 | * of idle, rather than relying on module smart-idle | |
356 | * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out | |
357 | * of standby, rather than relying on module smart-standby | |
358 | * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for | |
b56b7bc8 | 359 | * SDRAM controller, etc. XXX probably belongs outside the main hwmod file |
63c85238 | 360 | * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM |
b56b7bc8 | 361 | * controller, etc. XXX probably belongs outside the main hwmod file |
726072e5 PW |
362 | * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE) |
363 | * when module is enabled, rather than the default, which is to | |
364 | * enable autoidle | |
63c85238 | 365 | * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup |
bd36179e | 366 | * HWMOD_NO_IDLEST: this module does not have idle status - this is the case |
33f7ec81 | 367 | * only for few initiator modules on OMAP2 & 3. |
96835af9 BC |
368 | * HWMOD_CONTROL_OPT_CLKS_IN_RESET: Enable all optional clocks during reset. |
369 | * This is needed for devices like DSS that require optional clocks enabled | |
370 | * in order to complete the reset. Optional clocks will be disabled | |
371 | * again after the reset. | |
cc7a1d2a | 372 | * HWMOD_16BIT_REG: Module has 16bit registers |
63c85238 PW |
373 | */ |
374 | #define HWMOD_SWSUP_SIDLE (1 << 0) | |
375 | #define HWMOD_SWSUP_MSTANDBY (1 << 1) | |
376 | #define HWMOD_INIT_NO_RESET (1 << 2) | |
377 | #define HWMOD_INIT_NO_IDLE (1 << 3) | |
726072e5 PW |
378 | #define HWMOD_NO_OCP_AUTOIDLE (1 << 4) |
379 | #define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5) | |
33f7ec81 | 380 | #define HWMOD_NO_IDLEST (1 << 6) |
96835af9 | 381 | #define HWMOD_CONTROL_OPT_CLKS_IN_RESET (1 << 7) |
cc7a1d2a | 382 | #define HWMOD_16BIT_REG (1 << 8) |
63c85238 PW |
383 | |
384 | /* | |
385 | * omap_hwmod._int_flags definitions | |
386 | * These are for internal use only and are managed by the omap_hwmod code. | |
387 | * | |
388 | * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module | |
389 | * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP | |
390 | * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached | |
391 | */ | |
392 | #define _HWMOD_NO_MPU_PORT (1 << 0) | |
393 | #define _HWMOD_WAKEUP_ENABLED (1 << 1) | |
394 | #define _HWMOD_SYSCONFIG_LOADED (1 << 2) | |
395 | ||
396 | /* | |
397 | * omap_hwmod._state definitions | |
398 | * | |
399 | * INITIALIZED: reset (optionally), initialized, enabled, disabled | |
400 | * (optionally) | |
401 | * | |
402 | * | |
403 | */ | |
404 | #define _HWMOD_STATE_UNKNOWN 0 | |
405 | #define _HWMOD_STATE_REGISTERED 1 | |
406 | #define _HWMOD_STATE_CLKS_INITED 2 | |
407 | #define _HWMOD_STATE_INITIALIZED 3 | |
408 | #define _HWMOD_STATE_ENABLED 4 | |
409 | #define _HWMOD_STATE_IDLE 5 | |
410 | #define _HWMOD_STATE_DISABLED 6 | |
411 | ||
43b40992 PW |
412 | /** |
413 | * struct omap_hwmod_class - the type of an IP block | |
414 | * @name: name of the hwmod_class | |
415 | * @sysc: device SYSCONFIG/SYSSTATUS register data | |
416 | * @rev: revision of the IP class | |
e4dc8f50 | 417 | * @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown |
bd36179e | 418 | * @reset: ptr to fn to be executed in place of the standard hwmod reset fn |
43b40992 PW |
419 | * |
420 | * Represent the class of a OMAP hardware "modules" (e.g. timer, | |
421 | * smartreflex, gpio, uart...) | |
e4dc8f50 PW |
422 | * |
423 | * @pre_shutdown is a function that will be run immediately before | |
424 | * hwmod clocks are disabled, etc. It is intended for use for hwmods | |
425 | * like the MPU watchdog, which cannot be disabled with the standard | |
426 | * omap_hwmod_shutdown(). The function should return 0 upon success, | |
427 | * or some negative error upon failure. Returning an error will cause | |
428 | * omap_hwmod_shutdown() to abort the device shutdown and return an | |
429 | * error. | |
bd36179e PW |
430 | * |
431 | * If @reset is defined, then the function it points to will be | |
432 | * executed in place of the standard hwmod _reset() code in | |
433 | * mach-omap2/omap_hwmod.c. This is needed for IP blocks which have | |
434 | * unusual reset sequences - usually processor IP blocks like the IVA. | |
43b40992 PW |
435 | */ |
436 | struct omap_hwmod_class { | |
437 | const char *name; | |
438 | struct omap_hwmod_class_sysconfig *sysc; | |
439 | u32 rev; | |
e4dc8f50 | 440 | int (*pre_shutdown)(struct omap_hwmod *oh); |
bd36179e | 441 | int (*reset)(struct omap_hwmod *oh); |
43b40992 PW |
442 | }; |
443 | ||
63c85238 PW |
444 | /** |
445 | * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks) | |
446 | * @name: name of the hwmod | |
43b40992 | 447 | * @class: struct omap_hwmod_class * to the class of this hwmod |
63c85238 PW |
448 | * @od: struct omap_device currently associated with this hwmod (internal use) |
449 | * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt) | |
9ee9fff9 | 450 | * @sdma_reqs: ptr to an array of System DMA request IDs (see sdma_reqs_cnt) |
63c85238 | 451 | * @prcm: PRCM data pertaining to this hwmod |
50ebdac2 | 452 | * @main_clk: main clock: OMAP clock name |
63c85238 PW |
453 | * @_clk: pointer to the main struct clk (filled in at runtime) |
454 | * @opt_clks: other device clocks that drivers can request (0..*) | |
455 | * @masters: ptr to array of OCP ifs that this hwmod can initiate on | |
456 | * @slaves: ptr to array of OCP ifs that this hwmod can respond on | |
63c85238 PW |
457 | * @dev_attr: arbitrary device attributes that can be passed to the driver |
458 | * @_sysc_cache: internal-use hwmod flags | |
db2a60bf | 459 | * @_mpu_rt_va: cached register target start address (internal use) |
63c85238 | 460 | * @_mpu_port_index: cached MPU register target slave ID (internal use) |
63c85238 | 461 | * @mpu_irqs_cnt: number of @mpu_irqs |
9ee9fff9 | 462 | * @sdma_reqs_cnt: number of @sdma_reqs |
63c85238 PW |
463 | * @opt_clks_cnt: number of @opt_clks |
464 | * @master_cnt: number of @master entries | |
465 | * @slaves_cnt: number of @slave entries | |
466 | * @response_lat: device OCP response latency (in interface clock cycles) | |
467 | * @_int_flags: internal-use hwmod flags | |
468 | * @_state: internal-use hwmod state | |
2092e5cc | 469 | * @_postsetup_state: internal-use state to leave the hwmod in after _setup() |
63c85238 PW |
470 | * @flags: hwmod flags (documented below) |
471 | * @omap_chip: OMAP chips this hwmod is present on | |
dc6d1cda | 472 | * @_lock: spinlock serializing operations on this hwmod |
63c85238 PW |
473 | * @node: list node for hwmod list (internal use) |
474 | * | |
50ebdac2 PW |
475 | * @main_clk refers to this module's "main clock," which for our |
476 | * purposes is defined as "the functional clock needed for register | |
477 | * accesses to complete." Modules may not have a main clock if the | |
478 | * interface clock also serves as a main clock. | |
63c85238 PW |
479 | * |
480 | * Parameter names beginning with an underscore are managed internally by | |
481 | * the omap_hwmod code and should not be set during initialization. | |
482 | */ | |
483 | struct omap_hwmod { | |
484 | const char *name; | |
43b40992 | 485 | struct omap_hwmod_class *class; |
63c85238 | 486 | struct omap_device *od; |
718bfd76 | 487 | struct omap_hwmod_irq_info *mpu_irqs; |
9ee9fff9 | 488 | struct omap_hwmod_dma_info *sdma_reqs; |
5365efbe | 489 | struct omap_hwmod_rst_info *rst_lines; |
63c85238 PW |
490 | union { |
491 | struct omap_hwmod_omap2_prcm omap2; | |
492 | struct omap_hwmod_omap4_prcm omap4; | |
493 | } prcm; | |
50ebdac2 | 494 | const char *main_clk; |
63c85238 PW |
495 | struct clk *_clk; |
496 | struct omap_hwmod_opt_clk *opt_clks; | |
497 | struct omap_hwmod_ocp_if **masters; /* connect to *_IA */ | |
498 | struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */ | |
63c85238 PW |
499 | void *dev_attr; |
500 | u32 _sysc_cache; | |
db2a60bf | 501 | void __iomem *_mpu_rt_va; |
dc6d1cda | 502 | spinlock_t _lock; |
63c85238 PW |
503 | struct list_head node; |
504 | u16 flags; | |
505 | u8 _mpu_port_index; | |
63c85238 PW |
506 | u8 response_lat; |
507 | u8 mpu_irqs_cnt; | |
9ee9fff9 | 508 | u8 sdma_reqs_cnt; |
5365efbe | 509 | u8 rst_lines_cnt; |
63c85238 PW |
510 | u8 opt_clks_cnt; |
511 | u8 masters_cnt; | |
512 | u8 slaves_cnt; | |
513 | u8 hwmods_cnt; | |
514 | u8 _int_flags; | |
515 | u8 _state; | |
2092e5cc | 516 | u8 _postsetup_state; |
63c85238 PW |
517 | const struct omap_chip_id omap_chip; |
518 | }; | |
519 | ||
520 | int omap_hwmod_init(struct omap_hwmod **ohs); | |
63c85238 | 521 | struct omap_hwmod *omap_hwmod_lookup(const char *name); |
97d60162 PW |
522 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
523 | void *data); | |
2092e5cc | 524 | int omap_hwmod_late_init(void); |
63c85238 PW |
525 | |
526 | int omap_hwmod_enable(struct omap_hwmod *oh); | |
84824022 | 527 | int _omap_hwmod_enable(struct omap_hwmod *oh); |
63c85238 | 528 | int omap_hwmod_idle(struct omap_hwmod *oh); |
84824022 | 529 | int _omap_hwmod_idle(struct omap_hwmod *oh); |
63c85238 PW |
530 | int omap_hwmod_shutdown(struct omap_hwmod *oh); |
531 | ||
aee48e3c PW |
532 | int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name); |
533 | int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name); | |
534 | int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name); | |
535 | ||
63c85238 PW |
536 | int omap_hwmod_enable_clocks(struct omap_hwmod *oh); |
537 | int omap_hwmod_disable_clocks(struct omap_hwmod *oh); | |
538 | ||
46273e6f KH |
539 | int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode); |
540 | ||
63c85238 PW |
541 | int omap_hwmod_reset(struct omap_hwmod *oh); |
542 | void omap_hwmod_ocp_barrier(struct omap_hwmod *oh); | |
543 | ||
cc7a1d2a RN |
544 | void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs); |
545 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs); | |
63c85238 PW |
546 | |
547 | int omap_hwmod_count_resources(struct omap_hwmod *oh); | |
548 | int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); | |
549 | ||
550 | struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh); | |
db2a60bf | 551 | void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh); |
63c85238 PW |
552 | |
553 | int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, | |
554 | struct omap_hwmod *init_oh); | |
555 | int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, | |
556 | struct omap_hwmod *init_oh); | |
557 | ||
558 | int omap_hwmod_set_clockact_both(struct omap_hwmod *oh); | |
559 | int omap_hwmod_set_clockact_main(struct omap_hwmod *oh); | |
560 | int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh); | |
561 | int omap_hwmod_set_clockact_none(struct omap_hwmod *oh); | |
562 | ||
563 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh); | |
564 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh); | |
565 | ||
43b40992 PW |
566 | int omap_hwmod_for_each_by_class(const char *classname, |
567 | int (*fn)(struct omap_hwmod *oh, | |
568 | void *user), | |
569 | void *user); | |
570 | ||
2092e5cc | 571 | int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state); |
c80705aa | 572 | u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh); |
2092e5cc | 573 | |
7359154e PW |
574 | /* |
575 | * Chip variant-specific hwmod init routines - XXX should be converted | |
576 | * to use initcalls once the initial boot ordering is straightened out | |
577 | */ | |
578 | extern int omap2420_hwmod_init(void); | |
579 | extern int omap2430_hwmod_init(void); | |
580 | extern int omap3xxx_hwmod_init(void); | |
55d2cb08 | 581 | extern int omap44xx_hwmod_init(void); |
7359154e | 582 | |
63c85238 | 583 | #endif |