[deliverable/linux.git] / arch / arm / plat-omap / include / plat / omap_hwmod.h

/*
 * omap_hwmod macros, structures
 *
 * Copyright (C) 2009 Nokia Corporation
 * Paul Walmsley
 *
 * Created in collaboration with (alphabetical order): Benoit Cousson,
 * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari
 * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * These headers and macros are used to define OMAP on-chip module
 * data and their integration with other OMAP modules and Linux.
 *
 * References:
 * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
 * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
 * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
 * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140)
 * - Open Core Protocol Specification 2.2
 *
 * To do:
 * - add interconnect error log structures
 * - add pinmuxing
 * - init_conn_id_bit (CONNID_BIT_VECTOR)
 * - implement default hwmod SMS/SDRC flags?
 *
 */
#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H

#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/ioport.h>
#include <plat/cpu.h>

struct omap_device;

extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1;
extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;

/*
 * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant
 * with the original PRCM protocol defined for OMAP2420
 */
#define SYSC_TYPE1_MIDLEMODE_SHIFT	12
#define SYSC_TYPE1_MIDLEMODE_MASK	(0x3 << SYSC_MIDLEMODE_SHIFT)
#define SYSC_TYPE1_CLOCKACTIVITY_SHIFT	8
#define SYSC_TYPE1_CLOCKACTIVITY_MASK	(0x3 << SYSC_CLOCKACTIVITY_SHIFT)
#define SYSC_TYPE1_SIDLEMODE_SHIFT	3
#define SYSC_TYPE1_SIDLEMODE_MASK	(0x3 << SYSC_SIDLEMODE_SHIFT)
#define SYSC_TYPE1_ENAWAKEUP_SHIFT	2
#define SYSC_TYPE1_ENAWAKEUP_MASK	(1 << SYSC_ENAWAKEUP_SHIFT)
#define SYSC_TYPE1_SOFTRESET_SHIFT	1
#define SYSC_TYPE1_SOFTRESET_MASK	(1 << SYSC_SOFTRESET_SHIFT)
#define SYSC_TYPE1_AUTOIDLE_SHIFT	0
#define SYSC_TYPE1_AUTOIDLE_MASK	(1 << SYSC_AUTOIDLE_SHIFT)

/*
 * OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant
 * with the new PRCM protocol defined for new OMAP4 IPs.
 */
#define SYSC_TYPE2_SOFTRESET_SHIFT	0
#define SYSC_TYPE2_SOFTRESET_MASK	(1 << SYSC_TYPE2_SOFTRESET_SHIFT)
#define SYSC_TYPE2_SIDLEMODE_SHIFT	2
#define SYSC_TYPE2_SIDLEMODE_MASK	(0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT)
#define SYSC_TYPE2_MIDLEMODE_SHIFT	4
#define SYSC_TYPE2_MIDLEMODE_MASK	(0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT)

/* OCP SYSSTATUS bit shifts/masks */
#define SYSS_RESETDONE_SHIFT		0
#define SYSS_RESETDONE_MASK		(1 << SYSS_RESETDONE_SHIFT)

/* Master standby/slave idle mode flags */
#define HWMOD_IDLEMODE_FORCE		(1 << 0)
#define HWMOD_IDLEMODE_NO		(1 << 1)
#define HWMOD_IDLEMODE_SMART		(1 << 2)

/**
 * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
 * @name: name of the IRQ channel (module local name)
 * @irq_ch: IRQ channel ID
 *
 * @name should be something short, e.g., "tx" or "rx".  It is for use
 * by platform_get_resource_byname().  It is defined locally to the
 * hwmod.
 */
struct omap_hwmod_irq_info {
	const char	*name;
	u16		irq;
};

/**
 * struct omap_hwmod_dma_info - DMA channels used by the hwmod
 * @name: name of the DMA channel (module local name)
 * @dma_ch: DMA channel ID
 *
 * @name should be something short, e.g., "tx" or "rx".  It is for use
 * by platform_get_resource_byname().  It is defined locally to the
 * hwmod.
 */
struct omap_hwmod_dma_info {
	const char	*name;
	u16		dma_ch;
};

/**
 * struct omap_hwmod_opt_clk - optional clocks used by this hwmod
 * @role: "sys", "32k", "tv", etc -- for use in clk_get()
 * @clkdev_dev_id: opt clock: clkdev dev_id string
 * @clkdev_con_id: opt clock: clkdev con_id string
 * @_clk: pointer to the struct clk (filled in at runtime)
 *
 * The module's interface clock and main functional clock should not
 * be added as optional clocks.
 */
struct omap_hwmod_opt_clk {
	const char	*role;
	const char	*clkdev_dev_id;
	const char	*clkdev_con_id;
	struct clk	*_clk;
};


/* omap_hwmod_omap2_firewall.flags bits */
#define OMAP_FIREWALL_L3		(1 << 0)
#define OMAP_FIREWALL_L4		(1 << 1)

/**
 * struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data
 * @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_*
 * @l4_fw_region: L4 firewall region ID
 * @l4_prot_group: L4 protection group ID
 * @flags: (see omap_hwmod_omap2_firewall.flags macros above)
 */
struct omap_hwmod_omap2_firewall {
	u8 l3_perm_bit;
	u8 l4_fw_region;
	u8 l4_prot_group;
	u8 flags;
};


/*
 * omap_hwmod_addr_space.flags bits
 *
 * ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init.
 * ADDR_TYPE_RT: Address space contains module register target data.
 */
#define ADDR_MAP_ON_INIT	(1 << 0)
#define ADDR_TYPE_RT		(1 << 1)

/**
 * struct omap_hwmod_addr_space - MPU address space handled by the hwmod
 * @pa_start: starting physical address
 * @pa_end: ending physical address
 * @flags: (see omap_hwmod_addr_space.flags macros above)
 *
 * Address space doesn't necessarily follow physical interconnect
 * structure.  GPMC is one example.
 */
struct omap_hwmod_addr_space {
	u32 pa_start;
	u32 pa_end;
	u8 flags;
};


/*
 * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this
 * interface to interact with the hwmod.  Used to add sleep dependencies
 * when the module is enabled or disabled.
 */
#define OCP_USER_MPU			(1 << 0)
#define OCP_USER_SDMA			(1 << 1)

/* omap_hwmod_ocp_if.flags bits */
#define OCPIF_HAS_IDLEST		(1 << 0)
#define OCPIF_SWSUP_IDLE		(1 << 1)
#define OCPIF_CAN_BURST			(1 << 2)

/**
 * struct omap_hwmod_ocp_if - OCP interface data
 * @master: struct omap_hwmod that initiates OCP transactions on this link
 * @slave: struct omap_hwmod that responds to OCP transactions on this link
 * @addr: address space associated with this link
 * @clkdev_dev_id: interface clock: clkdev dev_id string
 * @clkdev_con_id: interface clock: clkdev con_id string
 * @_clk: pointer to the interface struct clk (filled in at runtime)
 * @fw: interface firewall data
 * @addr_cnt: ARRAY_SIZE(@addr)
 * @width: OCP data width
 * @thread_cnt: number of threads
 * @max_burst_len: maximum burst length in @width sized words (0 if unlimited)
 * @user: initiators using this interface (see OCP_USER_* macros above)
 * @flags: OCP interface flags (see OCPIF_* macros above)
 *
 * It may also be useful to add a tag_cnt field for OCP2.x devices.
 *
 * Parameter names beginning with an underscore are managed internally by
 * the omap_hwmod code and should not be set during initialization.
 */
struct omap_hwmod_ocp_if {
	struct omap_hwmod		*master;
	struct omap_hwmod		*slave;
	struct omap_hwmod_addr_space	*addr;
	const char			*clkdev_dev_id;
	const char			*clkdev_con_id;
	struct clk			*_clk;
	union {
		struct omap_hwmod_omap2_firewall omap2;
	}				fw;
	u8				addr_cnt;
	u8				width;
	u8				thread_cnt;
	u8				max_burst_len;
	u8				user;
	u8				flags;
};


/* Macros for use in struct omap_hwmod_sysconfig */

/* Flags for use in omap_hwmod_sysconfig.idlemodes */
#define MASTER_STANDBY_SHIFT	2
#define SLAVE_IDLE_SHIFT	0
#define SIDLE_FORCE		(HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT)
#define SIDLE_NO		(HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT)
#define SIDLE_SMART		(HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT)
#define MSTANDBY_FORCE		(HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
#define MSTANDBY_NO		(HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
#define MSTANDBY_SMART		(HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)

/* omap_hwmod_sysconfig.sysc_flags capability flags */
#define SYSC_HAS_AUTOIDLE	(1 << 0)
#define SYSC_HAS_SOFTRESET	(1 << 1)
#define SYSC_HAS_ENAWAKEUP	(1 << 2)
#define SYSC_HAS_EMUFREE	(1 << 3)
#define SYSC_HAS_CLOCKACTIVITY	(1 << 4)
#define SYSC_HAS_SIDLEMODE	(1 << 5)
#define SYSC_HAS_MIDLEMODE	(1 << 6)
#define SYSS_MISSING		(1 << 7)
#define SYSC_NO_CACHE		(1 << 8)  /* XXX SW flag, belongs elsewhere */

/* omap_hwmod_sysconfig.clockact flags */
#define CLOCKACT_TEST_BOTH	0x0
#define CLOCKACT_TEST_MAIN	0x1
#define CLOCKACT_TEST_ICLK	0x2
#define CLOCKACT_TEST_NONE	0x3

/**
 * struct omap_hwmod_sysc_fields - hwmod OCP_SYSCONFIG register field offsets.
 * @midle_shift: Offset of the midle bit
 * @clkact_shift: Offset of the clockactivity bit
 * @sidle_shift: Offset of the sidle bit
 * @enwkup_shift: Offset of the enawakeup bit
 * @srst_shift: Offset of the softreset bit
 * @autoidle_shift: Offset of the autoidle bit.
 */
struct omap_hwmod_sysc_fields {
	u8 midle_shift;
	u8 clkact_shift;
	u8 sidle_shift;
	u8 enwkup_shift;
	u8 srst_shift;
	u8 autoidle_shift;
};

/**
 * struct omap_hwmod_sysconfig - hwmod OCP_SYSCONFIG/OCP_SYSSTATUS data
 * @rev_offs: IP block revision register offset (from module base addr)
 * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
 * @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
 * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
 * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
 * @clockact: the default value of the module CLOCKACTIVITY bits
 *
 * @clockact describes to the module which clocks are likely to be
 * disabled when the PRCM issues its idle request to the module.  Some
 * modules have separate clockdomains for the interface clock and main
 * functional clock, and can check whether they should acknowledge the
 * idle request based on the internal module functionality that has
 * been associated with the clocks marked in @clockact.  This field is
 * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below)
 *
 *
 * @sysc_fields: structure containing the offset positions of various bits in
 * SYSCONFIG register. This can be populated using omap_hwmod_sysc_type1 or
 * omap_hwmod_sysc_type2 defined in omap_hwmod_common_data.c depending on
 * whether the device ip is compliant with the original PRCM protocol
 * defined for OMAP2420 or the new  PRCM protocol for new OMAP4 IPs.
 * If the device follows a differnt scheme for the sysconfig register ,
 * then this field has to be populated with the correct offset structure.
 */
struct omap_hwmod_sysconfig {
	u16 rev_offs;
	u16 sysc_offs;
	u16 syss_offs;
	u8 idlemodes;
	u8 sysc_flags;
	u8 clockact;
	struct omap_hwmod_sysc_fields *sysc_fields;
};

/**
 * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data
 * @module_offs: PRCM submodule offset from the start of the PRM/CM
 * @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3)
 * @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs
 * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3)
 * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit
 * @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit
 *
 * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST,
 * WKEN, GRPSEL registers.  In an ideal world, no extra information
 * would be needed for IDLEST information, but alas, there are some
 * exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit
 * are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST)
 */
struct omap_hwmod_omap2_prcm {
	s16 module_offs;
	u8 prcm_reg_id;
	u8 module_bit;
	u8 idlest_reg_id;
	u8 idlest_idle_bit;
	u8 idlest_stdby_bit;
};


/**
 * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
 * @module_offs: PRCM submodule offset from the start of the PRM/CM1/CM2
 * @device_offs: device register offset from @module_offs
 * @submodule_wkdep_bit: bit shift of the WKDEP range
 */
struct omap_hwmod_omap4_prcm {
	u32 module_offs;
	u16 device_offs;
	u8 submodule_wkdep_bit;
};


/*
 * omap_hwmod.flags definitions
 *
 * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
 *     of idle, rather than relying on module smart-idle
 * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out
 *     of standby, rather than relying on module smart-standby
 * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
 *     SDRAM controller, etc.
 * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
 *     controller, etc.
 * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
 *     when module is enabled, rather than the default, which is to
 *     enable autoidle
 * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
 */
#define HWMOD_SWSUP_SIDLE			(1 << 0)
#define HWMOD_SWSUP_MSTANDBY			(1 << 1)
#define HWMOD_INIT_NO_RESET			(1 << 2)
#define HWMOD_INIT_NO_IDLE			(1 << 3)
#define HWMOD_NO_OCP_AUTOIDLE			(1 << 4)
#define HWMOD_SET_DEFAULT_CLOCKACT		(1 << 5)

/*
 * omap_hwmod._int_flags definitions
 * These are for internal use only and are managed by the omap_hwmod code.
 *
 * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
 * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP
 * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
 */
#define _HWMOD_NO_MPU_PORT			(1 << 0)
#define _HWMOD_WAKEUP_ENABLED			(1 << 1)
#define _HWMOD_SYSCONFIG_LOADED			(1 << 2)

/*
 * omap_hwmod._state definitions
 *
 * INITIALIZED: reset (optionally), initialized, enabled, disabled
 *              (optionally)
 *
 *
 */
#define _HWMOD_STATE_UNKNOWN			0
#define _HWMOD_STATE_REGISTERED			1
#define _HWMOD_STATE_CLKS_INITED		2
#define _HWMOD_STATE_INITIALIZED		3
#define _HWMOD_STATE_ENABLED			4
#define _HWMOD_STATE_IDLE			5
#define _HWMOD_STATE_DISABLED			6

/**
 * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
 * @name: name of the hwmod
 * @od: struct omap_device currently associated with this hwmod (internal use)
 * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt)
 * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt)
 * @prcm: PRCM data pertaining to this hwmod
 * @clkdev_dev_id: main clock: clkdev dev_id string
 * @clkdev_con_id: main clock: clkdev con_id string
 * @_clk: pointer to the main struct clk (filled in at runtime)
 * @opt_clks: other device clocks that drivers can request (0..*)
 * @masters: ptr to array of OCP ifs that this hwmod can initiate on
 * @slaves: ptr to array of OCP ifs that this hwmod can respond on
 * @sysconfig: device SYSCONFIG/SYSSTATUS register data
 * @dev_attr: arbitrary device attributes that can be passed to the driver
 * @_sysc_cache: internal-use hwmod flags
 * @_rt_va: cached register target start address (internal use)
 * @_mpu_port_index: cached MPU register target slave ID (internal use)
 * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6)
 * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift
 * @mpu_irqs_cnt: number of @mpu_irqs
 * @sdma_chs_cnt: number of @sdma_chs
 * @opt_clks_cnt: number of @opt_clks
 * @master_cnt: number of @master entries
 * @slaves_cnt: number of @slave entries
 * @response_lat: device OCP response latency (in interface clock cycles)
 * @_int_flags: internal-use hwmod flags
 * @_state: internal-use hwmod state
 * @flags: hwmod flags (documented below)
 * @omap_chip: OMAP chips this hwmod is present on
 * @node: list node for hwmod list (internal use)
 *
 * @clkdev_dev_id, @clkdev_con_id, and @clk all refer to this module's "main
 * clock," which for our purposes is defined as "the functional clock needed
 * for register accesses to complete."  Modules may not have a main clock if
 * the interface clock also serves as a main clock.
 *
 * Parameter names beginning with an underscore are managed internally by
 * the omap_hwmod code and should not be set during initialization.
 */
struct omap_hwmod {
	const char			*name;
	struct omap_device		*od;
	struct omap_hwmod_irq_info	*mpu_irqs;
	struct omap_hwmod_dma_info	*sdma_chs;
	union {
		struct omap_hwmod_omap2_prcm omap2;
		struct omap_hwmod_omap4_prcm omap4;
	}				prcm;
	const char			*clkdev_dev_id;
	const char			*clkdev_con_id;
	struct clk			*_clk;
	struct omap_hwmod_opt_clk	*opt_clks;
	struct omap_hwmod_ocp_if	**masters; /* connect to *_IA */
	struct omap_hwmod_ocp_if	**slaves;  /* connect to *_TA */
	struct omap_hwmod_sysconfig	*sysconfig;
	void				*dev_attr;
	u32				_sysc_cache;
	void __iomem			*_rt_va;
	struct list_head		node;
	u16				flags;
	u8				_mpu_port_index;
	u8				msuspendmux_reg_id;
	u8				msuspendmux_shift;
	u8				response_lat;
	u8				mpu_irqs_cnt;
	u8				sdma_chs_cnt;
	u8				opt_clks_cnt;
	u8				masters_cnt;
	u8				slaves_cnt;
	u8				hwmods_cnt;
	u8				_int_flags;
	u8				_state;
	const struct omap_chip_id	omap_chip;
};

int omap_hwmod_init(struct omap_hwmod **ohs);
int omap_hwmod_register(struct omap_hwmod *oh);
int omap_hwmod_unregister(struct omap_hwmod *oh);
struct omap_hwmod *omap_hwmod_lookup(const char *name);
int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh));
int omap_hwmod_late_init(void);

int omap_hwmod_enable(struct omap_hwmod *oh);
int omap_hwmod_idle(struct omap_hwmod *oh);
int omap_hwmod_shutdown(struct omap_hwmod *oh);

int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
int omap_hwmod_disable_clocks(struct omap_hwmod *oh);

int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode);

int omap_hwmod_reset(struct omap_hwmod *oh);
void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);

void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs);
u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs);

int omap_hwmod_count_resources(struct omap_hwmod *oh);
int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);

struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);

int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
				 struct omap_hwmod *init_oh);
int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
				 struct omap_hwmod *init_oh);

int omap_hwmod_set_clockact_both(struct omap_hwmod *oh);
int omap_hwmod_set_clockact_main(struct omap_hwmod *oh);
int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh);
int omap_hwmod_set_clockact_none(struct omap_hwmod *oh);

int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);

#endif
Commit	Line	Data
63c85238 PW	1	/*
	2	* omap_hwmod macros, structures
	3	*
	4	* Copyright (C) 2009 Nokia Corporation
	5	* Paul Walmsley
	6	*
	7	* Created in collaboration with (alphabetical order): Benoit Cousson,
	8	* Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari
	9	* Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*
	15	* These headers and macros are used to define OMAP on-chip module
	16	* data and their integration with other OMAP modules and Linux.
	17	*
	18	* References:
	19	* - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
	20	* - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
	21	* - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
	22	* - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140)
	23	* - Open Core Protocol Specification 2.2
	24	*
	25	* To do:
	26	* - add interconnect error log structures
	27	* - add pinmuxing
	28	* - init_conn_id_bit (CONNID_BIT_VECTOR)
	29	* - implement default hwmod SMS/SDRC flags?
	30	*
	31	*/
	32	#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
	33	#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
	34
	35	#include <linux/kernel.h>
358f0e63	36	#include <linux/list.h>
63c85238	37	#include <linux/ioport.h>
ce491cf8	38	#include <plat/cpu.h>
63c85238 PW	39
	40	struct omap_device;
	41
358f0e63 TG	42	extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1;
	43	extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
	44
	45	/*
	46	* OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant
	47	* with the original PRCM protocol defined for OMAP2420
	48	*/
	49	#define SYSC_TYPE1_MIDLEMODE_SHIFT 12
	50	#define SYSC_TYPE1_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT)
	51	#define SYSC_TYPE1_CLOCKACTIVITY_SHIFT 8
	52	#define SYSC_TYPE1_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT)
	53	#define SYSC_TYPE1_SIDLEMODE_SHIFT 3
	54	#define SYSC_TYPE1_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT)
	55	#define SYSC_TYPE1_ENAWAKEUP_SHIFT 2
	56	#define SYSC_TYPE1_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT)
	57	#define SYSC_TYPE1_SOFTRESET_SHIFT 1
	58	#define SYSC_TYPE1_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT)
	59	#define SYSC_TYPE1_AUTOIDLE_SHIFT 0
	60	#define SYSC_TYPE1_AUTOIDLE_MASK (1 << SYSC_AUTOIDLE_SHIFT)
	61
	62	/*
	63	* OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant
	64	* with the new PRCM protocol defined for new OMAP4 IPs.
	65	*/
	66	#define SYSC_TYPE2_SOFTRESET_SHIFT 0
	67	#define SYSC_TYPE2_SOFTRESET_MASK (1 << SYSC_TYPE2_SOFTRESET_SHIFT)
	68	#define SYSC_TYPE2_SIDLEMODE_SHIFT 2
	69	#define SYSC_TYPE2_SIDLEMODE_MASK (0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT)
	70	#define SYSC_TYPE2_MIDLEMODE_SHIFT 4
	71	#define SYSC_TYPE2_MIDLEMODE_MASK (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT)
63c85238 PW	72
	73	/* OCP SYSSTATUS bit shifts/masks */
	74	#define SYSS_RESETDONE_SHIFT 0
	75	#define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT)
	76
	77	/* Master standby/slave idle mode flags */
	78	#define HWMOD_IDLEMODE_FORCE (1 << 0)
	79	#define HWMOD_IDLEMODE_NO (1 << 1)
	80	#define HWMOD_IDLEMODE_SMART (1 << 2)
	81
63c85238	82	/**
718bfd76 PW	83	* struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
	84	* @name: name of the IRQ channel (module local name)
	85	* @irq_ch: IRQ channel ID
	86	*
	87	* @name should be something short, e.g., "tx" or "rx". It is for use
	88	* by platform_get_resource_byname(). It is defined locally to the
	89	* hwmod.
	90	*/
	91	struct omap_hwmod_irq_info {
	92	const char *name;
	93	u16 irq;
	94	};
	95
	96	/**
	97	* struct omap_hwmod_dma_info - DMA channels used by the hwmod
63c85238 PW	98	* @name: name of the DMA channel (module local name)
	99	* @dma_ch: DMA channel ID
	100	*
	101	* @name should be something short, e.g., "tx" or "rx". It is for use
	102	* by platform_get_resource_byname(). It is defined locally to the
	103	* hwmod.
	104	*/
	105	struct omap_hwmod_dma_info {
	106	const char *name;
	107	u16 dma_ch;
	108	};
	109
	110	/**
	111	* struct omap_hwmod_opt_clk - optional clocks used by this hwmod
	112	* @role: "sys", "32k", "tv", etc -- for use in clk_get()
	113	* @clkdev_dev_id: opt clock: clkdev dev_id string
	114	* @clkdev_con_id: opt clock: clkdev con_id string
	115	* @_clk: pointer to the struct clk (filled in at runtime)
	116	*
	117	* The module's interface clock and main functional clock should not
	118	* be added as optional clocks.
	119	*/
	120	struct omap_hwmod_opt_clk {
	121	const char *role;
	122	const char *clkdev_dev_id;
	123	const char *clkdev_con_id;
	124	struct clk *_clk;
	125	};
	126
	127
	128	/* omap_hwmod_omap2_firewall.flags bits */
	129	#define OMAP_FIREWALL_L3 (1 << 0)
	130	#define OMAP_FIREWALL_L4 (1 << 1)
	131
	132	/**
	133	* struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data
	134	* @l3_perm_bit: bit shift for L3_PM__PERMISSION_
	135	* @l4_fw_region: L4 firewall region ID
	136	* @l4_prot_group: L4 protection group ID
	137	* @flags: (see omap_hwmod_omap2_firewall.flags macros above)
	138	*/
	139	struct omap_hwmod_omap2_firewall {
	140	u8 l3_perm_bit;
	141	u8 l4_fw_region;
	142	u8 l4_prot_group;
	143	u8 flags;
	144	};
	145
	146
	147	/*
	148	* omap_hwmod_addr_space.flags bits
	149	*
	150	* ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init.
	151	* ADDR_TYPE_RT: Address space contains module register target data.
	152	*/
	153	#define ADDR_MAP_ON_INIT (1 << 0)
	154	#define ADDR_TYPE_RT (1 << 1)
	155
	156	/**
	157	* struct omap_hwmod_addr_space - MPU address space handled by the hwmod
	158	* @pa_start: starting physical address
	159	* @pa_end: ending physical address
	160	* @flags: (see omap_hwmod_addr_space.flags macros above)
	161	*
162	* Address space doesn't necessarily follow physical interconnect
163	* structure. GPMC is one example.
164	*/
165	struct omap_hwmod_addr_space {
166	u32 pa_start;
167	u32 pa_end;
168	u8 flags;
169	};
170
171
172	/*
173	* omap_hwmod_ocp_if.user bits: these indicate the initiators that use this
174	* interface to interact with the hwmod. Used to add sleep dependencies
175	* when the module is enabled or disabled.
176	*/
177	#define OCP_USER_MPU (1 << 0)
178	#define OCP_USER_SDMA (1 << 1)
179
180	/* omap_hwmod_ocp_if.flags bits */
181	#define OCPIF_HAS_IDLEST (1 << 0)
182	#define OCPIF_SWSUP_IDLE (1 << 1)
183	#define OCPIF_CAN_BURST (1 << 2)
184
185	/**
186	* struct omap_hwmod_ocp_if - OCP interface data
187	* @master: struct omap_hwmod that initiates OCP transactions on this link
188	* @slave: struct omap_hwmod that responds to OCP transactions on this link
189	* @addr: address space associated with this link
190	* @clkdev_dev_id: interface clock: clkdev dev_id string
191	* @clkdev_con_id: interface clock: clkdev con_id string
192	* @_clk: pointer to the interface struct clk (filled in at runtime)
193	* @fw: interface firewall data
194	* @addr_cnt: ARRAY_SIZE(@addr)
195	* @width: OCP data width
196	* @thread_cnt: number of threads
197	* @max_burst_len: maximum burst length in @width sized words (0 if unlimited)
198	* @user: initiators using this interface (see OCP_USER_* macros above)
199	* @flags: OCP interface flags (see OCPIF_* macros above)
200	*
201	* It may also be useful to add a tag_cnt field for OCP2.x devices.
202	*
203	* Parameter names beginning with an underscore are managed internally by
204	* the omap_hwmod code and should not be set during initialization.
205	*/
206	struct omap_hwmod_ocp_if {
207	struct omap_hwmod *master;
208	struct omap_hwmod *slave;
209	struct omap_hwmod_addr_space *addr;
210	const char *clkdev_dev_id;
211	const char *clkdev_con_id;
212	struct clk *_clk;
213	union {
214	struct omap_hwmod_omap2_firewall omap2;
215	} fw;
216	u8 addr_cnt;
217	u8 width;
218	u8 thread_cnt;
219	u8 max_burst_len;
220	u8 user;
221	u8 flags;
222	};
223
224
225	/* Macros for use in struct omap_hwmod_sysconfig */
226
227	/* Flags for use in omap_hwmod_sysconfig.idlemodes */
228	#define MASTER_STANDBY_SHIFT 2
229	#define SLAVE_IDLE_SHIFT 0
230	#define SIDLE_FORCE (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT)
231	#define SIDLE_NO (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT)
232	#define SIDLE_SMART (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT)
233	#define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
234	#define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
235	#define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
236
237	/* omap_hwmod_sysconfig.sysc_flags capability flags */
238	#define SYSC_HAS_AUTOIDLE (1 << 0)
239	#define SYSC_HAS_SOFTRESET (1 << 1)
240	#define SYSC_HAS_ENAWAKEUP (1 << 2)
241	#define SYSC_HAS_EMUFREE (1 << 3)
242	#define SYSC_HAS_CLOCKACTIVITY (1 << 4)
243	#define SYSC_HAS_SIDLEMODE (1 << 5)
244	#define SYSC_HAS_MIDLEMODE (1 << 6)
245	#define SYSS_MISSING (1 << 7)
883edfdd	246	#define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */
63c85238 PW	247
	248	/* omap_hwmod_sysconfig.clockact flags */
	249	#define CLOCKACT_TEST_BOTH 0x0
	250	#define CLOCKACT_TEST_MAIN 0x1
	251	#define CLOCKACT_TEST_ICLK 0x2
	252	#define CLOCKACT_TEST_NONE 0x3
	253
358f0e63 TG	254	/**
	255	* struct omap_hwmod_sysc_fields - hwmod OCP_SYSCONFIG register field offsets.
	256	* @midle_shift: Offset of the midle bit
	257	* @clkact_shift: Offset of the clockactivity bit
	258	* @sidle_shift: Offset of the sidle bit
	259	* @enwkup_shift: Offset of the enawakeup bit
	260	* @srst_shift: Offset of the softreset bit
	261	* @autoidle_shift: Offset of the autoidle bit.
	262	*/
	263	struct omap_hwmod_sysc_fields {
	264	u8 midle_shift;
	265	u8 clkact_shift;
	266	u8 sidle_shift;
	267	u8 enwkup_shift;
	268	u8 srst_shift;
	269	u8 autoidle_shift;
	270	};
	271
63c85238 PW	272	/**
	273	* struct omap_hwmod_sysconfig - hwmod OCP_SYSCONFIG/OCP_SYSSTATUS data
	274	* @rev_offs: IP block revision register offset (from module base addr)
	275	* @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
	276	* @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
	277	* @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
	278	* @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
	279	* @clockact: the default value of the module CLOCKACTIVITY bits
	280	*
	281	* @clockact describes to the module which clocks are likely to be
	282	* disabled when the PRCM issues its idle request to the module. Some
	283	* modules have separate clockdomains for the interface clock and main
	284	* functional clock, and can check whether they should acknowledge the
	285	* idle request based on the internal module functionality that has
	286	* been associated with the clocks marked in @clockact. This field is
	287	* only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below)
	288	*
358f0e63 TG	289	*
	290	* @sysc_fields: structure containing the offset positions of various bits in
	291	* SYSCONFIG register. This can be populated using omap_hwmod_sysc_type1 or
	292	* omap_hwmod_sysc_type2 defined in omap_hwmod_common_data.c depending on
	293	* whether the device ip is compliant with the original PRCM protocol
	294	* defined for OMAP2420 or the new PRCM protocol for new OMAP4 IPs.
	295	* If the device follows a differnt scheme for the sysconfig register ,
	296	* then this field has to be populated with the correct offset structure.
63c85238 PW	297	*/
	298	struct omap_hwmod_sysconfig {
	299	u16 rev_offs;
	300	u16 sysc_offs;
	301	u16 syss_offs;
	302	u8 idlemodes;
	303	u8 sysc_flags;
	304	u8 clockact;
358f0e63	305	struct omap_hwmod_sysc_fields *sysc_fields;
63c85238 PW	306	};
	307
	308	/**
	309	* struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data
	310	* @module_offs: PRCM submodule offset from the start of the PRM/CM
	311	* @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3)
	312	* @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs
	313	* @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3)
	314	* @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit
	315	* @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit
	316	*
	317	* @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST,
	318	* WKEN, GRPSEL registers. In an ideal world, no extra information
	319	* would be needed for IDLEST information, but alas, there are some
	320	* exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit
	321	* are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST)
	322	*/
	323	struct omap_hwmod_omap2_prcm {
	324	s16 module_offs;
	325	u8 prcm_reg_id;
	326	u8 module_bit;
	327	u8 idlest_reg_id;
	328	u8 idlest_idle_bit;
	329	u8 idlest_stdby_bit;
	330	};
	331
	332
	333	/**
	334	* struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
	335	* @module_offs: PRCM submodule offset from the start of the PRM/CM1/CM2
	336	* @device_offs: device register offset from @module_offs
	337	* @submodule_wkdep_bit: bit shift of the WKDEP range
	338	*/
	339	struct omap_hwmod_omap4_prcm {
	340	u32 module_offs;
	341	u16 device_offs;
	342	u8 submodule_wkdep_bit;
	343	};
	344
	345
	346	/*
	347	* omap_hwmod.flags definitions
	348	*
	349	* HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
	350	* of idle, rather than relying on module smart-idle
	351	* HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out
	352	* of standby, rather than relying on module smart-standby
	353	* HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
	354	* SDRAM controller, etc.
	355	* HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
	356	* controller, etc.
726072e5 PW	357	* HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
	358	* when module is enabled, rather than the default, which is to
	359	* enable autoidle
63c85238 PW	360	* HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
	361	*/
	362	#define HWMOD_SWSUP_SIDLE (1 << 0)
	363	#define HWMOD_SWSUP_MSTANDBY (1 << 1)
	364	#define HWMOD_INIT_NO_RESET (1 << 2)
	365	#define HWMOD_INIT_NO_IDLE (1 << 3)
726072e5 PW	366	#define HWMOD_NO_OCP_AUTOIDLE (1 << 4)
726072e5 PW	367	#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5)
63c85238 PW	368
	369	/*
	370	* omap_hwmod._int_flags definitions
	371	* These are for internal use only and are managed by the omap_hwmod code.
	372	*
	373	* _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
	374	* _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP
	375	* _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
	376	*/
	377	#define _HWMOD_NO_MPU_PORT (1 << 0)
	378	#define _HWMOD_WAKEUP_ENABLED (1 << 1)
	379	#define _HWMOD_SYSCONFIG_LOADED (1 << 2)
	380
	381	/*
	382	* omap_hwmod._state definitions
	383	*
	384	* INITIALIZED: reset (optionally), initialized, enabled, disabled
	385	* (optionally)
	386	*
	387	*
	388	*/
	389	#define _HWMOD_STATE_UNKNOWN 0
	390	#define _HWMOD_STATE_REGISTERED 1
	391	#define _HWMOD_STATE_CLKS_INITED 2
	392	#define _HWMOD_STATE_INITIALIZED 3
	393	#define _HWMOD_STATE_ENABLED 4
	394	#define _HWMOD_STATE_IDLE 5
	395	#define _HWMOD_STATE_DISABLED 6
	396
	397	/**
	398	* struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
	399	* @name: name of the hwmod
	400	* @od: struct omap_device currently associated with this hwmod (internal use)
	401	* @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt)
	402	* @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt)
	403	* @prcm: PRCM data pertaining to this hwmod
	404	* @clkdev_dev_id: main clock: clkdev dev_id string
	405	* @clkdev_con_id: main clock: clkdev con_id string
	406	* @_clk: pointer to the main struct clk (filled in at runtime)
	407	* @opt_clks: other device clocks that drivers can request (0..*)
	408	* @masters: ptr to array of OCP ifs that this hwmod can initiate on
	409	* @slaves: ptr to array of OCP ifs that this hwmod can respond on
	410	* @sysconfig: device SYSCONFIG/SYSSTATUS register data
	411	* @dev_attr: arbitrary device attributes that can be passed to the driver
	412	* @_sysc_cache: internal-use hwmod flags
	413	* @_rt_va: cached register target start address (internal use)
	414	* @_mpu_port_index: cached MPU register target slave ID (internal use)
	415	* @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6)
	416	* @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift
	417	* @mpu_irqs_cnt: number of @mpu_irqs
	418	* @sdma_chs_cnt: number of @sdma_chs
	419	* @opt_clks_cnt: number of @opt_clks
	420	* @master_cnt: number of @master entries
	421	* @slaves_cnt: number of @slave entries
	422	* @response_lat: device OCP response latency (in interface clock cycles)
	423	* @_int_flags: internal-use hwmod flags
	424	* @_state: internal-use hwmod state
	425	* @flags: hwmod flags (documented below)
	426	* @omap_chip: OMAP chips this hwmod is present on
	427	* @node: list node for hwmod list (internal use)
	428	*
	429	* @clkdev_dev_id, @clkdev_con_id, and @clk all refer to this module's "main
	430	* clock," which for our purposes is defined as "the functional clock needed
	431	* for register accesses to complete." Modules may not have a main clock if
432	* the interface clock also serves as a main clock.
433	*
434	* Parameter names beginning with an underscore are managed internally by
435	* the omap_hwmod code and should not be set during initialization.
436	*/
437	struct omap_hwmod {
438	const char *name;
439	struct omap_device *od;
718bfd76	440	struct omap_hwmod_irq_info *mpu_irqs;
63c85238 PW	441	struct omap_hwmod_dma_info *sdma_chs;
	442	union {
	443	struct omap_hwmod_omap2_prcm omap2;
	444	struct omap_hwmod_omap4_prcm omap4;
	445	} prcm;
	446	const char *clkdev_dev_id;
	447	const char *clkdev_con_id;
	448	struct clk *_clk;
	449	struct omap_hwmod_opt_clk *opt_clks;
	450	struct omap_hwmod_ocp_if *masters; / connect to _IA /
	451	struct omap_hwmod_ocp_if *slaves; / connect to _TA /
	452	struct omap_hwmod_sysconfig *sysconfig;
	453	void *dev_attr;
	454	u32 _sysc_cache;
	455	void __iomem *_rt_va;
	456	struct list_head node;
	457	u16 flags;
	458	u8 _mpu_port_index;
	459	u8 msuspendmux_reg_id;
	460	u8 msuspendmux_shift;
	461	u8 response_lat;
	462	u8 mpu_irqs_cnt;
	463	u8 sdma_chs_cnt;
	464	u8 opt_clks_cnt;
	465	u8 masters_cnt;
	466	u8 slaves_cnt;
	467	u8 hwmods_cnt;
	468	u8 _int_flags;
	469	u8 _state;
	470	const struct omap_chip_id omap_chip;
	471	};
	472
	473	int omap_hwmod_init(struct omap_hwmod **ohs);
	474	int omap_hwmod_register(struct omap_hwmod *oh);
	475	int omap_hwmod_unregister(struct omap_hwmod *oh);
	476	struct omap_hwmod omap_hwmod_lookup(const char name);
	477	int omap_hwmod_for_each(int (fn)(struct omap_hwmod oh));
	478	int omap_hwmod_late_init(void);
	479
	480	int omap_hwmod_enable(struct omap_hwmod *oh);
	481	int omap_hwmod_idle(struct omap_hwmod *oh);
	482	int omap_hwmod_shutdown(struct omap_hwmod *oh);
	483
	484	int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
	485	int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
	486
46273e6f KH	487	int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode);
46273e6f KH	488
63c85238 PW	489	int omap_hwmod_reset(struct omap_hwmod *oh);
	490	void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
	491
	492	void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs);
	493	u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs);
	494
	495	int omap_hwmod_count_resources(struct omap_hwmod *oh);
	496	int omap_hwmod_fill_resources(struct omap_hwmod oh, struct resource res);
	497
	498	struct powerdomain omap_hwmod_get_pwrdm(struct omap_hwmod oh);
	499
	500	int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
	501	struct omap_hwmod *init_oh);
	502	int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
	503	struct omap_hwmod *init_oh);
	504
	505	int omap_hwmod_set_clockact_both(struct omap_hwmod *oh);
	506	int omap_hwmod_set_clockact_main(struct omap_hwmod *oh);
	507	int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh);
	508	int omap_hwmod_set_clockact_none(struct omap_hwmod *oh);
	509
	510	int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
	511	int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
	512
	513	#endif