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63c85238 PW |
1 | /* |
2 | * omap_hwmod macros, structures | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Paul Walmsley | |
6 | * | |
43b40992 | 7 | * Created in collaboration with (alphabetical order): BenoƮt Cousson, |
63c85238 PW |
8 | * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari |
9 | * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
15 | * These headers and macros are used to define OMAP on-chip module | |
16 | * data and their integration with other OMAP modules and Linux. | |
17 | * | |
18 | * References: | |
19 | * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) | |
20 | * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) | |
21 | * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) | |
22 | * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) | |
23 | * - Open Core Protocol Specification 2.2 | |
24 | * | |
25 | * To do: | |
26 | * - add interconnect error log structures | |
27 | * - add pinmuxing | |
28 | * - init_conn_id_bit (CONNID_BIT_VECTOR) | |
29 | * - implement default hwmod SMS/SDRC flags? | |
30 | * | |
31 | */ | |
32 | #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H | |
33 | #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H | |
34 | ||
35 | #include <linux/kernel.h> | |
358f0e63 | 36 | #include <linux/list.h> |
63c85238 | 37 | #include <linux/ioport.h> |
ce491cf8 | 38 | #include <plat/cpu.h> |
63c85238 PW |
39 | |
40 | struct omap_device; | |
41 | ||
358f0e63 TG |
42 | extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1; |
43 | extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2; | |
44 | ||
45 | /* | |
46 | * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant | |
47 | * with the original PRCM protocol defined for OMAP2420 | |
48 | */ | |
49 | #define SYSC_TYPE1_MIDLEMODE_SHIFT 12 | |
50 | #define SYSC_TYPE1_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT) | |
51 | #define SYSC_TYPE1_CLOCKACTIVITY_SHIFT 8 | |
52 | #define SYSC_TYPE1_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT) | |
53 | #define SYSC_TYPE1_SIDLEMODE_SHIFT 3 | |
54 | #define SYSC_TYPE1_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT) | |
55 | #define SYSC_TYPE1_ENAWAKEUP_SHIFT 2 | |
56 | #define SYSC_TYPE1_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT) | |
57 | #define SYSC_TYPE1_SOFTRESET_SHIFT 1 | |
58 | #define SYSC_TYPE1_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT) | |
59 | #define SYSC_TYPE1_AUTOIDLE_SHIFT 0 | |
60 | #define SYSC_TYPE1_AUTOIDLE_MASK (1 << SYSC_AUTOIDLE_SHIFT) | |
61 | ||
62 | /* | |
63 | * OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant | |
64 | * with the new PRCM protocol defined for new OMAP4 IPs. | |
65 | */ | |
66 | #define SYSC_TYPE2_SOFTRESET_SHIFT 0 | |
67 | #define SYSC_TYPE2_SOFTRESET_MASK (1 << SYSC_TYPE2_SOFTRESET_SHIFT) | |
68 | #define SYSC_TYPE2_SIDLEMODE_SHIFT 2 | |
69 | #define SYSC_TYPE2_SIDLEMODE_MASK (0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT) | |
70 | #define SYSC_TYPE2_MIDLEMODE_SHIFT 4 | |
71 | #define SYSC_TYPE2_MIDLEMODE_MASK (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT) | |
63c85238 PW |
72 | |
73 | /* OCP SYSSTATUS bit shifts/masks */ | |
74 | #define SYSS_RESETDONE_SHIFT 0 | |
75 | #define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT) | |
76 | ||
77 | /* Master standby/slave idle mode flags */ | |
78 | #define HWMOD_IDLEMODE_FORCE (1 << 0) | |
79 | #define HWMOD_IDLEMODE_NO (1 << 1) | |
80 | #define HWMOD_IDLEMODE_SMART (1 << 2) | |
81 | ||
63c85238 | 82 | /** |
718bfd76 PW |
83 | * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod |
84 | * @name: name of the IRQ channel (module local name) | |
85 | * @irq_ch: IRQ channel ID | |
86 | * | |
87 | * @name should be something short, e.g., "tx" or "rx". It is for use | |
88 | * by platform_get_resource_byname(). It is defined locally to the | |
89 | * hwmod. | |
90 | */ | |
91 | struct omap_hwmod_irq_info { | |
92 | const char *name; | |
93 | u16 irq; | |
94 | }; | |
95 | ||
96 | /** | |
97 | * struct omap_hwmod_dma_info - DMA channels used by the hwmod | |
63c85238 PW |
98 | * @name: name of the DMA channel (module local name) |
99 | * @dma_ch: DMA channel ID | |
100 | * | |
101 | * @name should be something short, e.g., "tx" or "rx". It is for use | |
102 | * by platform_get_resource_byname(). It is defined locally to the | |
103 | * hwmod. | |
104 | */ | |
105 | struct omap_hwmod_dma_info { | |
106 | const char *name; | |
107 | u16 dma_ch; | |
108 | }; | |
109 | ||
110 | /** | |
111 | * struct omap_hwmod_opt_clk - optional clocks used by this hwmod | |
112 | * @role: "sys", "32k", "tv", etc -- for use in clk_get() | |
50ebdac2 | 113 | * @clk: opt clock: OMAP clock name |
63c85238 PW |
114 | * @_clk: pointer to the struct clk (filled in at runtime) |
115 | * | |
116 | * The module's interface clock and main functional clock should not | |
117 | * be added as optional clocks. | |
118 | */ | |
119 | struct omap_hwmod_opt_clk { | |
120 | const char *role; | |
50ebdac2 | 121 | const char *clk; |
63c85238 PW |
122 | struct clk *_clk; |
123 | }; | |
124 | ||
125 | ||
126 | /* omap_hwmod_omap2_firewall.flags bits */ | |
127 | #define OMAP_FIREWALL_L3 (1 << 0) | |
128 | #define OMAP_FIREWALL_L4 (1 << 1) | |
129 | ||
130 | /** | |
131 | * struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data | |
132 | * @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_* | |
133 | * @l4_fw_region: L4 firewall region ID | |
134 | * @l4_prot_group: L4 protection group ID | |
135 | * @flags: (see omap_hwmod_omap2_firewall.flags macros above) | |
136 | */ | |
137 | struct omap_hwmod_omap2_firewall { | |
138 | u8 l3_perm_bit; | |
139 | u8 l4_fw_region; | |
140 | u8 l4_prot_group; | |
141 | u8 flags; | |
142 | }; | |
143 | ||
144 | ||
145 | /* | |
146 | * omap_hwmod_addr_space.flags bits | |
147 | * | |
148 | * ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init. | |
149 | * ADDR_TYPE_RT: Address space contains module register target data. | |
150 | */ | |
151 | #define ADDR_MAP_ON_INIT (1 << 0) | |
152 | #define ADDR_TYPE_RT (1 << 1) | |
153 | ||
154 | /** | |
155 | * struct omap_hwmod_addr_space - MPU address space handled by the hwmod | |
156 | * @pa_start: starting physical address | |
157 | * @pa_end: ending physical address | |
158 | * @flags: (see omap_hwmod_addr_space.flags macros above) | |
159 | * | |
160 | * Address space doesn't necessarily follow physical interconnect | |
161 | * structure. GPMC is one example. | |
162 | */ | |
163 | struct omap_hwmod_addr_space { | |
164 | u32 pa_start; | |
165 | u32 pa_end; | |
166 | u8 flags; | |
167 | }; | |
168 | ||
169 | ||
170 | /* | |
171 | * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this | |
172 | * interface to interact with the hwmod. Used to add sleep dependencies | |
173 | * when the module is enabled or disabled. | |
174 | */ | |
175 | #define OCP_USER_MPU (1 << 0) | |
176 | #define OCP_USER_SDMA (1 << 1) | |
177 | ||
178 | /* omap_hwmod_ocp_if.flags bits */ | |
33f7ec81 BC |
179 | #define OCPIF_SWSUP_IDLE (1 << 0) |
180 | #define OCPIF_CAN_BURST (1 << 1) | |
63c85238 PW |
181 | |
182 | /** | |
183 | * struct omap_hwmod_ocp_if - OCP interface data | |
184 | * @master: struct omap_hwmod that initiates OCP transactions on this link | |
185 | * @slave: struct omap_hwmod that responds to OCP transactions on this link | |
186 | * @addr: address space associated with this link | |
50ebdac2 | 187 | * @clk: interface clock: OMAP clock name |
63c85238 PW |
188 | * @_clk: pointer to the interface struct clk (filled in at runtime) |
189 | * @fw: interface firewall data | |
190 | * @addr_cnt: ARRAY_SIZE(@addr) | |
191 | * @width: OCP data width | |
192 | * @thread_cnt: number of threads | |
193 | * @max_burst_len: maximum burst length in @width sized words (0 if unlimited) | |
194 | * @user: initiators using this interface (see OCP_USER_* macros above) | |
195 | * @flags: OCP interface flags (see OCPIF_* macros above) | |
196 | * | |
197 | * It may also be useful to add a tag_cnt field for OCP2.x devices. | |
198 | * | |
199 | * Parameter names beginning with an underscore are managed internally by | |
200 | * the omap_hwmod code and should not be set during initialization. | |
201 | */ | |
202 | struct omap_hwmod_ocp_if { | |
203 | struct omap_hwmod *master; | |
204 | struct omap_hwmod *slave; | |
205 | struct omap_hwmod_addr_space *addr; | |
50ebdac2 | 206 | const char *clk; |
63c85238 PW |
207 | struct clk *_clk; |
208 | union { | |
209 | struct omap_hwmod_omap2_firewall omap2; | |
210 | } fw; | |
211 | u8 addr_cnt; | |
212 | u8 width; | |
213 | u8 thread_cnt; | |
214 | u8 max_burst_len; | |
215 | u8 user; | |
216 | u8 flags; | |
217 | }; | |
218 | ||
219 | ||
220 | /* Macros for use in struct omap_hwmod_sysconfig */ | |
221 | ||
222 | /* Flags for use in omap_hwmod_sysconfig.idlemodes */ | |
223 | #define MASTER_STANDBY_SHIFT 2 | |
224 | #define SLAVE_IDLE_SHIFT 0 | |
225 | #define SIDLE_FORCE (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT) | |
226 | #define SIDLE_NO (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT) | |
227 | #define SIDLE_SMART (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT) | |
228 | #define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT) | |
229 | #define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT) | |
230 | #define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT) | |
231 | ||
232 | /* omap_hwmod_sysconfig.sysc_flags capability flags */ | |
233 | #define SYSC_HAS_AUTOIDLE (1 << 0) | |
234 | #define SYSC_HAS_SOFTRESET (1 << 1) | |
235 | #define SYSC_HAS_ENAWAKEUP (1 << 2) | |
236 | #define SYSC_HAS_EMUFREE (1 << 3) | |
237 | #define SYSC_HAS_CLOCKACTIVITY (1 << 4) | |
238 | #define SYSC_HAS_SIDLEMODE (1 << 5) | |
239 | #define SYSC_HAS_MIDLEMODE (1 << 6) | |
240 | #define SYSS_MISSING (1 << 7) | |
883edfdd | 241 | #define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */ |
63c85238 PW |
242 | |
243 | /* omap_hwmod_sysconfig.clockact flags */ | |
244 | #define CLOCKACT_TEST_BOTH 0x0 | |
245 | #define CLOCKACT_TEST_MAIN 0x1 | |
246 | #define CLOCKACT_TEST_ICLK 0x2 | |
247 | #define CLOCKACT_TEST_NONE 0x3 | |
248 | ||
358f0e63 TG |
249 | /** |
250 | * struct omap_hwmod_sysc_fields - hwmod OCP_SYSCONFIG register field offsets. | |
251 | * @midle_shift: Offset of the midle bit | |
252 | * @clkact_shift: Offset of the clockactivity bit | |
253 | * @sidle_shift: Offset of the sidle bit | |
254 | * @enwkup_shift: Offset of the enawakeup bit | |
255 | * @srst_shift: Offset of the softreset bit | |
43b40992 | 256 | * @autoidle_shift: Offset of the autoidle bit |
358f0e63 TG |
257 | */ |
258 | struct omap_hwmod_sysc_fields { | |
259 | u8 midle_shift; | |
260 | u8 clkact_shift; | |
261 | u8 sidle_shift; | |
262 | u8 enwkup_shift; | |
263 | u8 srst_shift; | |
264 | u8 autoidle_shift; | |
265 | }; | |
266 | ||
63c85238 | 267 | /** |
43b40992 | 268 | * struct omap_hwmod_class_sysconfig - hwmod class OCP_SYS* data |
63c85238 PW |
269 | * @rev_offs: IP block revision register offset (from module base addr) |
270 | * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr) | |
271 | * @syss_offs: OCP_SYSSTATUS register offset (from module base addr) | |
272 | * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART} | |
273 | * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported | |
274 | * @clockact: the default value of the module CLOCKACTIVITY bits | |
275 | * | |
276 | * @clockact describes to the module which clocks are likely to be | |
277 | * disabled when the PRCM issues its idle request to the module. Some | |
278 | * modules have separate clockdomains for the interface clock and main | |
279 | * functional clock, and can check whether they should acknowledge the | |
280 | * idle request based on the internal module functionality that has | |
281 | * been associated with the clocks marked in @clockact. This field is | |
282 | * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below) | |
283 | * | |
358f0e63 TG |
284 | * @sysc_fields: structure containing the offset positions of various bits in |
285 | * SYSCONFIG register. This can be populated using omap_hwmod_sysc_type1 or | |
286 | * omap_hwmod_sysc_type2 defined in omap_hwmod_common_data.c depending on | |
287 | * whether the device ip is compliant with the original PRCM protocol | |
43b40992 PW |
288 | * defined for OMAP2420 or the new PRCM protocol for new OMAP4 IPs. |
289 | * If the device follows a different scheme for the sysconfig register , | |
358f0e63 | 290 | * then this field has to be populated with the correct offset structure. |
63c85238 | 291 | */ |
43b40992 | 292 | struct omap_hwmod_class_sysconfig { |
63c85238 PW |
293 | u16 rev_offs; |
294 | u16 sysc_offs; | |
295 | u16 syss_offs; | |
56dc79ab | 296 | u16 sysc_flags; |
63c85238 | 297 | u8 idlemodes; |
63c85238 | 298 | u8 clockact; |
358f0e63 | 299 | struct omap_hwmod_sysc_fields *sysc_fields; |
63c85238 PW |
300 | }; |
301 | ||
302 | /** | |
303 | * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data | |
304 | * @module_offs: PRCM submodule offset from the start of the PRM/CM | |
305 | * @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3) | |
306 | * @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs | |
307 | * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3) | |
308 | * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit | |
309 | * @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit | |
310 | * | |
311 | * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST, | |
312 | * WKEN, GRPSEL registers. In an ideal world, no extra information | |
313 | * would be needed for IDLEST information, but alas, there are some | |
314 | * exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit | |
315 | * are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST) | |
316 | */ | |
317 | struct omap_hwmod_omap2_prcm { | |
318 | s16 module_offs; | |
319 | u8 prcm_reg_id; | |
320 | u8 module_bit; | |
321 | u8 idlest_reg_id; | |
322 | u8 idlest_idle_bit; | |
323 | u8 idlest_stdby_bit; | |
324 | }; | |
325 | ||
326 | ||
327 | /** | |
328 | * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data | |
53934aa7 | 329 | * @clkctrl_reg: PRCM address of the clock control register |
63c85238 PW |
330 | * @submodule_wkdep_bit: bit shift of the WKDEP range |
331 | */ | |
332 | struct omap_hwmod_omap4_prcm { | |
53934aa7 BC |
333 | void __iomem *clkctrl_reg; |
334 | u8 submodule_wkdep_bit; | |
63c85238 PW |
335 | }; |
336 | ||
337 | ||
338 | /* | |
339 | * omap_hwmod.flags definitions | |
340 | * | |
341 | * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out | |
342 | * of idle, rather than relying on module smart-idle | |
343 | * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out | |
344 | * of standby, rather than relying on module smart-standby | |
345 | * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for | |
346 | * SDRAM controller, etc. | |
347 | * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM | |
348 | * controller, etc. | |
726072e5 PW |
349 | * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE) |
350 | * when module is enabled, rather than the default, which is to | |
351 | * enable autoidle | |
63c85238 | 352 | * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup |
33f7ec81 BC |
353 | * HWMOD_NO_IDLEST : this module does not have idle status - this is the case |
354 | * only for few initiator modules on OMAP2 & 3. | |
63c85238 PW |
355 | */ |
356 | #define HWMOD_SWSUP_SIDLE (1 << 0) | |
357 | #define HWMOD_SWSUP_MSTANDBY (1 << 1) | |
358 | #define HWMOD_INIT_NO_RESET (1 << 2) | |
359 | #define HWMOD_INIT_NO_IDLE (1 << 3) | |
726072e5 PW |
360 | #define HWMOD_NO_OCP_AUTOIDLE (1 << 4) |
361 | #define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5) | |
33f7ec81 | 362 | #define HWMOD_NO_IDLEST (1 << 6) |
63c85238 PW |
363 | |
364 | /* | |
365 | * omap_hwmod._int_flags definitions | |
366 | * These are for internal use only and are managed by the omap_hwmod code. | |
367 | * | |
368 | * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module | |
369 | * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP | |
370 | * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached | |
371 | */ | |
372 | #define _HWMOD_NO_MPU_PORT (1 << 0) | |
373 | #define _HWMOD_WAKEUP_ENABLED (1 << 1) | |
374 | #define _HWMOD_SYSCONFIG_LOADED (1 << 2) | |
375 | ||
376 | /* | |
377 | * omap_hwmod._state definitions | |
378 | * | |
379 | * INITIALIZED: reset (optionally), initialized, enabled, disabled | |
380 | * (optionally) | |
381 | * | |
382 | * | |
383 | */ | |
384 | #define _HWMOD_STATE_UNKNOWN 0 | |
385 | #define _HWMOD_STATE_REGISTERED 1 | |
386 | #define _HWMOD_STATE_CLKS_INITED 2 | |
387 | #define _HWMOD_STATE_INITIALIZED 3 | |
388 | #define _HWMOD_STATE_ENABLED 4 | |
389 | #define _HWMOD_STATE_IDLE 5 | |
390 | #define _HWMOD_STATE_DISABLED 6 | |
391 | ||
43b40992 PW |
392 | /** |
393 | * struct omap_hwmod_class - the type of an IP block | |
394 | * @name: name of the hwmod_class | |
395 | * @sysc: device SYSCONFIG/SYSSTATUS register data | |
396 | * @rev: revision of the IP class | |
397 | * | |
398 | * Represent the class of a OMAP hardware "modules" (e.g. timer, | |
399 | * smartreflex, gpio, uart...) | |
400 | */ | |
401 | struct omap_hwmod_class { | |
402 | const char *name; | |
403 | struct omap_hwmod_class_sysconfig *sysc; | |
404 | u32 rev; | |
405 | }; | |
406 | ||
63c85238 PW |
407 | /** |
408 | * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks) | |
409 | * @name: name of the hwmod | |
43b40992 | 410 | * @class: struct omap_hwmod_class * to the class of this hwmod |
63c85238 PW |
411 | * @od: struct omap_device currently associated with this hwmod (internal use) |
412 | * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt) | |
413 | * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt) | |
414 | * @prcm: PRCM data pertaining to this hwmod | |
50ebdac2 | 415 | * @main_clk: main clock: OMAP clock name |
63c85238 PW |
416 | * @_clk: pointer to the main struct clk (filled in at runtime) |
417 | * @opt_clks: other device clocks that drivers can request (0..*) | |
418 | * @masters: ptr to array of OCP ifs that this hwmod can initiate on | |
419 | * @slaves: ptr to array of OCP ifs that this hwmod can respond on | |
63c85238 PW |
420 | * @dev_attr: arbitrary device attributes that can be passed to the driver |
421 | * @_sysc_cache: internal-use hwmod flags | |
422 | * @_rt_va: cached register target start address (internal use) | |
423 | * @_mpu_port_index: cached MPU register target slave ID (internal use) | |
424 | * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6) | |
425 | * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift | |
426 | * @mpu_irqs_cnt: number of @mpu_irqs | |
427 | * @sdma_chs_cnt: number of @sdma_chs | |
428 | * @opt_clks_cnt: number of @opt_clks | |
429 | * @master_cnt: number of @master entries | |
430 | * @slaves_cnt: number of @slave entries | |
431 | * @response_lat: device OCP response latency (in interface clock cycles) | |
432 | * @_int_flags: internal-use hwmod flags | |
433 | * @_state: internal-use hwmod state | |
434 | * @flags: hwmod flags (documented below) | |
435 | * @omap_chip: OMAP chips this hwmod is present on | |
436 | * @node: list node for hwmod list (internal use) | |
437 | * | |
50ebdac2 PW |
438 | * @main_clk refers to this module's "main clock," which for our |
439 | * purposes is defined as "the functional clock needed for register | |
440 | * accesses to complete." Modules may not have a main clock if the | |
441 | * interface clock also serves as a main clock. | |
63c85238 PW |
442 | * |
443 | * Parameter names beginning with an underscore are managed internally by | |
444 | * the omap_hwmod code and should not be set during initialization. | |
445 | */ | |
446 | struct omap_hwmod { | |
447 | const char *name; | |
43b40992 | 448 | struct omap_hwmod_class *class; |
63c85238 | 449 | struct omap_device *od; |
718bfd76 | 450 | struct omap_hwmod_irq_info *mpu_irqs; |
63c85238 PW |
451 | struct omap_hwmod_dma_info *sdma_chs; |
452 | union { | |
453 | struct omap_hwmod_omap2_prcm omap2; | |
454 | struct omap_hwmod_omap4_prcm omap4; | |
455 | } prcm; | |
50ebdac2 | 456 | const char *main_clk; |
63c85238 PW |
457 | struct clk *_clk; |
458 | struct omap_hwmod_opt_clk *opt_clks; | |
459 | struct omap_hwmod_ocp_if **masters; /* connect to *_IA */ | |
460 | struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */ | |
63c85238 PW |
461 | void *dev_attr; |
462 | u32 _sysc_cache; | |
463 | void __iomem *_rt_va; | |
464 | struct list_head node; | |
465 | u16 flags; | |
466 | u8 _mpu_port_index; | |
467 | u8 msuspendmux_reg_id; | |
468 | u8 msuspendmux_shift; | |
469 | u8 response_lat; | |
470 | u8 mpu_irqs_cnt; | |
471 | u8 sdma_chs_cnt; | |
472 | u8 opt_clks_cnt; | |
473 | u8 masters_cnt; | |
474 | u8 slaves_cnt; | |
475 | u8 hwmods_cnt; | |
476 | u8 _int_flags; | |
477 | u8 _state; | |
478 | const struct omap_chip_id omap_chip; | |
479 | }; | |
480 | ||
481 | int omap_hwmod_init(struct omap_hwmod **ohs); | |
482 | int omap_hwmod_register(struct omap_hwmod *oh); | |
483 | int omap_hwmod_unregister(struct omap_hwmod *oh); | |
484 | struct omap_hwmod *omap_hwmod_lookup(const char *name); | |
97d60162 PW |
485 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
486 | void *data); | |
487 | int omap_hwmod_late_init(u8 skip_setup_idle); | |
63c85238 PW |
488 | |
489 | int omap_hwmod_enable(struct omap_hwmod *oh); | |
84824022 | 490 | int _omap_hwmod_enable(struct omap_hwmod *oh); |
63c85238 | 491 | int omap_hwmod_idle(struct omap_hwmod *oh); |
84824022 | 492 | int _omap_hwmod_idle(struct omap_hwmod *oh); |
63c85238 PW |
493 | int omap_hwmod_shutdown(struct omap_hwmod *oh); |
494 | ||
495 | int omap_hwmod_enable_clocks(struct omap_hwmod *oh); | |
496 | int omap_hwmod_disable_clocks(struct omap_hwmod *oh); | |
497 | ||
46273e6f KH |
498 | int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode); |
499 | ||
63c85238 PW |
500 | int omap_hwmod_reset(struct omap_hwmod *oh); |
501 | void omap_hwmod_ocp_barrier(struct omap_hwmod *oh); | |
502 | ||
503 | void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs); | |
504 | u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs); | |
505 | ||
506 | int omap_hwmod_count_resources(struct omap_hwmod *oh); | |
507 | int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); | |
508 | ||
509 | struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh); | |
510 | ||
511 | int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, | |
512 | struct omap_hwmod *init_oh); | |
513 | int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, | |
514 | struct omap_hwmod *init_oh); | |
515 | ||
516 | int omap_hwmod_set_clockact_both(struct omap_hwmod *oh); | |
517 | int omap_hwmod_set_clockact_main(struct omap_hwmod *oh); | |
518 | int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh); | |
519 | int omap_hwmod_set_clockact_none(struct omap_hwmod *oh); | |
520 | ||
521 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh); | |
522 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh); | |
523 | ||
43b40992 PW |
524 | int omap_hwmod_for_each_by_class(const char *classname, |
525 | int (*fn)(struct omap_hwmod *oh, | |
526 | void *user), | |
527 | void *user); | |
528 | ||
7359154e PW |
529 | /* |
530 | * Chip variant-specific hwmod init routines - XXX should be converted | |
531 | * to use initcalls once the initial boot ordering is straightened out | |
532 | */ | |
533 | extern int omap2420_hwmod_init(void); | |
534 | extern int omap2430_hwmod_init(void); | |
535 | extern int omap3xxx_hwmod_init(void); | |
536 | ||
63c85238 | 537 | #endif |