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OMAP2/3: PRM/CM: prefix OMAP2 PRM/CM functions with "omap2_"
[deliverable/linux.git] / arch / arm / plat-omap / include / plat / powerdomain.h
CommitLineData
ad67ef68
PW		 1/*
2 * OMAP2/3 powerdomain control
3 *
55ed9694 4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
6e01478a 5 * Copyright (C) 2007-2010 Nokia Corporation
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PW		 6 *
7 * Written by Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
6e01478a
PW		 12 *
13 * XXX This should be moved to the mach-omap2/ directory at the earliest
14 * opportunity.
ad67ef68
PW		 15 */
16
6e01478a
PW		 17#ifndef ASM_ARM_PLAT_OMAP_INCLUDE_PLAT_POWERDOMAIN
18#define ASM_ARM_PLAT_OMAP_INCLUDE_PLAT_POWERDOMAIN
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PW		 19
20#include <linux/types.h>
21#include <linux/list.h>
22
23#include <asm/atomic.h>
24
ce491cf8 25#include <plat/cpu.h>
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PW		 26
27
28/* Powerdomain basic power states */
29#define PWRDM_POWER_OFF 0x0
30#define PWRDM_POWER_RET 0x1
31#define PWRDM_POWER_INACTIVE 0x2
32#define PWRDM_POWER_ON 0x3
33
2354eb5a
PW		 34#define PWRDM_MAX_PWRSTS 4
35
ad67ef68 36/* Powerdomain allowable state bitfields */
d3353e16 37#define PWRSTS_ON (1 << PWRDM_POWER_ON)
bb722f33 38#define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
ad67ef68
PW		 39#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
40 (1 << PWRDM_POWER_ON))
41
42#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
43 (1 << PWRDM_POWER_RET))
44
f37c6dfa
AP		 45#define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \
46 (1 << PWRDM_POWER_ON))
47
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PW		 48#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
49
50
0b7cbfb5
PW		 51/* Powerdomain flags */
52#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
3863c74b
TG		 53#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
54 * in MEM bank 1 position. This is
55 * true for OMAP3430
56 */
90dbc7b0
RN		 57#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /*
58 * support to transition from a
59 * sleep state to a lower sleep
60 * state without waking up the
61 * powerdomain
62 */
0b7cbfb5 63
ad67ef68 64/*
38900c27
AP		 65 * Number of memory banks that are power-controllable. On OMAP4430, the
66 * maximum is 5.
ad67ef68 67 */
38900c27 68#define PWRDM_MAX_MEM_BANKS 5
ad67ef68 69
8420bb13
PW		 70/*
71 * Maximum number of clockdomains that can be associated with a powerdomain.
38900c27 72 * CORE powerdomain on OMAP4 is the worst case
8420bb13 73 */
38900c27 74#define PWRDM_MAX_CLKDMS 9
8420bb13 75
ad67ef68
PW		 76/* XXX A completely arbitrary number. What is reasonable here? */
77#define PWRDM_TRANSITION_BAILOUT 100000
78
8420bb13 79struct clockdomain;
ad67ef68
PW		 80struct powerdomain;
81
f0271d65
PW		 82/**
83 * struct powerdomain - OMAP powerdomain
84 * @name: Powerdomain name
85 * @omap_chip: represents the OMAP chip types containing this pwrdm
86 * @prcm_offs: the address offset from CM_BASE/PRM_BASE
87 * @pwrsts: Possible powerdomain power states
88 * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
89 * @flags: Powerdomain flags
90 * @banks: Number of software-controllable memory banks in this powerdomain
91 * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
92 * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
93 * @pwrdm_clkdms: Clockdomains in this powerdomain
94 * @node: list_head linking all powerdomains
95 * @state:
96 * @state_counter:
97 * @timer:
98 * @state_timer:
99 */
ad67ef68 100struct powerdomain {
ad67ef68 101 const char *name;
ad67ef68 102 const struct omap_chip_id omap_chip;
e0594b44 103 const s16 prcm_offs;
ad67ef68 104 const u8 pwrsts;
ad67ef68 105 const u8 pwrsts_logic_ret;
0b7cbfb5 106 const u8 flags;
ad67ef68 107 const u8 banks;
ad67ef68 108 const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
ad67ef68 109 const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
8420bb13 110 struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
ad67ef68 111 struct list_head node;
ba20bb12 112 int state;
2354eb5a 113 unsigned state_counter[PWRDM_MAX_PWRSTS];
cde08f81
TG		 114 unsigned ret_logic_off_counter;
115 unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
331b93f4
PDS		 116
117#ifdef CONFIG_PM_DEBUG
118 s64 timer;
2354eb5a 119 s64 state_timer[PWRDM_MAX_PWRSTS];
331b93f4 120#endif
ad67ef68
PW		 121};
122
3b1e8b21
RN		 123/**
124 * struct pwrdm_ops - Arch specfic function implementations
125 * @pwrdm_set_next_pwrst: Set the target power state for a pd
126 * @pwrdm_read_next_pwrst: Read the target power state set for a pd
127 * @pwrdm_read_pwrst: Read the current power state of a pd
128 * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd
129 * @pwrdm_set_logic_retst: Set the logic state in RET for a pd
130 * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd
131 * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd
132 * @pwrdm_read_logic_pwrst: Read the current logic state of a pd
133 * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd
134 * @pwrdm_read_logic_retst: Read the logic state in RET for a pd
135 * @pwrdm_read_mem_pwrst: Read the current memory state of a pd
136 * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd
137 * @pwrdm_read_mem_retst: Read the memory state in RET for a pd
138 * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd
139 * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd
140 * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
141 * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
142 * @pwrdm_wait_transition: Wait for a pd state transition to complete
143 */
144struct pwrdm_ops {
145 int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
146 int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm);
147 int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm);
148 int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm);
149 int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst);
150 int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
151 int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
152 int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm);
153 int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm);
154 int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm);
155 int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
156 int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
157 int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
158 int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm);
159 int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm);
160 int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
161 int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
162 int (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
163};
ad67ef68 164
74bea6b9 165void pwrdm_fw_init(void);
3b1e8b21 166void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs);
ad67ef68 167
ad67ef68
PW		 168struct powerdomain *pwrdm_lookup(const char *name);
169
a23456e9
PDS		 170int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
171 void *user);
ee894b18
AB		 172int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
173 void *user);
ad67ef68 174
8420bb13
PW		 175int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
176int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
177int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
178 int (*fn)(struct powerdomain *pwrdm,
179 struct clockdomain *clkdm));
180
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PW		 181int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
182
183int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
184int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
fecb494b 185int pwrdm_read_pwrst(struct powerdomain *pwrdm);
ad67ef68
PW		 186int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
187int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
188
189int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
190int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
191int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
192
193int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
194int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
1e3d0d2b 195int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
ad67ef68
PW		 196int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
197int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
1e3d0d2b 198int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
ad67ef68 199
0b7cbfb5
PW		 200int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
201int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
202bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
203
ad67ef68
PW		 204int pwrdm_wait_transition(struct powerdomain *pwrdm);
205
ba20bb12
PDS		 206int pwrdm_state_switch(struct powerdomain *pwrdm);
207int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
208int pwrdm_pre_transition(void);
209int pwrdm_post_transition(void);
04aeae77 210int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
ba20bb12 211
6e01478a
PW		 212extern void omap2xxx_powerdomains_init(void);
213extern void omap3xxx_powerdomains_init(void);
214extern void omap44xx_powerdomains_init(void);
215
ad67ef68 216#endif
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