Commit | Line | Data |
---|---|---|
a9dcad5e HD |
1 | /* |
2 | * omap iommu: tlb and pagetable primitives | |
3 | * | |
c127c7dc | 4 | * Copyright (C) 2008-2010 Nokia Corporation |
a9dcad5e HD |
5 | * |
6 | * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, | |
7 | * Paul Mundt and Toshihiro Kobayashi | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/err.h> | |
15 | #include <linux/module.h> | |
5a0e3ad6 | 16 | #include <linux/slab.h> |
a9dcad5e HD |
17 | #include <linux/interrupt.h> |
18 | #include <linux/ioport.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/platform_device.h> | |
21 | ||
22 | #include <asm/cacheflush.h> | |
23 | ||
ce491cf8 | 24 | #include <plat/iommu.h> |
a9dcad5e HD |
25 | |
26 | #include "iopgtable.h" | |
27 | ||
37c2836c HD |
28 | #define for_each_iotlb_cr(obj, n, __i, cr) \ |
29 | for (__i = 0; \ | |
30 | (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \ | |
31 | __i++) | |
32 | ||
a9dcad5e HD |
33 | /* accommodate the difference between omap1 and omap2/3 */ |
34 | static const struct iommu_functions *arch_iommu; | |
35 | ||
36 | static struct platform_driver omap_iommu_driver; | |
37 | static struct kmem_cache *iopte_cachep; | |
38 | ||
39 | /** | |
40 | * install_iommu_arch - Install archtecure specific iommu functions | |
41 | * @ops: a pointer to architecture specific iommu functions | |
42 | * | |
43 | * There are several kind of iommu algorithm(tlb, pagetable) among | |
44 | * omap series. This interface installs such an iommu algorighm. | |
45 | **/ | |
46 | int install_iommu_arch(const struct iommu_functions *ops) | |
47 | { | |
48 | if (arch_iommu) | |
49 | return -EBUSY; | |
50 | ||
51 | arch_iommu = ops; | |
52 | return 0; | |
53 | } | |
54 | EXPORT_SYMBOL_GPL(install_iommu_arch); | |
55 | ||
56 | /** | |
57 | * uninstall_iommu_arch - Uninstall archtecure specific iommu functions | |
58 | * @ops: a pointer to architecture specific iommu functions | |
59 | * | |
60 | * This interface uninstalls the iommu algorighm installed previously. | |
61 | **/ | |
62 | void uninstall_iommu_arch(const struct iommu_functions *ops) | |
63 | { | |
64 | if (arch_iommu != ops) | |
65 | pr_err("%s: not your arch\n", __func__); | |
66 | ||
67 | arch_iommu = NULL; | |
68 | } | |
69 | EXPORT_SYMBOL_GPL(uninstall_iommu_arch); | |
70 | ||
71 | /** | |
72 | * iommu_save_ctx - Save registers for pm off-mode support | |
73 | * @obj: target iommu | |
74 | **/ | |
75 | void iommu_save_ctx(struct iommu *obj) | |
76 | { | |
77 | arch_iommu->save_ctx(obj); | |
78 | } | |
79 | EXPORT_SYMBOL_GPL(iommu_save_ctx); | |
80 | ||
81 | /** | |
82 | * iommu_restore_ctx - Restore registers for pm off-mode support | |
83 | * @obj: target iommu | |
84 | **/ | |
85 | void iommu_restore_ctx(struct iommu *obj) | |
86 | { | |
87 | arch_iommu->restore_ctx(obj); | |
88 | } | |
89 | EXPORT_SYMBOL_GPL(iommu_restore_ctx); | |
90 | ||
91 | /** | |
92 | * iommu_arch_version - Return running iommu arch version | |
93 | **/ | |
94 | u32 iommu_arch_version(void) | |
95 | { | |
96 | return arch_iommu->version; | |
97 | } | |
98 | EXPORT_SYMBOL_GPL(iommu_arch_version); | |
99 | ||
100 | static int iommu_enable(struct iommu *obj) | |
101 | { | |
102 | int err; | |
103 | ||
104 | if (!obj) | |
105 | return -EINVAL; | |
106 | ||
107 | clk_enable(obj->clk); | |
108 | ||
109 | err = arch_iommu->enable(obj); | |
110 | ||
111 | clk_disable(obj->clk); | |
112 | return err; | |
113 | } | |
114 | ||
115 | static void iommu_disable(struct iommu *obj) | |
116 | { | |
117 | if (!obj) | |
118 | return; | |
119 | ||
120 | clk_enable(obj->clk); | |
121 | ||
122 | arch_iommu->disable(obj); | |
123 | ||
124 | clk_disable(obj->clk); | |
125 | } | |
126 | ||
127 | /* | |
128 | * TLB operations | |
129 | */ | |
130 | void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e) | |
131 | { | |
132 | BUG_ON(!cr || !e); | |
133 | ||
134 | arch_iommu->cr_to_e(cr, e); | |
135 | } | |
136 | EXPORT_SYMBOL_GPL(iotlb_cr_to_e); | |
137 | ||
138 | static inline int iotlb_cr_valid(struct cr_regs *cr) | |
139 | { | |
140 | if (!cr) | |
141 | return -EINVAL; | |
142 | ||
143 | return arch_iommu->cr_valid(cr); | |
144 | } | |
145 | ||
146 | static inline struct cr_regs *iotlb_alloc_cr(struct iommu *obj, | |
147 | struct iotlb_entry *e) | |
148 | { | |
149 | if (!e) | |
150 | return NULL; | |
151 | ||
152 | return arch_iommu->alloc_cr(obj, e); | |
153 | } | |
154 | ||
155 | u32 iotlb_cr_to_virt(struct cr_regs *cr) | |
156 | { | |
157 | return arch_iommu->cr_to_virt(cr); | |
158 | } | |
159 | EXPORT_SYMBOL_GPL(iotlb_cr_to_virt); | |
160 | ||
161 | static u32 get_iopte_attr(struct iotlb_entry *e) | |
162 | { | |
163 | return arch_iommu->get_pte_attr(e); | |
164 | } | |
165 | ||
166 | static u32 iommu_report_fault(struct iommu *obj, u32 *da) | |
167 | { | |
168 | return arch_iommu->fault_isr(obj, da); | |
169 | } | |
170 | ||
171 | static void iotlb_lock_get(struct iommu *obj, struct iotlb_lock *l) | |
172 | { | |
173 | u32 val; | |
174 | ||
175 | val = iommu_read_reg(obj, MMU_LOCK); | |
176 | ||
177 | l->base = MMU_LOCK_BASE(val); | |
178 | l->vict = MMU_LOCK_VICT(val); | |
179 | ||
a9dcad5e HD |
180 | } |
181 | ||
182 | static void iotlb_lock_set(struct iommu *obj, struct iotlb_lock *l) | |
183 | { | |
184 | u32 val; | |
185 | ||
a9dcad5e HD |
186 | val = (l->base << MMU_LOCK_BASE_SHIFT); |
187 | val |= (l->vict << MMU_LOCK_VICT_SHIFT); | |
188 | ||
189 | iommu_write_reg(obj, val, MMU_LOCK); | |
190 | } | |
191 | ||
192 | static void iotlb_read_cr(struct iommu *obj, struct cr_regs *cr) | |
193 | { | |
194 | arch_iommu->tlb_read_cr(obj, cr); | |
195 | } | |
196 | ||
197 | static void iotlb_load_cr(struct iommu *obj, struct cr_regs *cr) | |
198 | { | |
199 | arch_iommu->tlb_load_cr(obj, cr); | |
200 | ||
201 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); | |
202 | iommu_write_reg(obj, 1, MMU_LD_TLB); | |
203 | } | |
204 | ||
205 | /** | |
206 | * iotlb_dump_cr - Dump an iommu tlb entry into buf | |
207 | * @obj: target iommu | |
208 | * @cr: contents of cam and ram register | |
209 | * @buf: output buffer | |
210 | **/ | |
211 | static inline ssize_t iotlb_dump_cr(struct iommu *obj, struct cr_regs *cr, | |
212 | char *buf) | |
213 | { | |
214 | BUG_ON(!cr || !buf); | |
215 | ||
216 | return arch_iommu->dump_cr(obj, cr, buf); | |
217 | } | |
218 | ||
37c2836c HD |
219 | /* only used in iotlb iteration for-loop */ |
220 | static struct cr_regs __iotlb_read_cr(struct iommu *obj, int n) | |
221 | { | |
222 | struct cr_regs cr; | |
223 | struct iotlb_lock l; | |
224 | ||
225 | iotlb_lock_get(obj, &l); | |
226 | l.vict = n; | |
227 | iotlb_lock_set(obj, &l); | |
228 | iotlb_read_cr(obj, &cr); | |
229 | ||
230 | return cr; | |
231 | } | |
232 | ||
a9dcad5e HD |
233 | /** |
234 | * load_iotlb_entry - Set an iommu tlb entry | |
235 | * @obj: target iommu | |
236 | * @e: an iommu tlb entry info | |
237 | **/ | |
238 | int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e) | |
239 | { | |
a9dcad5e HD |
240 | int err = 0; |
241 | struct iotlb_lock l; | |
242 | struct cr_regs *cr; | |
243 | ||
244 | if (!obj || !obj->nr_tlb_entries || !e) | |
245 | return -EINVAL; | |
246 | ||
247 | clk_enable(obj->clk); | |
248 | ||
be6d8026 KH |
249 | iotlb_lock_get(obj, &l); |
250 | if (l.base == obj->nr_tlb_entries) { | |
251 | dev_warn(obj->dev, "%s: preserve entries full\n", __func__); | |
a9dcad5e HD |
252 | err = -EBUSY; |
253 | goto out; | |
254 | } | |
be6d8026 | 255 | if (!e->prsvd) { |
37c2836c HD |
256 | int i; |
257 | struct cr_regs tmp; | |
be6d8026 | 258 | |
37c2836c | 259 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp) |
be6d8026 KH |
260 | if (!iotlb_cr_valid(&tmp)) |
261 | break; | |
37c2836c | 262 | |
be6d8026 KH |
263 | if (i == obj->nr_tlb_entries) { |
264 | dev_dbg(obj->dev, "%s: full: no entry\n", __func__); | |
265 | err = -EBUSY; | |
266 | goto out; | |
267 | } | |
37c2836c HD |
268 | |
269 | iotlb_lock_get(obj, &l); | |
be6d8026 KH |
270 | } else { |
271 | l.vict = l.base; | |
272 | iotlb_lock_set(obj, &l); | |
273 | } | |
a9dcad5e HD |
274 | |
275 | cr = iotlb_alloc_cr(obj, e); | |
276 | if (IS_ERR(cr)) { | |
277 | clk_disable(obj->clk); | |
278 | return PTR_ERR(cr); | |
279 | } | |
280 | ||
281 | iotlb_load_cr(obj, cr); | |
282 | kfree(cr); | |
283 | ||
be6d8026 KH |
284 | if (e->prsvd) |
285 | l.base++; | |
a9dcad5e HD |
286 | /* increment victim for next tlb load */ |
287 | if (++l.vict == obj->nr_tlb_entries) | |
be6d8026 | 288 | l.vict = l.base; |
a9dcad5e HD |
289 | iotlb_lock_set(obj, &l); |
290 | out: | |
291 | clk_disable(obj->clk); | |
292 | return err; | |
293 | } | |
294 | EXPORT_SYMBOL_GPL(load_iotlb_entry); | |
295 | ||
296 | /** | |
297 | * flush_iotlb_page - Clear an iommu tlb entry | |
298 | * @obj: target iommu | |
299 | * @da: iommu device virtual address | |
300 | * | |
301 | * Clear an iommu tlb entry which includes 'da' address. | |
302 | **/ | |
303 | void flush_iotlb_page(struct iommu *obj, u32 da) | |
304 | { | |
a9dcad5e | 305 | int i; |
37c2836c | 306 | struct cr_regs cr; |
a9dcad5e HD |
307 | |
308 | clk_enable(obj->clk); | |
309 | ||
37c2836c | 310 | for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) { |
a9dcad5e HD |
311 | u32 start; |
312 | size_t bytes; | |
313 | ||
a9dcad5e HD |
314 | if (!iotlb_cr_valid(&cr)) |
315 | continue; | |
316 | ||
317 | start = iotlb_cr_to_virt(&cr); | |
318 | bytes = iopgsz_to_bytes(cr.cam & 3); | |
319 | ||
320 | if ((start <= da) && (da < start + bytes)) { | |
321 | dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", | |
322 | __func__, start, da, bytes); | |
a9dcad5e HD |
323 | iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); |
324 | } | |
325 | } | |
326 | clk_disable(obj->clk); | |
327 | ||
328 | if (i == obj->nr_tlb_entries) | |
329 | dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da); | |
330 | } | |
331 | EXPORT_SYMBOL_GPL(flush_iotlb_page); | |
332 | ||
333 | /** | |
334 | * flush_iotlb_range - Clear an iommu tlb entries | |
335 | * @obj: target iommu | |
336 | * @start: iommu device virtual address(start) | |
337 | * @end: iommu device virtual address(end) | |
338 | * | |
339 | * Clear an iommu tlb entry which includes 'da' address. | |
340 | **/ | |
341 | void flush_iotlb_range(struct iommu *obj, u32 start, u32 end) | |
342 | { | |
343 | u32 da = start; | |
344 | ||
345 | while (da < end) { | |
346 | flush_iotlb_page(obj, da); | |
347 | /* FIXME: Optimize for multiple page size */ | |
348 | da += IOPTE_SIZE; | |
349 | } | |
350 | } | |
351 | EXPORT_SYMBOL_GPL(flush_iotlb_range); | |
352 | ||
353 | /** | |
354 | * flush_iotlb_all - Clear all iommu tlb entries | |
355 | * @obj: target iommu | |
356 | **/ | |
357 | void flush_iotlb_all(struct iommu *obj) | |
358 | { | |
359 | struct iotlb_lock l; | |
360 | ||
361 | clk_enable(obj->clk); | |
362 | ||
363 | l.base = 0; | |
364 | l.vict = 0; | |
365 | iotlb_lock_set(obj, &l); | |
366 | ||
367 | iommu_write_reg(obj, 1, MMU_GFLUSH); | |
368 | ||
369 | clk_disable(obj->clk); | |
370 | } | |
371 | EXPORT_SYMBOL_GPL(flush_iotlb_all); | |
372 | ||
ddfa975a KH |
373 | /** |
374 | * iommu_set_twl - enable/disable table walking logic | |
375 | * @obj: target iommu | |
376 | * @on: enable/disable | |
377 | * | |
378 | * Function used to enable/disable TWL. If one wants to work | |
379 | * exclusively with locked TLB entries and receive notifications | |
380 | * for TLB miss then call this function to disable TWL. | |
381 | */ | |
382 | void iommu_set_twl(struct iommu *obj, bool on) | |
383 | { | |
384 | clk_enable(obj->clk); | |
385 | arch_iommu->set_twl(obj, on); | |
386 | clk_disable(obj->clk); | |
387 | } | |
388 | EXPORT_SYMBOL_GPL(iommu_set_twl); | |
389 | ||
a9dcad5e HD |
390 | #if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE) |
391 | ||
14e0e679 | 392 | ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes) |
a9dcad5e | 393 | { |
a9dcad5e HD |
394 | if (!obj || !buf) |
395 | return -EINVAL; | |
396 | ||
397 | clk_enable(obj->clk); | |
398 | ||
14e0e679 | 399 | bytes = arch_iommu->dump_ctx(obj, buf, bytes); |
a9dcad5e HD |
400 | |
401 | clk_disable(obj->clk); | |
402 | ||
403 | return bytes; | |
404 | } | |
405 | EXPORT_SYMBOL_GPL(iommu_dump_ctx); | |
406 | ||
14e0e679 | 407 | static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs, int num) |
a9dcad5e HD |
408 | { |
409 | int i; | |
37c2836c HD |
410 | struct iotlb_lock saved; |
411 | struct cr_regs tmp; | |
a9dcad5e HD |
412 | struct cr_regs *p = crs; |
413 | ||
414 | clk_enable(obj->clk); | |
a9dcad5e | 415 | iotlb_lock_get(obj, &saved); |
a9dcad5e | 416 | |
37c2836c | 417 | for_each_iotlb_cr(obj, num, i, tmp) { |
a9dcad5e HD |
418 | if (!iotlb_cr_valid(&tmp)) |
419 | continue; | |
a9dcad5e HD |
420 | *p++ = tmp; |
421 | } | |
37c2836c | 422 | |
a9dcad5e HD |
423 | iotlb_lock_set(obj, &saved); |
424 | clk_disable(obj->clk); | |
425 | ||
426 | return p - crs; | |
427 | } | |
428 | ||
429 | /** | |
430 | * dump_tlb_entries - dump cr arrays to given buffer | |
431 | * @obj: target iommu | |
432 | * @buf: output buffer | |
433 | **/ | |
14e0e679 | 434 | size_t dump_tlb_entries(struct iommu *obj, char *buf, ssize_t bytes) |
a9dcad5e | 435 | { |
14e0e679 | 436 | int i, num; |
a9dcad5e HD |
437 | struct cr_regs *cr; |
438 | char *p = buf; | |
439 | ||
14e0e679 HD |
440 | num = bytes / sizeof(*cr); |
441 | num = min(obj->nr_tlb_entries, num); | |
442 | ||
443 | cr = kcalloc(num, sizeof(*cr), GFP_KERNEL); | |
a9dcad5e HD |
444 | if (!cr) |
445 | return 0; | |
446 | ||
14e0e679 HD |
447 | num = __dump_tlb_entries(obj, cr, num); |
448 | for (i = 0; i < num; i++) | |
a9dcad5e HD |
449 | p += iotlb_dump_cr(obj, cr + i, p); |
450 | kfree(cr); | |
451 | ||
452 | return p - buf; | |
453 | } | |
454 | EXPORT_SYMBOL_GPL(dump_tlb_entries); | |
455 | ||
456 | int foreach_iommu_device(void *data, int (*fn)(struct device *, void *)) | |
457 | { | |
458 | return driver_for_each_device(&omap_iommu_driver.driver, | |
459 | NULL, data, fn); | |
460 | } | |
461 | EXPORT_SYMBOL_GPL(foreach_iommu_device); | |
462 | ||
463 | #endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */ | |
464 | ||
465 | /* | |
466 | * H/W pagetable operations | |
467 | */ | |
468 | static void flush_iopgd_range(u32 *first, u32 *last) | |
469 | { | |
470 | /* FIXME: L2 cache should be taken care of if it exists */ | |
471 | do { | |
472 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd" | |
473 | : : "r" (first)); | |
474 | first += L1_CACHE_BYTES / sizeof(*first); | |
475 | } while (first <= last); | |
476 | } | |
477 | ||
478 | static void flush_iopte_range(u32 *first, u32 *last) | |
479 | { | |
480 | /* FIXME: L2 cache should be taken care of if it exists */ | |
481 | do { | |
482 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte" | |
483 | : : "r" (first)); | |
484 | first += L1_CACHE_BYTES / sizeof(*first); | |
485 | } while (first <= last); | |
486 | } | |
487 | ||
488 | static void iopte_free(u32 *iopte) | |
489 | { | |
490 | /* Note: freed iopte's must be clean ready for re-use */ | |
491 | kmem_cache_free(iopte_cachep, iopte); | |
492 | } | |
493 | ||
494 | static u32 *iopte_alloc(struct iommu *obj, u32 *iopgd, u32 da) | |
495 | { | |
496 | u32 *iopte; | |
497 | ||
498 | /* a table has already existed */ | |
499 | if (*iopgd) | |
500 | goto pte_ready; | |
501 | ||
502 | /* | |
503 | * do the allocation outside the page table lock | |
504 | */ | |
505 | spin_unlock(&obj->page_table_lock); | |
506 | iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL); | |
507 | spin_lock(&obj->page_table_lock); | |
508 | ||
509 | if (!*iopgd) { | |
510 | if (!iopte) | |
511 | return ERR_PTR(-ENOMEM); | |
512 | ||
513 | *iopgd = virt_to_phys(iopte) | IOPGD_TABLE; | |
514 | flush_iopgd_range(iopgd, iopgd); | |
515 | ||
516 | dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte); | |
517 | } else { | |
518 | /* We raced, free the reduniovant table */ | |
519 | iopte_free(iopte); | |
520 | } | |
521 | ||
522 | pte_ready: | |
523 | iopte = iopte_offset(iopgd, da); | |
524 | ||
525 | dev_vdbg(obj->dev, | |
526 | "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", | |
527 | __func__, da, iopgd, *iopgd, iopte, *iopte); | |
528 | ||
529 | return iopte; | |
530 | } | |
531 | ||
532 | static int iopgd_alloc_section(struct iommu *obj, u32 da, u32 pa, u32 prot) | |
533 | { | |
534 | u32 *iopgd = iopgd_offset(obj, da); | |
535 | ||
4abb7617 HD |
536 | if ((da | pa) & ~IOSECTION_MASK) { |
537 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
538 | __func__, da, pa, IOSECTION_SIZE); | |
539 | return -EINVAL; | |
540 | } | |
541 | ||
a9dcad5e HD |
542 | *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION; |
543 | flush_iopgd_range(iopgd, iopgd); | |
544 | return 0; | |
545 | } | |
546 | ||
547 | static int iopgd_alloc_super(struct iommu *obj, u32 da, u32 pa, u32 prot) | |
548 | { | |
549 | u32 *iopgd = iopgd_offset(obj, da); | |
550 | int i; | |
551 | ||
4abb7617 HD |
552 | if ((da | pa) & ~IOSUPER_MASK) { |
553 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
554 | __func__, da, pa, IOSUPER_SIZE); | |
555 | return -EINVAL; | |
556 | } | |
557 | ||
a9dcad5e HD |
558 | for (i = 0; i < 16; i++) |
559 | *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER; | |
560 | flush_iopgd_range(iopgd, iopgd + 15); | |
561 | return 0; | |
562 | } | |
563 | ||
564 | static int iopte_alloc_page(struct iommu *obj, u32 da, u32 pa, u32 prot) | |
565 | { | |
566 | u32 *iopgd = iopgd_offset(obj, da); | |
567 | u32 *iopte = iopte_alloc(obj, iopgd, da); | |
568 | ||
569 | if (IS_ERR(iopte)) | |
570 | return PTR_ERR(iopte); | |
571 | ||
572 | *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL; | |
573 | flush_iopte_range(iopte, iopte); | |
574 | ||
575 | dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n", | |
576 | __func__, da, pa, iopte, *iopte); | |
577 | ||
578 | return 0; | |
579 | } | |
580 | ||
581 | static int iopte_alloc_large(struct iommu *obj, u32 da, u32 pa, u32 prot) | |
582 | { | |
583 | u32 *iopgd = iopgd_offset(obj, da); | |
584 | u32 *iopte = iopte_alloc(obj, iopgd, da); | |
585 | int i; | |
586 | ||
4abb7617 HD |
587 | if ((da | pa) & ~IOLARGE_MASK) { |
588 | dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n", | |
589 | __func__, da, pa, IOLARGE_SIZE); | |
590 | return -EINVAL; | |
591 | } | |
592 | ||
a9dcad5e HD |
593 | if (IS_ERR(iopte)) |
594 | return PTR_ERR(iopte); | |
595 | ||
596 | for (i = 0; i < 16; i++) | |
597 | *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE; | |
598 | flush_iopte_range(iopte, iopte + 15); | |
599 | return 0; | |
600 | } | |
601 | ||
602 | static int iopgtable_store_entry_core(struct iommu *obj, struct iotlb_entry *e) | |
603 | { | |
604 | int (*fn)(struct iommu *, u32, u32, u32); | |
605 | u32 prot; | |
606 | int err; | |
607 | ||
608 | if (!obj || !e) | |
609 | return -EINVAL; | |
610 | ||
611 | switch (e->pgsz) { | |
612 | case MMU_CAM_PGSZ_16M: | |
613 | fn = iopgd_alloc_super; | |
614 | break; | |
615 | case MMU_CAM_PGSZ_1M: | |
616 | fn = iopgd_alloc_section; | |
617 | break; | |
618 | case MMU_CAM_PGSZ_64K: | |
619 | fn = iopte_alloc_large; | |
620 | break; | |
621 | case MMU_CAM_PGSZ_4K: | |
622 | fn = iopte_alloc_page; | |
623 | break; | |
624 | default: | |
625 | fn = NULL; | |
626 | BUG(); | |
627 | break; | |
628 | } | |
629 | ||
630 | prot = get_iopte_attr(e); | |
631 | ||
632 | spin_lock(&obj->page_table_lock); | |
633 | err = fn(obj, e->da, e->pa, prot); | |
634 | spin_unlock(&obj->page_table_lock); | |
635 | ||
636 | return err; | |
637 | } | |
638 | ||
639 | /** | |
640 | * iopgtable_store_entry - Make an iommu pte entry | |
641 | * @obj: target iommu | |
642 | * @e: an iommu tlb entry info | |
643 | **/ | |
644 | int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e) | |
645 | { | |
646 | int err; | |
647 | ||
648 | flush_iotlb_page(obj, e->da); | |
649 | err = iopgtable_store_entry_core(obj, e); | |
650 | #ifdef PREFETCH_IOTLB | |
651 | if (!err) | |
652 | load_iotlb_entry(obj, e); | |
653 | #endif | |
654 | return err; | |
655 | } | |
656 | EXPORT_SYMBOL_GPL(iopgtable_store_entry); | |
657 | ||
658 | /** | |
659 | * iopgtable_lookup_entry - Lookup an iommu pte entry | |
660 | * @obj: target iommu | |
661 | * @da: iommu device virtual address | |
662 | * @ppgd: iommu pgd entry pointer to be returned | |
663 | * @ppte: iommu pte entry pointer to be returned | |
664 | **/ | |
665 | void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd, u32 **ppte) | |
666 | { | |
667 | u32 *iopgd, *iopte = NULL; | |
668 | ||
669 | iopgd = iopgd_offset(obj, da); | |
670 | if (!*iopgd) | |
671 | goto out; | |
672 | ||
a1a54456 | 673 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
674 | iopte = iopte_offset(iopgd, da); |
675 | out: | |
676 | *ppgd = iopgd; | |
677 | *ppte = iopte; | |
678 | } | |
679 | EXPORT_SYMBOL_GPL(iopgtable_lookup_entry); | |
680 | ||
681 | static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da) | |
682 | { | |
683 | size_t bytes; | |
684 | u32 *iopgd = iopgd_offset(obj, da); | |
685 | int nent = 1; | |
686 | ||
687 | if (!*iopgd) | |
688 | return 0; | |
689 | ||
a1a54456 | 690 | if (iopgd_is_table(*iopgd)) { |
a9dcad5e HD |
691 | int i; |
692 | u32 *iopte = iopte_offset(iopgd, da); | |
693 | ||
694 | bytes = IOPTE_SIZE; | |
695 | if (*iopte & IOPTE_LARGE) { | |
696 | nent *= 16; | |
697 | /* rewind to the 1st entry */ | |
c127c7dc | 698 | iopte = iopte_offset(iopgd, (da & IOLARGE_MASK)); |
a9dcad5e HD |
699 | } |
700 | bytes *= nent; | |
701 | memset(iopte, 0, nent * sizeof(*iopte)); | |
702 | flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte)); | |
703 | ||
704 | /* | |
705 | * do table walk to check if this table is necessary or not | |
706 | */ | |
707 | iopte = iopte_offset(iopgd, 0); | |
708 | for (i = 0; i < PTRS_PER_IOPTE; i++) | |
709 | if (iopte[i]) | |
710 | goto out; | |
711 | ||
712 | iopte_free(iopte); | |
713 | nent = 1; /* for the next L1 entry */ | |
714 | } else { | |
715 | bytes = IOPGD_SIZE; | |
dcc730dc | 716 | if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) { |
a9dcad5e HD |
717 | nent *= 16; |
718 | /* rewind to the 1st entry */ | |
8d33ea58 | 719 | iopgd = iopgd_offset(obj, (da & IOSUPER_MASK)); |
a9dcad5e HD |
720 | } |
721 | bytes *= nent; | |
722 | } | |
723 | memset(iopgd, 0, nent * sizeof(*iopgd)); | |
724 | flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd)); | |
725 | out: | |
726 | return bytes; | |
727 | } | |
728 | ||
729 | /** | |
730 | * iopgtable_clear_entry - Remove an iommu pte entry | |
731 | * @obj: target iommu | |
732 | * @da: iommu device virtual address | |
733 | **/ | |
734 | size_t iopgtable_clear_entry(struct iommu *obj, u32 da) | |
735 | { | |
736 | size_t bytes; | |
737 | ||
738 | spin_lock(&obj->page_table_lock); | |
739 | ||
740 | bytes = iopgtable_clear_entry_core(obj, da); | |
741 | flush_iotlb_page(obj, da); | |
742 | ||
743 | spin_unlock(&obj->page_table_lock); | |
744 | ||
745 | return bytes; | |
746 | } | |
747 | EXPORT_SYMBOL_GPL(iopgtable_clear_entry); | |
748 | ||
749 | static void iopgtable_clear_entry_all(struct iommu *obj) | |
750 | { | |
751 | int i; | |
752 | ||
753 | spin_lock(&obj->page_table_lock); | |
754 | ||
755 | for (i = 0; i < PTRS_PER_IOPGD; i++) { | |
756 | u32 da; | |
757 | u32 *iopgd; | |
758 | ||
759 | da = i << IOPGD_SHIFT; | |
760 | iopgd = iopgd_offset(obj, da); | |
761 | ||
762 | if (!*iopgd) | |
763 | continue; | |
764 | ||
a1a54456 | 765 | if (iopgd_is_table(*iopgd)) |
a9dcad5e HD |
766 | iopte_free(iopte_offset(iopgd, 0)); |
767 | ||
768 | *iopgd = 0; | |
769 | flush_iopgd_range(iopgd, iopgd); | |
770 | } | |
771 | ||
772 | flush_iotlb_all(obj); | |
773 | ||
774 | spin_unlock(&obj->page_table_lock); | |
775 | } | |
776 | ||
777 | /* | |
778 | * Device IOMMU generic operations | |
779 | */ | |
780 | static irqreturn_t iommu_fault_handler(int irq, void *data) | |
781 | { | |
782 | u32 stat, da; | |
783 | u32 *iopgd, *iopte; | |
784 | int err = -EIO; | |
785 | struct iommu *obj = data; | |
786 | ||
787 | if (!obj->refcount) | |
788 | return IRQ_NONE; | |
789 | ||
790 | /* Dynamic loading TLB or PTE */ | |
791 | if (obj->isr) | |
792 | err = obj->isr(obj); | |
793 | ||
794 | if (!err) | |
795 | return IRQ_HANDLED; | |
796 | ||
797 | clk_enable(obj->clk); | |
798 | stat = iommu_report_fault(obj, &da); | |
799 | clk_disable(obj->clk); | |
800 | if (!stat) | |
801 | return IRQ_HANDLED; | |
802 | ||
37b29810 HD |
803 | iommu_disable(obj); |
804 | ||
a9dcad5e HD |
805 | iopgd = iopgd_offset(obj, da); |
806 | ||
a1a54456 | 807 | if (!iopgd_is_table(*iopgd)) { |
a9dcad5e HD |
808 | dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", __func__, |
809 | da, iopgd, *iopgd); | |
810 | return IRQ_NONE; | |
811 | } | |
812 | ||
813 | iopte = iopte_offset(iopgd, da); | |
814 | ||
815 | dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", | |
816 | __func__, da, iopgd, *iopgd, iopte, *iopte); | |
817 | ||
818 | return IRQ_NONE; | |
819 | } | |
820 | ||
821 | static int device_match_by_alias(struct device *dev, void *data) | |
822 | { | |
823 | struct iommu *obj = to_iommu(dev); | |
824 | const char *name = data; | |
825 | ||
826 | pr_debug("%s: %s %s\n", __func__, obj->name, name); | |
827 | ||
828 | return strcmp(obj->name, name) == 0; | |
829 | } | |
830 | ||
831 | /** | |
832 | * iommu_get - Get iommu handler | |
833 | * @name: target iommu name | |
834 | **/ | |
835 | struct iommu *iommu_get(const char *name) | |
836 | { | |
837 | int err = -ENOMEM; | |
838 | struct device *dev; | |
839 | struct iommu *obj; | |
840 | ||
841 | dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name, | |
842 | device_match_by_alias); | |
843 | if (!dev) | |
844 | return ERR_PTR(-ENODEV); | |
845 | ||
846 | obj = to_iommu(dev); | |
847 | ||
848 | mutex_lock(&obj->iommu_lock); | |
849 | ||
850 | if (obj->refcount++ == 0) { | |
851 | err = iommu_enable(obj); | |
852 | if (err) | |
853 | goto err_enable; | |
854 | flush_iotlb_all(obj); | |
855 | } | |
856 | ||
857 | if (!try_module_get(obj->owner)) | |
858 | goto err_module; | |
859 | ||
860 | mutex_unlock(&obj->iommu_lock); | |
861 | ||
862 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); | |
863 | return obj; | |
864 | ||
865 | err_module: | |
866 | if (obj->refcount == 1) | |
867 | iommu_disable(obj); | |
868 | err_enable: | |
869 | obj->refcount--; | |
870 | mutex_unlock(&obj->iommu_lock); | |
871 | return ERR_PTR(err); | |
872 | } | |
873 | EXPORT_SYMBOL_GPL(iommu_get); | |
874 | ||
875 | /** | |
876 | * iommu_put - Put back iommu handler | |
877 | * @obj: target iommu | |
878 | **/ | |
879 | void iommu_put(struct iommu *obj) | |
880 | { | |
acf9d467 | 881 | if (!obj || IS_ERR(obj)) |
a9dcad5e HD |
882 | return; |
883 | ||
884 | mutex_lock(&obj->iommu_lock); | |
885 | ||
886 | if (--obj->refcount == 0) | |
887 | iommu_disable(obj); | |
888 | ||
889 | module_put(obj->owner); | |
890 | ||
891 | mutex_unlock(&obj->iommu_lock); | |
892 | ||
893 | dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name); | |
894 | } | |
895 | EXPORT_SYMBOL_GPL(iommu_put); | |
896 | ||
897 | /* | |
898 | * OMAP Device MMU(IOMMU) detection | |
899 | */ | |
900 | static int __devinit omap_iommu_probe(struct platform_device *pdev) | |
901 | { | |
902 | int err = -ENODEV; | |
903 | void *p; | |
904 | int irq; | |
905 | struct iommu *obj; | |
906 | struct resource *res; | |
907 | struct iommu_platform_data *pdata = pdev->dev.platform_data; | |
908 | ||
909 | if (pdev->num_resources != 2) | |
910 | return -EINVAL; | |
911 | ||
912 | obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL); | |
913 | if (!obj) | |
914 | return -ENOMEM; | |
915 | ||
916 | obj->clk = clk_get(&pdev->dev, pdata->clk_name); | |
917 | if (IS_ERR(obj->clk)) | |
918 | goto err_clk; | |
919 | ||
920 | obj->nr_tlb_entries = pdata->nr_tlb_entries; | |
921 | obj->name = pdata->name; | |
922 | obj->dev = &pdev->dev; | |
923 | obj->ctx = (void *)obj + sizeof(*obj); | |
924 | ||
925 | mutex_init(&obj->iommu_lock); | |
926 | mutex_init(&obj->mmap_lock); | |
927 | spin_lock_init(&obj->page_table_lock); | |
928 | INIT_LIST_HEAD(&obj->mmap); | |
929 | ||
930 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
931 | if (!res) { | |
932 | err = -ENODEV; | |
933 | goto err_mem; | |
934 | } | |
935 | obj->regbase = ioremap(res->start, resource_size(res)); | |
936 | if (!obj->regbase) { | |
937 | err = -ENOMEM; | |
938 | goto err_mem; | |
939 | } | |
940 | ||
941 | res = request_mem_region(res->start, resource_size(res), | |
942 | dev_name(&pdev->dev)); | |
943 | if (!res) { | |
944 | err = -EIO; | |
945 | goto err_mem; | |
946 | } | |
947 | ||
948 | irq = platform_get_irq(pdev, 0); | |
949 | if (irq < 0) { | |
950 | err = -ENODEV; | |
951 | goto err_irq; | |
952 | } | |
953 | err = request_irq(irq, iommu_fault_handler, IRQF_SHARED, | |
954 | dev_name(&pdev->dev), obj); | |
955 | if (err < 0) | |
956 | goto err_irq; | |
957 | platform_set_drvdata(pdev, obj); | |
958 | ||
959 | p = (void *)__get_free_pages(GFP_KERNEL, get_order(IOPGD_TABLE_SIZE)); | |
960 | if (!p) { | |
961 | err = -ENOMEM; | |
962 | goto err_pgd; | |
963 | } | |
964 | memset(p, 0, IOPGD_TABLE_SIZE); | |
965 | clean_dcache_area(p, IOPGD_TABLE_SIZE); | |
966 | obj->iopgd = p; | |
967 | ||
968 | BUG_ON(!IS_ALIGNED((unsigned long)obj->iopgd, IOPGD_TABLE_SIZE)); | |
969 | ||
970 | dev_info(&pdev->dev, "%s registered\n", obj->name); | |
971 | return 0; | |
972 | ||
973 | err_pgd: | |
974 | free_irq(irq, obj); | |
975 | err_irq: | |
976 | release_mem_region(res->start, resource_size(res)); | |
977 | iounmap(obj->regbase); | |
978 | err_mem: | |
979 | clk_put(obj->clk); | |
980 | err_clk: | |
981 | kfree(obj); | |
982 | return err; | |
983 | } | |
984 | ||
985 | static int __devexit omap_iommu_remove(struct platform_device *pdev) | |
986 | { | |
987 | int irq; | |
988 | struct resource *res; | |
989 | struct iommu *obj = platform_get_drvdata(pdev); | |
990 | ||
991 | platform_set_drvdata(pdev, NULL); | |
992 | ||
993 | iopgtable_clear_entry_all(obj); | |
994 | free_pages((unsigned long)obj->iopgd, get_order(IOPGD_TABLE_SIZE)); | |
995 | ||
996 | irq = platform_get_irq(pdev, 0); | |
997 | free_irq(irq, obj); | |
998 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
999 | release_mem_region(res->start, resource_size(res)); | |
1000 | iounmap(obj->regbase); | |
1001 | ||
1002 | clk_put(obj->clk); | |
1003 | dev_info(&pdev->dev, "%s removed\n", obj->name); | |
1004 | kfree(obj); | |
1005 | return 0; | |
1006 | } | |
1007 | ||
1008 | static struct platform_driver omap_iommu_driver = { | |
1009 | .probe = omap_iommu_probe, | |
1010 | .remove = __devexit_p(omap_iommu_remove), | |
1011 | .driver = { | |
1012 | .name = "omap-iommu", | |
1013 | }, | |
1014 | }; | |
1015 | ||
1016 | static void iopte_cachep_ctor(void *iopte) | |
1017 | { | |
1018 | clean_dcache_area(iopte, IOPTE_TABLE_SIZE); | |
1019 | } | |
1020 | ||
1021 | static int __init omap_iommu_init(void) | |
1022 | { | |
1023 | struct kmem_cache *p; | |
1024 | const unsigned long flags = SLAB_HWCACHE_ALIGN; | |
1025 | size_t align = 1 << 10; /* L2 pagetable alignement */ | |
1026 | ||
1027 | p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags, | |
1028 | iopte_cachep_ctor); | |
1029 | if (!p) | |
1030 | return -ENOMEM; | |
1031 | iopte_cachep = p; | |
1032 | ||
1033 | return platform_driver_register(&omap_iommu_driver); | |
1034 | } | |
1035 | module_init(omap_iommu_init); | |
1036 | ||
1037 | static void __exit omap_iommu_exit(void) | |
1038 | { | |
1039 | kmem_cache_destroy(iopte_cachep); | |
1040 | ||
1041 | platform_driver_unregister(&omap_iommu_driver); | |
1042 | } | |
1043 | module_exit(omap_iommu_exit); | |
1044 | ||
1045 | MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives"); | |
1046 | MODULE_ALIAS("platform:omap-iommu"); | |
1047 | MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi"); | |
1048 | MODULE_LICENSE("GPL v2"); |