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5e1c5ff4 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/mcbsp.c | |
3 | * | |
4 | * Copyright (C) 2004 Nokia Corporation | |
5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> | |
6 | * | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Multichannel mode not supported. | |
13 | */ | |
14 | ||
15 | #include <linux/module.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/device.h> | |
bc5d0c89 | 18 | #include <linux/platform_device.h> |
5e1c5ff4 TL |
19 | #include <linux/wait.h> |
20 | #include <linux/completion.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/err.h> | |
f8ce2547 | 23 | #include <linux/clk.h> |
04fbf6a2 | 24 | #include <linux/delay.h> |
fb78d808 | 25 | #include <linux/io.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
5e1c5ff4 | 27 | |
ce491cf8 TL |
28 | #include <plat/dma.h> |
29 | #include <plat/mcbsp.h> | |
5e1c5ff4 | 30 | |
d912fa92 EN |
31 | #include "../mach-omap2/cm-regbits-34xx.h" |
32 | ||
b4b58f58 | 33 | struct omap_mcbsp **mcbsp_ptr; |
c8c99699 | 34 | int omap_mcbsp_count, omap_mcbsp_cache_size; |
bc5d0c89 | 35 | |
b0a330dc | 36 | static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) |
b4b58f58 | 37 | { |
c8c99699 JK |
38 | if (cpu_class_is_omap1()) { |
39 | ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val; | |
8ea3200f | 40 | __raw_writew((u16)val, mcbsp->io_base + reg); |
c8c99699 JK |
41 | } else if (cpu_is_omap2420()) { |
42 | ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val; | |
43 | __raw_writew((u16)val, mcbsp->io_base + reg); | |
44 | } else { | |
45 | ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val; | |
8ea3200f | 46 | __raw_writel(val, mcbsp->io_base + reg); |
c8c99699 | 47 | } |
b4b58f58 CS |
48 | } |
49 | ||
b0a330dc | 50 | static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache) |
b4b58f58 | 51 | { |
c8c99699 JK |
52 | if (cpu_class_is_omap1()) { |
53 | return !from_cache ? __raw_readw(mcbsp->io_base + reg) : | |
54 | ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)]; | |
55 | } else if (cpu_is_omap2420()) { | |
56 | return !from_cache ? __raw_readw(mcbsp->io_base + reg) : | |
57 | ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)]; | |
58 | } else { | |
59 | return !from_cache ? __raw_readl(mcbsp->io_base + reg) : | |
60 | ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)]; | |
61 | } | |
b4b58f58 CS |
62 | } |
63 | ||
d912fa92 | 64 | #ifdef CONFIG_ARCH_OMAP3 |
b0a330dc | 65 | static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val) |
d912fa92 EN |
66 | { |
67 | __raw_writel(val, mcbsp->st_data->io_base_st + reg); | |
68 | } | |
69 | ||
b0a330dc | 70 | static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg) |
d912fa92 EN |
71 | { |
72 | return __raw_readl(mcbsp->st_data->io_base_st + reg); | |
73 | } | |
74 | #endif | |
75 | ||
8ea3200f | 76 | #define MCBSP_READ(mcbsp, reg) \ |
c8c99699 | 77 | omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0) |
8ea3200f JK |
78 | #define MCBSP_WRITE(mcbsp, reg, val) \ |
79 | omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val) | |
c8c99699 JK |
80 | #define MCBSP_READ_CACHE(mcbsp, reg) \ |
81 | omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1) | |
b4b58f58 | 82 | |
d912fa92 EN |
83 | #define MCBSP_ST_READ(mcbsp, reg) \ |
84 | omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg) | |
85 | #define MCBSP_ST_WRITE(mcbsp, reg, val) \ | |
86 | omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val) | |
87 | ||
5e1c5ff4 TL |
88 | static void omap_mcbsp_dump_reg(u8 id) |
89 | { | |
b4b58f58 CS |
90 | struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id); |
91 | ||
92 | dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id); | |
93 | dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n", | |
8ea3200f | 94 | MCBSP_READ(mcbsp, DRR2)); |
b4b58f58 | 95 | dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n", |
8ea3200f | 96 | MCBSP_READ(mcbsp, DRR1)); |
b4b58f58 | 97 | dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n", |
8ea3200f | 98 | MCBSP_READ(mcbsp, DXR2)); |
b4b58f58 | 99 | dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n", |
8ea3200f | 100 | MCBSP_READ(mcbsp, DXR1)); |
b4b58f58 | 101 | dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n", |
8ea3200f | 102 | MCBSP_READ(mcbsp, SPCR2)); |
b4b58f58 | 103 | dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n", |
8ea3200f | 104 | MCBSP_READ(mcbsp, SPCR1)); |
b4b58f58 | 105 | dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n", |
8ea3200f | 106 | MCBSP_READ(mcbsp, RCR2)); |
b4b58f58 | 107 | dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n", |
8ea3200f | 108 | MCBSP_READ(mcbsp, RCR1)); |
b4b58f58 | 109 | dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n", |
8ea3200f | 110 | MCBSP_READ(mcbsp, XCR2)); |
b4b58f58 | 111 | dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n", |
8ea3200f | 112 | MCBSP_READ(mcbsp, XCR1)); |
b4b58f58 | 113 | dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n", |
8ea3200f | 114 | MCBSP_READ(mcbsp, SRGR2)); |
b4b58f58 | 115 | dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n", |
8ea3200f | 116 | MCBSP_READ(mcbsp, SRGR1)); |
b4b58f58 | 117 | dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n", |
8ea3200f | 118 | MCBSP_READ(mcbsp, PCR0)); |
b4b58f58 | 119 | dev_dbg(mcbsp->dev, "***********************\n"); |
5e1c5ff4 TL |
120 | } |
121 | ||
0cd61b68 | 122 | static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id) |
5e1c5ff4 | 123 | { |
e8f2af17 | 124 | struct omap_mcbsp *mcbsp_tx = dev_id; |
d6d834b0 | 125 | u16 irqst_spcr2; |
5e1c5ff4 | 126 | |
8ea3200f | 127 | irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2); |
d6d834b0 | 128 | dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2); |
5e1c5ff4 | 129 | |
d6d834b0 EN |
130 | if (irqst_spcr2 & XSYNC_ERR) { |
131 | dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n", | |
132 | irqst_spcr2); | |
133 | /* Writing zero to XSYNC_ERR clears the IRQ */ | |
0841cb82 | 134 | MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2)); |
d6d834b0 EN |
135 | } else { |
136 | complete(&mcbsp_tx->tx_irq_completion); | |
137 | } | |
fb78d808 | 138 | |
5e1c5ff4 TL |
139 | return IRQ_HANDLED; |
140 | } | |
141 | ||
0cd61b68 | 142 | static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id) |
5e1c5ff4 | 143 | { |
e8f2af17 | 144 | struct omap_mcbsp *mcbsp_rx = dev_id; |
d6d834b0 EN |
145 | u16 irqst_spcr1; |
146 | ||
8ea3200f | 147 | irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1); |
d6d834b0 EN |
148 | dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1); |
149 | ||
150 | if (irqst_spcr1 & RSYNC_ERR) { | |
151 | dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n", | |
152 | irqst_spcr1); | |
153 | /* Writing zero to RSYNC_ERR clears the IRQ */ | |
0841cb82 | 154 | MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1)); |
d6d834b0 EN |
155 | } else { |
156 | complete(&mcbsp_rx->tx_irq_completion); | |
157 | } | |
fb78d808 | 158 | |
5e1c5ff4 TL |
159 | return IRQ_HANDLED; |
160 | } | |
161 | ||
5e1c5ff4 TL |
162 | static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data) |
163 | { | |
e8f2af17 | 164 | struct omap_mcbsp *mcbsp_dma_tx = data; |
5e1c5ff4 | 165 | |
bc5d0c89 | 166 | dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n", |
8ea3200f | 167 | MCBSP_READ(mcbsp_dma_tx, SPCR2)); |
5e1c5ff4 TL |
168 | |
169 | /* We can free the channels */ | |
170 | omap_free_dma(mcbsp_dma_tx->dma_tx_lch); | |
171 | mcbsp_dma_tx->dma_tx_lch = -1; | |
172 | ||
173 | complete(&mcbsp_dma_tx->tx_dma_completion); | |
174 | } | |
175 | ||
176 | static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data) | |
177 | { | |
e8f2af17 | 178 | struct omap_mcbsp *mcbsp_dma_rx = data; |
5e1c5ff4 | 179 | |
bc5d0c89 | 180 | dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n", |
8ea3200f | 181 | MCBSP_READ(mcbsp_dma_rx, SPCR2)); |
5e1c5ff4 TL |
182 | |
183 | /* We can free the channels */ | |
184 | omap_free_dma(mcbsp_dma_rx->dma_rx_lch); | |
185 | mcbsp_dma_rx->dma_rx_lch = -1; | |
186 | ||
187 | complete(&mcbsp_dma_rx->rx_dma_completion); | |
188 | } | |
189 | ||
5e1c5ff4 TL |
190 | /* |
191 | * omap_mcbsp_config simply write a config to the | |
192 | * appropriate McBSP. | |
193 | * You either call this function or set the McBSP registers | |
194 | * by yourself before calling omap_mcbsp_start(). | |
195 | */ | |
fb78d808 | 196 | void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config) |
5e1c5ff4 | 197 | { |
b4b58f58 | 198 | struct omap_mcbsp *mcbsp; |
5e1c5ff4 | 199 | |
bc5d0c89 EV |
200 | if (!omap_mcbsp_check_valid_id(id)) { |
201 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
202 | return; | |
203 | } | |
b4b58f58 | 204 | mcbsp = id_to_mcbsp_ptr(id); |
bc5d0c89 | 205 | |
b4b58f58 CS |
206 | dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n", |
207 | mcbsp->id, mcbsp->phys_base); | |
5e1c5ff4 TL |
208 | |
209 | /* We write the given config */ | |
8ea3200f JK |
210 | MCBSP_WRITE(mcbsp, SPCR2, config->spcr2); |
211 | MCBSP_WRITE(mcbsp, SPCR1, config->spcr1); | |
212 | MCBSP_WRITE(mcbsp, RCR2, config->rcr2); | |
213 | MCBSP_WRITE(mcbsp, RCR1, config->rcr1); | |
214 | MCBSP_WRITE(mcbsp, XCR2, config->xcr2); | |
215 | MCBSP_WRITE(mcbsp, XCR1, config->xcr1); | |
216 | MCBSP_WRITE(mcbsp, SRGR2, config->srgr2); | |
217 | MCBSP_WRITE(mcbsp, SRGR1, config->srgr1); | |
218 | MCBSP_WRITE(mcbsp, MCR2, config->mcr2); | |
219 | MCBSP_WRITE(mcbsp, MCR1, config->mcr1); | |
220 | MCBSP_WRITE(mcbsp, PCR0, config->pcr0); | |
a5b92cc3 | 221 | if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { |
8ea3200f JK |
222 | MCBSP_WRITE(mcbsp, XCCR, config->xccr); |
223 | MCBSP_WRITE(mcbsp, RCCR, config->rccr); | |
3127f8f8 | 224 | } |
5e1c5ff4 | 225 | } |
fb78d808 | 226 | EXPORT_SYMBOL(omap_mcbsp_config); |
5e1c5ff4 | 227 | |
a8eb7ca0 | 228 | #ifdef CONFIG_ARCH_OMAP3 |
d912fa92 EN |
229 | static void omap_st_on(struct omap_mcbsp *mcbsp) |
230 | { | |
231 | unsigned int w; | |
232 | ||
233 | /* | |
234 | * Sidetone uses McBSP ICLK - which must not idle when sidetones | |
235 | * are enabled or sidetones start sounding ugly. | |
236 | */ | |
237 | w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); | |
238 | w &= ~(1 << (mcbsp->id - 2)); | |
239 | cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); | |
240 | ||
241 | /* Enable McBSP Sidetone */ | |
242 | w = MCBSP_READ(mcbsp, SSELCR); | |
243 | MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN); | |
244 | ||
245 | w = MCBSP_ST_READ(mcbsp, SYSCONFIG); | |
246 | MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE)); | |
247 | ||
248 | /* Enable Sidetone from Sidetone Core */ | |
249 | w = MCBSP_ST_READ(mcbsp, SSELCR); | |
250 | MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN); | |
251 | } | |
252 | ||
253 | static void omap_st_off(struct omap_mcbsp *mcbsp) | |
254 | { | |
255 | unsigned int w; | |
256 | ||
257 | w = MCBSP_ST_READ(mcbsp, SSELCR); | |
258 | MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN)); | |
259 | ||
260 | w = MCBSP_ST_READ(mcbsp, SYSCONFIG); | |
261 | MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE); | |
262 | ||
263 | w = MCBSP_READ(mcbsp, SSELCR); | |
264 | MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN)); | |
265 | ||
266 | w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); | |
267 | w |= 1 << (mcbsp->id - 2); | |
268 | cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); | |
269 | } | |
270 | ||
271 | static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir) | |
272 | { | |
273 | u16 val, i; | |
274 | ||
275 | val = MCBSP_ST_READ(mcbsp, SYSCONFIG); | |
276 | MCBSP_ST_WRITE(mcbsp, SYSCONFIG, val & ~(ST_AUTOIDLE)); | |
277 | ||
278 | val = MCBSP_ST_READ(mcbsp, SSELCR); | |
279 | ||
280 | if (val & ST_COEFFWREN) | |
281 | MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN)); | |
282 | ||
283 | MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN); | |
284 | ||
285 | for (i = 0; i < 128; i++) | |
286 | MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]); | |
287 | ||
288 | i = 0; | |
289 | ||
290 | val = MCBSP_ST_READ(mcbsp, SSELCR); | |
291 | while (!(val & ST_COEFFWRDONE) && (++i < 1000)) | |
292 | val = MCBSP_ST_READ(mcbsp, SSELCR); | |
293 | ||
294 | MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN)); | |
295 | ||
296 | if (i == 1000) | |
297 | dev_err(mcbsp->dev, "McBSP FIR load error!\n"); | |
298 | } | |
299 | ||
300 | static void omap_st_chgain(struct omap_mcbsp *mcbsp) | |
301 | { | |
302 | u16 w; | |
303 | struct omap_mcbsp_st_data *st_data = mcbsp->st_data; | |
304 | ||
305 | w = MCBSP_ST_READ(mcbsp, SYSCONFIG); | |
306 | MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE)); | |
307 | ||
308 | w = MCBSP_ST_READ(mcbsp, SSELCR); | |
309 | ||
310 | MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \ | |
311 | ST_CH1GAIN(st_data->ch1gain)); | |
312 | } | |
313 | ||
314 | int omap_st_set_chgain(unsigned int id, int channel, s16 chgain) | |
315 | { | |
316 | struct omap_mcbsp *mcbsp; | |
317 | struct omap_mcbsp_st_data *st_data; | |
318 | int ret = 0; | |
319 | ||
320 | if (!omap_mcbsp_check_valid_id(id)) { | |
321 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
322 | return -ENODEV; | |
323 | } | |
324 | ||
325 | mcbsp = id_to_mcbsp_ptr(id); | |
326 | st_data = mcbsp->st_data; | |
327 | ||
328 | if (!st_data) | |
329 | return -ENOENT; | |
330 | ||
331 | spin_lock_irq(&mcbsp->lock); | |
332 | if (channel == 0) | |
333 | st_data->ch0gain = chgain; | |
334 | else if (channel == 1) | |
335 | st_data->ch1gain = chgain; | |
336 | else | |
337 | ret = -EINVAL; | |
338 | ||
339 | if (st_data->enabled) | |
340 | omap_st_chgain(mcbsp); | |
341 | spin_unlock_irq(&mcbsp->lock); | |
342 | ||
343 | return ret; | |
344 | } | |
345 | EXPORT_SYMBOL(omap_st_set_chgain); | |
346 | ||
347 | int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain) | |
348 | { | |
349 | struct omap_mcbsp *mcbsp; | |
350 | struct omap_mcbsp_st_data *st_data; | |
351 | int ret = 0; | |
352 | ||
353 | if (!omap_mcbsp_check_valid_id(id)) { | |
354 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
355 | return -ENODEV; | |
356 | } | |
357 | ||
358 | mcbsp = id_to_mcbsp_ptr(id); | |
359 | st_data = mcbsp->st_data; | |
360 | ||
361 | if (!st_data) | |
362 | return -ENOENT; | |
363 | ||
364 | spin_lock_irq(&mcbsp->lock); | |
365 | if (channel == 0) | |
366 | *chgain = st_data->ch0gain; | |
367 | else if (channel == 1) | |
368 | *chgain = st_data->ch1gain; | |
369 | else | |
370 | ret = -EINVAL; | |
371 | spin_unlock_irq(&mcbsp->lock); | |
372 | ||
373 | return ret; | |
374 | } | |
375 | EXPORT_SYMBOL(omap_st_get_chgain); | |
376 | ||
377 | static int omap_st_start(struct omap_mcbsp *mcbsp) | |
378 | { | |
379 | struct omap_mcbsp_st_data *st_data = mcbsp->st_data; | |
380 | ||
381 | if (st_data && st_data->enabled && !st_data->running) { | |
382 | omap_st_fir_write(mcbsp, st_data->taps); | |
383 | omap_st_chgain(mcbsp); | |
384 | ||
385 | if (!mcbsp->free) { | |
386 | omap_st_on(mcbsp); | |
387 | st_data->running = 1; | |
388 | } | |
389 | } | |
390 | ||
391 | return 0; | |
392 | } | |
393 | ||
394 | int omap_st_enable(unsigned int id) | |
395 | { | |
396 | struct omap_mcbsp *mcbsp; | |
397 | struct omap_mcbsp_st_data *st_data; | |
398 | ||
399 | if (!omap_mcbsp_check_valid_id(id)) { | |
400 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
401 | return -ENODEV; | |
402 | } | |
403 | ||
404 | mcbsp = id_to_mcbsp_ptr(id); | |
405 | st_data = mcbsp->st_data; | |
406 | ||
407 | if (!st_data) | |
408 | return -ENODEV; | |
409 | ||
410 | spin_lock_irq(&mcbsp->lock); | |
411 | st_data->enabled = 1; | |
412 | omap_st_start(mcbsp); | |
413 | spin_unlock_irq(&mcbsp->lock); | |
414 | ||
415 | return 0; | |
416 | } | |
417 | EXPORT_SYMBOL(omap_st_enable); | |
418 | ||
419 | static int omap_st_stop(struct omap_mcbsp *mcbsp) | |
420 | { | |
421 | struct omap_mcbsp_st_data *st_data = mcbsp->st_data; | |
422 | ||
423 | if (st_data && st_data->running) { | |
424 | if (!mcbsp->free) { | |
425 | omap_st_off(mcbsp); | |
426 | st_data->running = 0; | |
427 | } | |
428 | } | |
429 | ||
430 | return 0; | |
431 | } | |
432 | ||
433 | int omap_st_disable(unsigned int id) | |
434 | { | |
435 | struct omap_mcbsp *mcbsp; | |
436 | struct omap_mcbsp_st_data *st_data; | |
437 | int ret = 0; | |
438 | ||
439 | if (!omap_mcbsp_check_valid_id(id)) { | |
440 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
441 | return -ENODEV; | |
442 | } | |
443 | ||
444 | mcbsp = id_to_mcbsp_ptr(id); | |
445 | st_data = mcbsp->st_data; | |
446 | ||
447 | if (!st_data) | |
448 | return -ENODEV; | |
449 | ||
450 | spin_lock_irq(&mcbsp->lock); | |
451 | omap_st_stop(mcbsp); | |
452 | st_data->enabled = 0; | |
453 | spin_unlock_irq(&mcbsp->lock); | |
454 | ||
455 | return ret; | |
456 | } | |
457 | EXPORT_SYMBOL(omap_st_disable); | |
458 | ||
459 | int omap_st_is_enabled(unsigned int id) | |
460 | { | |
461 | struct omap_mcbsp *mcbsp; | |
462 | struct omap_mcbsp_st_data *st_data; | |
463 | ||
464 | if (!omap_mcbsp_check_valid_id(id)) { | |
465 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
466 | return -ENODEV; | |
467 | } | |
468 | ||
469 | mcbsp = id_to_mcbsp_ptr(id); | |
470 | st_data = mcbsp->st_data; | |
471 | ||
472 | if (!st_data) | |
473 | return -ENODEV; | |
474 | ||
475 | ||
476 | return st_data->enabled; | |
477 | } | |
478 | EXPORT_SYMBOL(omap_st_is_enabled); | |
479 | ||
7aa9ff56 | 480 | /* |
451fd82d PU |
481 | * omap_mcbsp_set_rx_threshold configures the transmit threshold in words. |
482 | * The threshold parameter is 1 based, and it is converted (threshold - 1) | |
483 | * for the THRSH2 register. | |
7aa9ff56 EV |
484 | */ |
485 | void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold) | |
486 | { | |
487 | struct omap_mcbsp *mcbsp; | |
7aa9ff56 | 488 | |
752ec2f2 | 489 | if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) |
7aa9ff56 EV |
490 | return; |
491 | ||
492 | if (!omap_mcbsp_check_valid_id(id)) { | |
493 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
494 | return; | |
495 | } | |
496 | mcbsp = id_to_mcbsp_ptr(id); | |
7aa9ff56 | 497 | |
451fd82d PU |
498 | if (threshold && threshold <= mcbsp->max_tx_thres) |
499 | MCBSP_WRITE(mcbsp, THRSH2, threshold - 1); | |
7aa9ff56 EV |
500 | } |
501 | EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold); | |
502 | ||
503 | /* | |
451fd82d PU |
504 | * omap_mcbsp_set_rx_threshold configures the receive threshold in words. |
505 | * The threshold parameter is 1 based, and it is converted (threshold - 1) | |
506 | * for the THRSH1 register. | |
7aa9ff56 EV |
507 | */ |
508 | void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold) | |
509 | { | |
510 | struct omap_mcbsp *mcbsp; | |
7aa9ff56 | 511 | |
752ec2f2 | 512 | if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) |
7aa9ff56 EV |
513 | return; |
514 | ||
515 | if (!omap_mcbsp_check_valid_id(id)) { | |
516 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
517 | return; | |
518 | } | |
519 | mcbsp = id_to_mcbsp_ptr(id); | |
7aa9ff56 | 520 | |
451fd82d PU |
521 | if (threshold && threshold <= mcbsp->max_rx_thres) |
522 | MCBSP_WRITE(mcbsp, THRSH1, threshold - 1); | |
7aa9ff56 EV |
523 | } |
524 | EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold); | |
a1a56f5f EV |
525 | |
526 | /* | |
527 | * omap_mcbsp_get_max_tx_thres just return the current configured | |
528 | * maximum threshold for transmission | |
529 | */ | |
530 | u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) | |
531 | { | |
532 | struct omap_mcbsp *mcbsp; | |
533 | ||
534 | if (!omap_mcbsp_check_valid_id(id)) { | |
535 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
536 | return -ENODEV; | |
537 | } | |
538 | mcbsp = id_to_mcbsp_ptr(id); | |
539 | ||
540 | return mcbsp->max_tx_thres; | |
541 | } | |
542 | EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold); | |
543 | ||
544 | /* | |
545 | * omap_mcbsp_get_max_rx_thres just return the current configured | |
546 | * maximum threshold for reception | |
547 | */ | |
548 | u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) | |
549 | { | |
550 | struct omap_mcbsp *mcbsp; | |
551 | ||
552 | if (!omap_mcbsp_check_valid_id(id)) { | |
553 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
554 | return -ENODEV; | |
555 | } | |
556 | mcbsp = id_to_mcbsp_ptr(id); | |
557 | ||
558 | return mcbsp->max_rx_thres; | |
559 | } | |
560 | EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold); | |
98cb20e8 | 561 | |
0acce82b PU |
562 | u16 omap_mcbsp_get_fifo_size(unsigned int id) |
563 | { | |
564 | struct omap_mcbsp *mcbsp; | |
565 | ||
566 | if (!omap_mcbsp_check_valid_id(id)) { | |
567 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
568 | return -ENODEV; | |
569 | } | |
570 | mcbsp = id_to_mcbsp_ptr(id); | |
571 | ||
572 | return mcbsp->pdata->buffer_size; | |
573 | } | |
574 | EXPORT_SYMBOL(omap_mcbsp_get_fifo_size); | |
575 | ||
7dc976ed PU |
576 | /* |
577 | * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO | |
578 | */ | |
579 | u16 omap_mcbsp_get_tx_delay(unsigned int id) | |
580 | { | |
581 | struct omap_mcbsp *mcbsp; | |
582 | u16 buffstat; | |
583 | ||
584 | if (!omap_mcbsp_check_valid_id(id)) { | |
585 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
586 | return -ENODEV; | |
587 | } | |
588 | mcbsp = id_to_mcbsp_ptr(id); | |
589 | ||
590 | /* Returns the number of free locations in the buffer */ | |
591 | buffstat = MCBSP_READ(mcbsp, XBUFFSTAT); | |
592 | ||
593 | /* Number of slots are different in McBSP ports */ | |
f10b8ad1 | 594 | return mcbsp->pdata->buffer_size - buffstat; |
7dc976ed PU |
595 | } |
596 | EXPORT_SYMBOL(omap_mcbsp_get_tx_delay); | |
597 | ||
598 | /* | |
599 | * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO | |
600 | * to reach the threshold value (when the DMA will be triggered to read it) | |
601 | */ | |
602 | u16 omap_mcbsp_get_rx_delay(unsigned int id) | |
603 | { | |
604 | struct omap_mcbsp *mcbsp; | |
605 | u16 buffstat, threshold; | |
606 | ||
607 | if (!omap_mcbsp_check_valid_id(id)) { | |
608 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
609 | return -ENODEV; | |
610 | } | |
611 | mcbsp = id_to_mcbsp_ptr(id); | |
612 | ||
613 | /* Returns the number of used locations in the buffer */ | |
614 | buffstat = MCBSP_READ(mcbsp, RBUFFSTAT); | |
615 | /* RX threshold */ | |
616 | threshold = MCBSP_READ(mcbsp, THRSH1); | |
617 | ||
618 | /* Return the number of location till we reach the threshold limit */ | |
619 | if (threshold <= buffstat) | |
620 | return 0; | |
621 | else | |
622 | return threshold - buffstat; | |
623 | } | |
624 | EXPORT_SYMBOL(omap_mcbsp_get_rx_delay); | |
625 | ||
98cb20e8 PU |
626 | /* |
627 | * omap_mcbsp_get_dma_op_mode just return the current configured | |
628 | * operating mode for the mcbsp channel | |
629 | */ | |
630 | int omap_mcbsp_get_dma_op_mode(unsigned int id) | |
631 | { | |
632 | struct omap_mcbsp *mcbsp; | |
633 | int dma_op_mode; | |
634 | ||
635 | if (!omap_mcbsp_check_valid_id(id)) { | |
636 | printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1); | |
637 | return -ENODEV; | |
638 | } | |
639 | mcbsp = id_to_mcbsp_ptr(id); | |
640 | ||
98cb20e8 | 641 | dma_op_mode = mcbsp->dma_op_mode; |
98cb20e8 PU |
642 | |
643 | return dma_op_mode; | |
644 | } | |
645 | EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode); | |
2122fdc6 EN |
646 | |
647 | static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) | |
648 | { | |
649 | /* | |
650 | * Enable wakup behavior, smart idle and all wakeups | |
651 | * REVISIT: some wakeups may be unnecessary | |
652 | */ | |
752ec2f2 | 653 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { |
2122fdc6 EN |
654 | u16 syscon; |
655 | ||
8ea3200f | 656 | syscon = MCBSP_READ(mcbsp, SYSCON); |
2ba93f8f | 657 | syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03)); |
d99a7454 | 658 | |
fa3935ba EN |
659 | if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) { |
660 | syscon |= (ENAWAKEUP | SIDLEMODE(0x02) | | |
661 | CLOCKACTIVITY(0x02)); | |
8ea3200f | 662 | MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN); |
fa3935ba | 663 | } else { |
d99a7454 | 664 | syscon |= SIDLEMODE(0x01); |
fa3935ba | 665 | } |
d99a7454 | 666 | |
8ea3200f | 667 | MCBSP_WRITE(mcbsp, SYSCON, syscon); |
2122fdc6 EN |
668 | } |
669 | } | |
670 | ||
671 | static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) | |
672 | { | |
673 | /* | |
674 | * Disable wakup behavior, smart idle and all wakeups | |
675 | */ | |
752ec2f2 | 676 | if (cpu_is_omap34xx() || cpu_is_omap44xx()) { |
2122fdc6 | 677 | u16 syscon; |
2122fdc6 | 678 | |
8ea3200f | 679 | syscon = MCBSP_READ(mcbsp, SYSCON); |
2ba93f8f | 680 | syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03)); |
72cc6d71 EN |
681 | /* |
682 | * HW bug workaround - If no_idle mode is taken, we need to | |
683 | * go to smart_idle before going to always_idle, or the | |
684 | * device will not hit retention anymore. | |
685 | */ | |
686 | syscon |= SIDLEMODE(0x02); | |
8ea3200f | 687 | MCBSP_WRITE(mcbsp, SYSCON, syscon); |
72cc6d71 EN |
688 | |
689 | syscon &= ~(SIDLEMODE(0x03)); | |
8ea3200f | 690 | MCBSP_WRITE(mcbsp, SYSCON, syscon); |
2122fdc6 | 691 | |
8ea3200f | 692 | MCBSP_WRITE(mcbsp, WAKEUPEN, 0); |
2122fdc6 EN |
693 | } |
694 | } | |
695 | #else | |
696 | static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {} | |
697 | static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {} | |
d912fa92 EN |
698 | static inline void omap_st_start(struct omap_mcbsp *mcbsp) {} |
699 | static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {} | |
7aa9ff56 EV |
700 | #endif |
701 | ||
120db2cb TL |
702 | /* |
703 | * We can choose between IRQ based or polled IO. | |
704 | * This needs to be called before omap_mcbsp_request(). | |
705 | */ | |
706 | int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type) | |
707 | { | |
b4b58f58 CS |
708 | struct omap_mcbsp *mcbsp; |
709 | ||
bc5d0c89 EV |
710 | if (!omap_mcbsp_check_valid_id(id)) { |
711 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
712 | return -ENODEV; | |
713 | } | |
b4b58f58 | 714 | mcbsp = id_to_mcbsp_ptr(id); |
120db2cb | 715 | |
b4b58f58 | 716 | spin_lock(&mcbsp->lock); |
120db2cb | 717 | |
b4b58f58 CS |
718 | if (!mcbsp->free) { |
719 | dev_err(mcbsp->dev, "McBSP%d is currently in use\n", | |
720 | mcbsp->id); | |
721 | spin_unlock(&mcbsp->lock); | |
120db2cb TL |
722 | return -EINVAL; |
723 | } | |
724 | ||
b4b58f58 | 725 | mcbsp->io_type = io_type; |
120db2cb | 726 | |
b4b58f58 | 727 | spin_unlock(&mcbsp->lock); |
120db2cb TL |
728 | |
729 | return 0; | |
730 | } | |
fb78d808 | 731 | EXPORT_SYMBOL(omap_mcbsp_set_io_type); |
5e1c5ff4 | 732 | |
5e1c5ff4 TL |
733 | int omap_mcbsp_request(unsigned int id) |
734 | { | |
b4b58f58 | 735 | struct omap_mcbsp *mcbsp; |
c8c99699 | 736 | void *reg_cache; |
5e1c5ff4 TL |
737 | int err; |
738 | ||
bc5d0c89 EV |
739 | if (!omap_mcbsp_check_valid_id(id)) { |
740 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
741 | return -ENODEV; | |
120db2cb | 742 | } |
b4b58f58 | 743 | mcbsp = id_to_mcbsp_ptr(id); |
bc5d0c89 | 744 | |
c8c99699 JK |
745 | reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL); |
746 | if (!reg_cache) { | |
747 | return -ENOMEM; | |
748 | } | |
749 | ||
b4b58f58 CS |
750 | spin_lock(&mcbsp->lock); |
751 | if (!mcbsp->free) { | |
752 | dev_err(mcbsp->dev, "McBSP%d is currently in use\n", | |
753 | mcbsp->id); | |
c8c99699 JK |
754 | err = -EBUSY; |
755 | goto err_kfree; | |
5e1c5ff4 TL |
756 | } |
757 | ||
b4b58f58 | 758 | mcbsp->free = 0; |
c8c99699 | 759 | mcbsp->reg_cache = reg_cache; |
b4b58f58 | 760 | spin_unlock(&mcbsp->lock); |
5e1c5ff4 | 761 | |
b820ce4e RK |
762 | if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request) |
763 | mcbsp->pdata->ops->request(id); | |
764 | ||
765 | clk_enable(mcbsp->iclk); | |
766 | clk_enable(mcbsp->fclk); | |
767 | ||
2122fdc6 EN |
768 | /* Do procedure specific to omap34xx arch, if applicable */ |
769 | omap34xx_mcbsp_request(mcbsp); | |
770 | ||
5a07055a JN |
771 | /* |
772 | * Make sure that transmitter, receiver and sample-rate generator are | |
773 | * not running before activating IRQs. | |
774 | */ | |
8ea3200f JK |
775 | MCBSP_WRITE(mcbsp, SPCR1, 0); |
776 | MCBSP_WRITE(mcbsp, SPCR2, 0); | |
5a07055a | 777 | |
b4b58f58 | 778 | if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { |
120db2cb | 779 | /* We need to get IRQs here */ |
5a07055a | 780 | init_completion(&mcbsp->tx_irq_completion); |
b4b58f58 CS |
781 | err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, |
782 | 0, "McBSP", (void *)mcbsp); | |
120db2cb | 783 | if (err != 0) { |
b4b58f58 CS |
784 | dev_err(mcbsp->dev, "Unable to request TX IRQ %d " |
785 | "for McBSP%d\n", mcbsp->tx_irq, | |
786 | mcbsp->id); | |
c8c99699 | 787 | goto err_clk_disable; |
120db2cb | 788 | } |
5e1c5ff4 | 789 | |
9319b9da JEC |
790 | if (mcbsp->rx_irq) { |
791 | init_completion(&mcbsp->rx_irq_completion); | |
792 | err = request_irq(mcbsp->rx_irq, | |
793 | omap_mcbsp_rx_irq_handler, | |
b4b58f58 | 794 | 0, "McBSP", (void *)mcbsp); |
9319b9da JEC |
795 | if (err != 0) { |
796 | dev_err(mcbsp->dev, "Unable to request RX IRQ %d " | |
797 | "for McBSP%d\n", mcbsp->rx_irq, | |
798 | mcbsp->id); | |
799 | goto err_free_irq; | |
800 | } | |
120db2cb | 801 | } |
5e1c5ff4 TL |
802 | } |
803 | ||
5e1c5ff4 | 804 | return 0; |
c8c99699 | 805 | err_free_irq: |
1866b545 | 806 | free_irq(mcbsp->tx_irq, (void *)mcbsp); |
c8c99699 | 807 | err_clk_disable: |
1866b545 | 808 | if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free) |
c8c99699 | 809 | mcbsp->pdata->ops->free(id); |
1866b545 JK |
810 | |
811 | /* Do procedure specific to omap34xx arch, if applicable */ | |
812 | omap34xx_mcbsp_free(mcbsp); | |
813 | ||
814 | clk_disable(mcbsp->fclk); | |
815 | clk_disable(mcbsp->iclk); | |
816 | ||
c8c99699 | 817 | spin_lock(&mcbsp->lock); |
1866b545 | 818 | mcbsp->free = 1; |
c8c99699 JK |
819 | mcbsp->reg_cache = NULL; |
820 | err_kfree: | |
821 | spin_unlock(&mcbsp->lock); | |
822 | kfree(reg_cache); | |
1866b545 JK |
823 | |
824 | return err; | |
5e1c5ff4 | 825 | } |
fb78d808 | 826 | EXPORT_SYMBOL(omap_mcbsp_request); |
5e1c5ff4 TL |
827 | |
828 | void omap_mcbsp_free(unsigned int id) | |
829 | { | |
b4b58f58 | 830 | struct omap_mcbsp *mcbsp; |
c8c99699 | 831 | void *reg_cache; |
b4b58f58 | 832 | |
bc5d0c89 EV |
833 | if (!omap_mcbsp_check_valid_id(id)) { |
834 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
5e1c5ff4 | 835 | return; |
120db2cb | 836 | } |
b4b58f58 | 837 | mcbsp = id_to_mcbsp_ptr(id); |
bc5d0c89 | 838 | |
b4b58f58 CS |
839 | if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free) |
840 | mcbsp->pdata->ops->free(id); | |
bc5d0c89 | 841 | |
2122fdc6 EN |
842 | /* Do procedure specific to omap34xx arch, if applicable */ |
843 | omap34xx_mcbsp_free(mcbsp); | |
844 | ||
b820ce4e RK |
845 | clk_disable(mcbsp->fclk); |
846 | clk_disable(mcbsp->iclk); | |
847 | ||
848 | if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { | |
849 | /* Free IRQs */ | |
9319b9da JEC |
850 | if (mcbsp->rx_irq) |
851 | free_irq(mcbsp->rx_irq, (void *)mcbsp); | |
b820ce4e RK |
852 | free_irq(mcbsp->tx_irq, (void *)mcbsp); |
853 | } | |
5e1c5ff4 | 854 | |
c8c99699 | 855 | reg_cache = mcbsp->reg_cache; |
5e1c5ff4 | 856 | |
c8c99699 JK |
857 | spin_lock(&mcbsp->lock); |
858 | if (mcbsp->free) | |
859 | dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id); | |
860 | else | |
861 | mcbsp->free = 1; | |
862 | mcbsp->reg_cache = NULL; | |
b4b58f58 | 863 | spin_unlock(&mcbsp->lock); |
c8c99699 JK |
864 | |
865 | if (reg_cache) | |
866 | kfree(reg_cache); | |
5e1c5ff4 | 867 | } |
fb78d808 | 868 | EXPORT_SYMBOL(omap_mcbsp_free); |
5e1c5ff4 TL |
869 | |
870 | /* | |
c12abc01 JN |
871 | * Here we start the McBSP, by enabling transmitter, receiver or both. |
872 | * If no transmitter or receiver is active prior calling, then sample-rate | |
873 | * generator and frame sync are started. | |
5e1c5ff4 | 874 | */ |
c12abc01 | 875 | void omap_mcbsp_start(unsigned int id, int tx, int rx) |
5e1c5ff4 | 876 | { |
b4b58f58 | 877 | struct omap_mcbsp *mcbsp; |
ce3f054b | 878 | int enable_srg = 0; |
5e1c5ff4 TL |
879 | u16 w; |
880 | ||
bc5d0c89 EV |
881 | if (!omap_mcbsp_check_valid_id(id)) { |
882 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
5e1c5ff4 | 883 | return; |
bc5d0c89 | 884 | } |
b4b58f58 | 885 | mcbsp = id_to_mcbsp_ptr(id); |
5e1c5ff4 | 886 | |
d912fa92 EN |
887 | if (cpu_is_omap34xx()) |
888 | omap_st_start(mcbsp); | |
889 | ||
96fbd745 JK |
890 | mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7; |
891 | mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7; | |
5e1c5ff4 | 892 | |
ce3f054b PU |
893 | /* Only enable SRG, if McBSP is master */ |
894 | w = MCBSP_READ_CACHE(mcbsp, PCR0); | |
895 | if (w & (FSXM | FSRM | CLKXM | CLKRM)) | |
896 | enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | | |
897 | MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); | |
c12abc01 | 898 | |
ce3f054b | 899 | if (enable_srg) { |
c12abc01 | 900 | /* Start the sample generator */ |
96fbd745 | 901 | w = MCBSP_READ_CACHE(mcbsp, SPCR2); |
8ea3200f | 902 | MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6)); |
c12abc01 | 903 | } |
5e1c5ff4 TL |
904 | |
905 | /* Enable transmitter and receiver */ | |
d09a2afc | 906 | tx &= 1; |
96fbd745 | 907 | w = MCBSP_READ_CACHE(mcbsp, SPCR2); |
8ea3200f | 908 | MCBSP_WRITE(mcbsp, SPCR2, w | tx); |
5e1c5ff4 | 909 | |
d09a2afc | 910 | rx &= 1; |
96fbd745 | 911 | w = MCBSP_READ_CACHE(mcbsp, SPCR1); |
8ea3200f | 912 | MCBSP_WRITE(mcbsp, SPCR1, w | rx); |
5e1c5ff4 | 913 | |
44a6311c EV |
914 | /* |
915 | * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec | |
916 | * REVISIT: 100us may give enough time for two CLKSRG, however | |
917 | * due to some unknown PM related, clock gating etc. reason it | |
918 | * is now at 500us. | |
919 | */ | |
920 | udelay(500); | |
5e1c5ff4 | 921 | |
ce3f054b | 922 | if (enable_srg) { |
c12abc01 | 923 | /* Start frame sync */ |
96fbd745 | 924 | w = MCBSP_READ_CACHE(mcbsp, SPCR2); |
8ea3200f | 925 | MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); |
c12abc01 | 926 | } |
5e1c5ff4 | 927 | |
752ec2f2 | 928 | if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { |
d09a2afc | 929 | /* Release the transmitter and receiver */ |
96fbd745 | 930 | w = MCBSP_READ_CACHE(mcbsp, XCCR); |
d09a2afc | 931 | w &= ~(tx ? XDISABLE : 0); |
8ea3200f | 932 | MCBSP_WRITE(mcbsp, XCCR, w); |
96fbd745 | 933 | w = MCBSP_READ_CACHE(mcbsp, RCCR); |
d09a2afc | 934 | w &= ~(rx ? RDISABLE : 0); |
8ea3200f | 935 | MCBSP_WRITE(mcbsp, RCCR, w); |
d09a2afc JN |
936 | } |
937 | ||
5e1c5ff4 TL |
938 | /* Dump McBSP Regs */ |
939 | omap_mcbsp_dump_reg(id); | |
5e1c5ff4 | 940 | } |
fb78d808 | 941 | EXPORT_SYMBOL(omap_mcbsp_start); |
5e1c5ff4 | 942 | |
c12abc01 | 943 | void omap_mcbsp_stop(unsigned int id, int tx, int rx) |
5e1c5ff4 | 944 | { |
b4b58f58 | 945 | struct omap_mcbsp *mcbsp; |
c12abc01 | 946 | int idle; |
5e1c5ff4 TL |
947 | u16 w; |
948 | ||
bc5d0c89 EV |
949 | if (!omap_mcbsp_check_valid_id(id)) { |
950 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
5e1c5ff4 | 951 | return; |
bc5d0c89 | 952 | } |
5e1c5ff4 | 953 | |
b4b58f58 | 954 | mcbsp = id_to_mcbsp_ptr(id); |
5e1c5ff4 | 955 | |
fb78d808 | 956 | /* Reset transmitter */ |
d09a2afc | 957 | tx &= 1; |
752ec2f2 | 958 | if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { |
96fbd745 | 959 | w = MCBSP_READ_CACHE(mcbsp, XCCR); |
d09a2afc | 960 | w |= (tx ? XDISABLE : 0); |
8ea3200f | 961 | MCBSP_WRITE(mcbsp, XCCR, w); |
d09a2afc | 962 | } |
96fbd745 | 963 | w = MCBSP_READ_CACHE(mcbsp, SPCR2); |
8ea3200f | 964 | MCBSP_WRITE(mcbsp, SPCR2, w & ~tx); |
5e1c5ff4 TL |
965 | |
966 | /* Reset receiver */ | |
d09a2afc | 967 | rx &= 1; |
752ec2f2 | 968 | if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) { |
96fbd745 | 969 | w = MCBSP_READ_CACHE(mcbsp, RCCR); |
a93d4ed2 | 970 | w |= (rx ? RDISABLE : 0); |
8ea3200f | 971 | MCBSP_WRITE(mcbsp, RCCR, w); |
d09a2afc | 972 | } |
96fbd745 | 973 | w = MCBSP_READ_CACHE(mcbsp, SPCR1); |
8ea3200f | 974 | MCBSP_WRITE(mcbsp, SPCR1, w & ~rx); |
5e1c5ff4 | 975 | |
96fbd745 JK |
976 | idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | |
977 | MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); | |
c12abc01 JN |
978 | |
979 | if (idle) { | |
980 | /* Reset the sample rate generator */ | |
96fbd745 | 981 | w = MCBSP_READ_CACHE(mcbsp, SPCR2); |
8ea3200f | 982 | MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6)); |
c12abc01 | 983 | } |
d912fa92 EN |
984 | |
985 | if (cpu_is_omap34xx()) | |
986 | omap_st_stop(mcbsp); | |
5e1c5ff4 | 987 | } |
fb78d808 | 988 | EXPORT_SYMBOL(omap_mcbsp_stop); |
5e1c5ff4 | 989 | |
bb13b5fd TL |
990 | /* polled mcbsp i/o operations */ |
991 | int omap_mcbsp_pollwrite(unsigned int id, u16 buf) | |
992 | { | |
b4b58f58 | 993 | struct omap_mcbsp *mcbsp; |
bc5d0c89 EV |
994 | |
995 | if (!omap_mcbsp_check_valid_id(id)) { | |
996 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
997 | return -ENODEV; | |
998 | } | |
999 | ||
b4b58f58 | 1000 | mcbsp = id_to_mcbsp_ptr(id); |
b4b58f58 | 1001 | |
8ea3200f | 1002 | MCBSP_WRITE(mcbsp, DXR1, buf); |
bb13b5fd | 1003 | /* if frame sync error - clear the error */ |
8ea3200f | 1004 | if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) { |
bb13b5fd | 1005 | /* clear error */ |
0841cb82 | 1006 | MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2)); |
bb13b5fd TL |
1007 | /* resend */ |
1008 | return -1; | |
1009 | } else { | |
1010 | /* wait for transmit confirmation */ | |
1011 | int attemps = 0; | |
8ea3200f | 1012 | while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) { |
bb13b5fd | 1013 | if (attemps++ > 1000) { |
8ea3200f | 1014 | MCBSP_WRITE(mcbsp, SPCR2, |
96fbd745 JK |
1015 | MCBSP_READ_CACHE(mcbsp, SPCR2) & |
1016 | (~XRST)); | |
bb13b5fd | 1017 | udelay(10); |
8ea3200f | 1018 | MCBSP_WRITE(mcbsp, SPCR2, |
96fbd745 JK |
1019 | MCBSP_READ_CACHE(mcbsp, SPCR2) | |
1020 | (XRST)); | |
bb13b5fd | 1021 | udelay(10); |
b4b58f58 CS |
1022 | dev_err(mcbsp->dev, "Could not write to" |
1023 | " McBSP%d Register\n", mcbsp->id); | |
bb13b5fd TL |
1024 | return -2; |
1025 | } | |
1026 | } | |
1027 | } | |
fb78d808 | 1028 | |
bb13b5fd TL |
1029 | return 0; |
1030 | } | |
fb78d808 | 1031 | EXPORT_SYMBOL(omap_mcbsp_pollwrite); |
bb13b5fd | 1032 | |
fb78d808 | 1033 | int omap_mcbsp_pollread(unsigned int id, u16 *buf) |
bb13b5fd | 1034 | { |
b4b58f58 | 1035 | struct omap_mcbsp *mcbsp; |
bc5d0c89 EV |
1036 | |
1037 | if (!omap_mcbsp_check_valid_id(id)) { | |
1038 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
1039 | return -ENODEV; | |
1040 | } | |
b4b58f58 | 1041 | mcbsp = id_to_mcbsp_ptr(id); |
bc5d0c89 | 1042 | |
bb13b5fd | 1043 | /* if frame sync error - clear the error */ |
8ea3200f | 1044 | if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) { |
bb13b5fd | 1045 | /* clear error */ |
0841cb82 | 1046 | MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1)); |
bb13b5fd TL |
1047 | /* resend */ |
1048 | return -1; | |
1049 | } else { | |
1050 | /* wait for recieve confirmation */ | |
1051 | int attemps = 0; | |
8ea3200f | 1052 | while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) { |
bb13b5fd | 1053 | if (attemps++ > 1000) { |
8ea3200f | 1054 | MCBSP_WRITE(mcbsp, SPCR1, |
96fbd745 JK |
1055 | MCBSP_READ_CACHE(mcbsp, SPCR1) & |
1056 | (~RRST)); | |
bb13b5fd | 1057 | udelay(10); |
8ea3200f | 1058 | MCBSP_WRITE(mcbsp, SPCR1, |
96fbd745 JK |
1059 | MCBSP_READ_CACHE(mcbsp, SPCR1) | |
1060 | (RRST)); | |
bb13b5fd | 1061 | udelay(10); |
b4b58f58 CS |
1062 | dev_err(mcbsp->dev, "Could not read from" |
1063 | " McBSP%d Register\n", mcbsp->id); | |
bb13b5fd TL |
1064 | return -2; |
1065 | } | |
1066 | } | |
1067 | } | |
8ea3200f | 1068 | *buf = MCBSP_READ(mcbsp, DRR1); |
fb78d808 | 1069 | |
bb13b5fd TL |
1070 | return 0; |
1071 | } | |
fb78d808 | 1072 | EXPORT_SYMBOL(omap_mcbsp_pollread); |
bb13b5fd | 1073 | |
5e1c5ff4 TL |
1074 | /* |
1075 | * IRQ based word transmission. | |
1076 | */ | |
1077 | void omap_mcbsp_xmit_word(unsigned int id, u32 word) | |
1078 | { | |
b4b58f58 | 1079 | struct omap_mcbsp *mcbsp; |
bc5d0c89 | 1080 | omap_mcbsp_word_length word_length; |
5e1c5ff4 | 1081 | |
bc5d0c89 EV |
1082 | if (!omap_mcbsp_check_valid_id(id)) { |
1083 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
5e1c5ff4 | 1084 | return; |
bc5d0c89 | 1085 | } |
5e1c5ff4 | 1086 | |
b4b58f58 | 1087 | mcbsp = id_to_mcbsp_ptr(id); |
b4b58f58 | 1088 | word_length = mcbsp->tx_word_length; |
5e1c5ff4 | 1089 | |
b4b58f58 | 1090 | wait_for_completion(&mcbsp->tx_irq_completion); |
5e1c5ff4 TL |
1091 | |
1092 | if (word_length > OMAP_MCBSP_WORD_16) | |
8ea3200f JK |
1093 | MCBSP_WRITE(mcbsp, DXR2, word >> 16); |
1094 | MCBSP_WRITE(mcbsp, DXR1, word & 0xffff); | |
5e1c5ff4 | 1095 | } |
fb78d808 | 1096 | EXPORT_SYMBOL(omap_mcbsp_xmit_word); |
5e1c5ff4 TL |
1097 | |
1098 | u32 omap_mcbsp_recv_word(unsigned int id) | |
1099 | { | |
b4b58f58 | 1100 | struct omap_mcbsp *mcbsp; |
5e1c5ff4 | 1101 | u16 word_lsb, word_msb = 0; |
bc5d0c89 | 1102 | omap_mcbsp_word_length word_length; |
5e1c5ff4 | 1103 | |
bc5d0c89 EV |
1104 | if (!omap_mcbsp_check_valid_id(id)) { |
1105 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
1106 | return -ENODEV; | |
1107 | } | |
b4b58f58 | 1108 | mcbsp = id_to_mcbsp_ptr(id); |
5e1c5ff4 | 1109 | |
b4b58f58 | 1110 | word_length = mcbsp->rx_word_length; |
5e1c5ff4 | 1111 | |
b4b58f58 | 1112 | wait_for_completion(&mcbsp->rx_irq_completion); |
5e1c5ff4 TL |
1113 | |
1114 | if (word_length > OMAP_MCBSP_WORD_16) | |
8ea3200f JK |
1115 | word_msb = MCBSP_READ(mcbsp, DRR2); |
1116 | word_lsb = MCBSP_READ(mcbsp, DRR1); | |
5e1c5ff4 TL |
1117 | |
1118 | return (word_lsb | (word_msb << 16)); | |
1119 | } | |
fb78d808 | 1120 | EXPORT_SYMBOL(omap_mcbsp_recv_word); |
5e1c5ff4 | 1121 | |
120db2cb TL |
1122 | int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word) |
1123 | { | |
b4b58f58 | 1124 | struct omap_mcbsp *mcbsp; |
bc5d0c89 EV |
1125 | omap_mcbsp_word_length tx_word_length; |
1126 | omap_mcbsp_word_length rx_word_length; | |
120db2cb TL |
1127 | u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0; |
1128 | ||
bc5d0c89 EV |
1129 | if (!omap_mcbsp_check_valid_id(id)) { |
1130 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
1131 | return -ENODEV; | |
1132 | } | |
b4b58f58 | 1133 | mcbsp = id_to_mcbsp_ptr(id); |
b4b58f58 CS |
1134 | tx_word_length = mcbsp->tx_word_length; |
1135 | rx_word_length = mcbsp->rx_word_length; | |
bc5d0c89 | 1136 | |
120db2cb TL |
1137 | if (tx_word_length != rx_word_length) |
1138 | return -EINVAL; | |
1139 | ||
1140 | /* First we wait for the transmitter to be ready */ | |
8ea3200f | 1141 | spcr2 = MCBSP_READ(mcbsp, SPCR2); |
120db2cb | 1142 | while (!(spcr2 & XRDY)) { |
8ea3200f | 1143 | spcr2 = MCBSP_READ(mcbsp, SPCR2); |
120db2cb TL |
1144 | if (attempts++ > 1000) { |
1145 | /* We must reset the transmitter */ | |
96fbd745 JK |
1146 | MCBSP_WRITE(mcbsp, SPCR2, |
1147 | MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST)); | |
120db2cb | 1148 | udelay(10); |
96fbd745 JK |
1149 | MCBSP_WRITE(mcbsp, SPCR2, |
1150 | MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST); | |
120db2cb | 1151 | udelay(10); |
b4b58f58 CS |
1152 | dev_err(mcbsp->dev, "McBSP%d transmitter not " |
1153 | "ready\n", mcbsp->id); | |
120db2cb TL |
1154 | return -EAGAIN; |
1155 | } | |
1156 | } | |
1157 | ||
1158 | /* Now we can push the data */ | |
1159 | if (tx_word_length > OMAP_MCBSP_WORD_16) | |
8ea3200f JK |
1160 | MCBSP_WRITE(mcbsp, DXR2, word >> 16); |
1161 | MCBSP_WRITE(mcbsp, DXR1, word & 0xffff); | |
120db2cb TL |
1162 | |
1163 | /* We wait for the receiver to be ready */ | |
8ea3200f | 1164 | spcr1 = MCBSP_READ(mcbsp, SPCR1); |
120db2cb | 1165 | while (!(spcr1 & RRDY)) { |
8ea3200f | 1166 | spcr1 = MCBSP_READ(mcbsp, SPCR1); |
120db2cb TL |
1167 | if (attempts++ > 1000) { |
1168 | /* We must reset the receiver */ | |
96fbd745 JK |
1169 | MCBSP_WRITE(mcbsp, SPCR1, |
1170 | MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST)); | |
120db2cb | 1171 | udelay(10); |
96fbd745 JK |
1172 | MCBSP_WRITE(mcbsp, SPCR1, |
1173 | MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST); | |
120db2cb | 1174 | udelay(10); |
b4b58f58 CS |
1175 | dev_err(mcbsp->dev, "McBSP%d receiver not " |
1176 | "ready\n", mcbsp->id); | |
120db2cb TL |
1177 | return -EAGAIN; |
1178 | } | |
1179 | } | |
1180 | ||
1181 | /* Receiver is ready, let's read the dummy data */ | |
1182 | if (rx_word_length > OMAP_MCBSP_WORD_16) | |
8ea3200f JK |
1183 | word_msb = MCBSP_READ(mcbsp, DRR2); |
1184 | word_lsb = MCBSP_READ(mcbsp, DRR1); | |
120db2cb TL |
1185 | |
1186 | return 0; | |
1187 | } | |
fb78d808 | 1188 | EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll); |
120db2cb | 1189 | |
fb78d808 | 1190 | int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word) |
120db2cb | 1191 | { |
b4b58f58 | 1192 | struct omap_mcbsp *mcbsp; |
d592dd1a | 1193 | u32 clock_word = 0; |
bc5d0c89 EV |
1194 | omap_mcbsp_word_length tx_word_length; |
1195 | omap_mcbsp_word_length rx_word_length; | |
120db2cb TL |
1196 | u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0; |
1197 | ||
bc5d0c89 EV |
1198 | if (!omap_mcbsp_check_valid_id(id)) { |
1199 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
1200 | return -ENODEV; | |
1201 | } | |
1202 | ||
b4b58f58 | 1203 | mcbsp = id_to_mcbsp_ptr(id); |
b4b58f58 CS |
1204 | |
1205 | tx_word_length = mcbsp->tx_word_length; | |
1206 | rx_word_length = mcbsp->rx_word_length; | |
bc5d0c89 | 1207 | |
120db2cb TL |
1208 | if (tx_word_length != rx_word_length) |
1209 | return -EINVAL; | |
1210 | ||
1211 | /* First we wait for the transmitter to be ready */ | |
8ea3200f | 1212 | spcr2 = MCBSP_READ(mcbsp, SPCR2); |
120db2cb | 1213 | while (!(spcr2 & XRDY)) { |
8ea3200f | 1214 | spcr2 = MCBSP_READ(mcbsp, SPCR2); |
120db2cb TL |
1215 | if (attempts++ > 1000) { |
1216 | /* We must reset the transmitter */ | |
96fbd745 JK |
1217 | MCBSP_WRITE(mcbsp, SPCR2, |
1218 | MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST)); | |
120db2cb | 1219 | udelay(10); |
96fbd745 JK |
1220 | MCBSP_WRITE(mcbsp, SPCR2, |
1221 | MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST); | |
120db2cb | 1222 | udelay(10); |
b4b58f58 CS |
1223 | dev_err(mcbsp->dev, "McBSP%d transmitter not " |
1224 | "ready\n", mcbsp->id); | |
120db2cb TL |
1225 | return -EAGAIN; |
1226 | } | |
1227 | } | |
1228 | ||
1229 | /* We first need to enable the bus clock */ | |
1230 | if (tx_word_length > OMAP_MCBSP_WORD_16) | |
8ea3200f JK |
1231 | MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16); |
1232 | MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff); | |
120db2cb TL |
1233 | |
1234 | /* We wait for the receiver to be ready */ | |
8ea3200f | 1235 | spcr1 = MCBSP_READ(mcbsp, SPCR1); |
120db2cb | 1236 | while (!(spcr1 & RRDY)) { |
8ea3200f | 1237 | spcr1 = MCBSP_READ(mcbsp, SPCR1); |
120db2cb TL |
1238 | if (attempts++ > 1000) { |
1239 | /* We must reset the receiver */ | |
96fbd745 JK |
1240 | MCBSP_WRITE(mcbsp, SPCR1, |
1241 | MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST)); | |
120db2cb | 1242 | udelay(10); |
96fbd745 JK |
1243 | MCBSP_WRITE(mcbsp, SPCR1, |
1244 | MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST); | |
120db2cb | 1245 | udelay(10); |
b4b58f58 CS |
1246 | dev_err(mcbsp->dev, "McBSP%d receiver not " |
1247 | "ready\n", mcbsp->id); | |
120db2cb TL |
1248 | return -EAGAIN; |
1249 | } | |
1250 | } | |
1251 | ||
1252 | /* Receiver is ready, there is something for us */ | |
1253 | if (rx_word_length > OMAP_MCBSP_WORD_16) | |
8ea3200f JK |
1254 | word_msb = MCBSP_READ(mcbsp, DRR2); |
1255 | word_lsb = MCBSP_READ(mcbsp, DRR1); | |
120db2cb TL |
1256 | |
1257 | word[0] = (word_lsb | (word_msb << 16)); | |
1258 | ||
1259 | return 0; | |
1260 | } | |
fb78d808 | 1261 | EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll); |
120db2cb | 1262 | |
5e1c5ff4 TL |
1263 | /* |
1264 | * Simple DMA based buffer rx/tx routines. | |
1265 | * Nothing fancy, just a single buffer tx/rx through DMA. | |
1266 | * The DMA resources are released once the transfer is done. | |
1267 | * For anything fancier, you should use your own customized DMA | |
1268 | * routines and callbacks. | |
1269 | */ | |
fb78d808 EV |
1270 | int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, |
1271 | unsigned int length) | |
5e1c5ff4 | 1272 | { |
b4b58f58 | 1273 | struct omap_mcbsp *mcbsp; |
5e1c5ff4 | 1274 | int dma_tx_ch; |
120db2cb TL |
1275 | int src_port = 0; |
1276 | int dest_port = 0; | |
1277 | int sync_dev = 0; | |
5e1c5ff4 | 1278 | |
bc5d0c89 EV |
1279 | if (!omap_mcbsp_check_valid_id(id)) { |
1280 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
1281 | return -ENODEV; | |
1282 | } | |
b4b58f58 | 1283 | mcbsp = id_to_mcbsp_ptr(id); |
5e1c5ff4 | 1284 | |
b4b58f58 | 1285 | if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX", |
fb78d808 | 1286 | omap_mcbsp_tx_dma_callback, |
b4b58f58 | 1287 | mcbsp, |
fb78d808 | 1288 | &dma_tx_ch)) { |
b4b58f58 | 1289 | dev_err(mcbsp->dev, " Unable to request DMA channel for " |
bc5d0c89 | 1290 | "McBSP%d TX. Trying IRQ based TX\n", |
b4b58f58 | 1291 | mcbsp->id); |
5e1c5ff4 TL |
1292 | return -EAGAIN; |
1293 | } | |
b4b58f58 | 1294 | mcbsp->dma_tx_lch = dma_tx_ch; |
5e1c5ff4 | 1295 | |
b4b58f58 | 1296 | dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id, |
bc5d0c89 | 1297 | dma_tx_ch); |
5e1c5ff4 | 1298 | |
b4b58f58 | 1299 | init_completion(&mcbsp->tx_dma_completion); |
5e1c5ff4 | 1300 | |
120db2cb TL |
1301 | if (cpu_class_is_omap1()) { |
1302 | src_port = OMAP_DMA_PORT_TIPB; | |
1303 | dest_port = OMAP_DMA_PORT_EMIFF; | |
1304 | } | |
bc5d0c89 | 1305 | if (cpu_class_is_omap2()) |
b4b58f58 | 1306 | sync_dev = mcbsp->dma_tx_sync; |
120db2cb | 1307 | |
b4b58f58 | 1308 | omap_set_dma_transfer_params(mcbsp->dma_tx_lch, |
5e1c5ff4 TL |
1309 | OMAP_DMA_DATA_TYPE_S16, |
1310 | length >> 1, 1, | |
1a8bfa1e | 1311 | OMAP_DMA_SYNC_ELEMENT, |
120db2cb | 1312 | sync_dev, 0); |
5e1c5ff4 | 1313 | |
b4b58f58 | 1314 | omap_set_dma_dest_params(mcbsp->dma_tx_lch, |
120db2cb | 1315 | src_port, |
5e1c5ff4 | 1316 | OMAP_DMA_AMODE_CONSTANT, |
b4b58f58 | 1317 | mcbsp->phys_base + OMAP_MCBSP_REG_DXR1, |
1a8bfa1e | 1318 | 0, 0); |
5e1c5ff4 | 1319 | |
b4b58f58 | 1320 | omap_set_dma_src_params(mcbsp->dma_tx_lch, |
120db2cb | 1321 | dest_port, |
5e1c5ff4 | 1322 | OMAP_DMA_AMODE_POST_INC, |
1a8bfa1e TL |
1323 | buffer, |
1324 | 0, 0); | |
5e1c5ff4 | 1325 | |
b4b58f58 CS |
1326 | omap_start_dma(mcbsp->dma_tx_lch); |
1327 | wait_for_completion(&mcbsp->tx_dma_completion); | |
fb78d808 | 1328 | |
5e1c5ff4 TL |
1329 | return 0; |
1330 | } | |
fb78d808 | 1331 | EXPORT_SYMBOL(omap_mcbsp_xmit_buffer); |
5e1c5ff4 | 1332 | |
fb78d808 EV |
1333 | int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, |
1334 | unsigned int length) | |
5e1c5ff4 | 1335 | { |
b4b58f58 | 1336 | struct omap_mcbsp *mcbsp; |
5e1c5ff4 | 1337 | int dma_rx_ch; |
120db2cb TL |
1338 | int src_port = 0; |
1339 | int dest_port = 0; | |
1340 | int sync_dev = 0; | |
5e1c5ff4 | 1341 | |
bc5d0c89 EV |
1342 | if (!omap_mcbsp_check_valid_id(id)) { |
1343 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
1344 | return -ENODEV; | |
1345 | } | |
b4b58f58 | 1346 | mcbsp = id_to_mcbsp_ptr(id); |
5e1c5ff4 | 1347 | |
b4b58f58 | 1348 | if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX", |
fb78d808 | 1349 | omap_mcbsp_rx_dma_callback, |
b4b58f58 | 1350 | mcbsp, |
fb78d808 | 1351 | &dma_rx_ch)) { |
b4b58f58 | 1352 | dev_err(mcbsp->dev, "Unable to request DMA channel for " |
bc5d0c89 | 1353 | "McBSP%d RX. Trying IRQ based RX\n", |
b4b58f58 | 1354 | mcbsp->id); |
5e1c5ff4 TL |
1355 | return -EAGAIN; |
1356 | } | |
b4b58f58 | 1357 | mcbsp->dma_rx_lch = dma_rx_ch; |
5e1c5ff4 | 1358 | |
b4b58f58 | 1359 | dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id, |
bc5d0c89 | 1360 | dma_rx_ch); |
5e1c5ff4 | 1361 | |
b4b58f58 | 1362 | init_completion(&mcbsp->rx_dma_completion); |
5e1c5ff4 | 1363 | |
120db2cb TL |
1364 | if (cpu_class_is_omap1()) { |
1365 | src_port = OMAP_DMA_PORT_TIPB; | |
1366 | dest_port = OMAP_DMA_PORT_EMIFF; | |
1367 | } | |
bc5d0c89 | 1368 | if (cpu_class_is_omap2()) |
b4b58f58 | 1369 | sync_dev = mcbsp->dma_rx_sync; |
120db2cb | 1370 | |
b4b58f58 | 1371 | omap_set_dma_transfer_params(mcbsp->dma_rx_lch, |
fb78d808 EV |
1372 | OMAP_DMA_DATA_TYPE_S16, |
1373 | length >> 1, 1, | |
1374 | OMAP_DMA_SYNC_ELEMENT, | |
1375 | sync_dev, 0); | |
5e1c5ff4 | 1376 | |
b4b58f58 | 1377 | omap_set_dma_src_params(mcbsp->dma_rx_lch, |
120db2cb | 1378 | src_port, |
5e1c5ff4 | 1379 | OMAP_DMA_AMODE_CONSTANT, |
b4b58f58 | 1380 | mcbsp->phys_base + OMAP_MCBSP_REG_DRR1, |
1a8bfa1e | 1381 | 0, 0); |
5e1c5ff4 | 1382 | |
b4b58f58 | 1383 | omap_set_dma_dest_params(mcbsp->dma_rx_lch, |
fb78d808 EV |
1384 | dest_port, |
1385 | OMAP_DMA_AMODE_POST_INC, | |
1386 | buffer, | |
1387 | 0, 0); | |
5e1c5ff4 | 1388 | |
b4b58f58 CS |
1389 | omap_start_dma(mcbsp->dma_rx_lch); |
1390 | wait_for_completion(&mcbsp->rx_dma_completion); | |
fb78d808 | 1391 | |
5e1c5ff4 TL |
1392 | return 0; |
1393 | } | |
fb78d808 | 1394 | EXPORT_SYMBOL(omap_mcbsp_recv_buffer); |
5e1c5ff4 TL |
1395 | |
1396 | /* | |
1397 | * SPI wrapper. | |
1398 | * Since SPI setup is much simpler than the generic McBSP one, | |
1399 | * this wrapper just need an omap_mcbsp_spi_cfg structure as an input. | |
1400 | * Once this is done, you can call omap_mcbsp_start(). | |
1401 | */ | |
fb78d808 EV |
1402 | void omap_mcbsp_set_spi_mode(unsigned int id, |
1403 | const struct omap_mcbsp_spi_cfg *spi_cfg) | |
5e1c5ff4 | 1404 | { |
b4b58f58 | 1405 | struct omap_mcbsp *mcbsp; |
5e1c5ff4 TL |
1406 | struct omap_mcbsp_reg_cfg mcbsp_cfg; |
1407 | ||
bc5d0c89 EV |
1408 | if (!omap_mcbsp_check_valid_id(id)) { |
1409 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | |
5e1c5ff4 | 1410 | return; |
bc5d0c89 | 1411 | } |
b4b58f58 | 1412 | mcbsp = id_to_mcbsp_ptr(id); |
5e1c5ff4 TL |
1413 | |
1414 | memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg)); | |
1415 | ||
1416 | /* SPI has only one frame */ | |
1417 | mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0)); | |
1418 | mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0)); | |
1419 | ||
fb78d808 | 1420 | /* Clock stop mode */ |
5e1c5ff4 TL |
1421 | if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY) |
1422 | mcbsp_cfg.spcr1 |= (1 << 12); | |
1423 | else | |
1424 | mcbsp_cfg.spcr1 |= (3 << 11); | |
1425 | ||
1426 | /* Set clock parities */ | |
1427 | if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING) | |
1428 | mcbsp_cfg.pcr0 |= CLKRP; | |
1429 | else | |
1430 | mcbsp_cfg.pcr0 &= ~CLKRP; | |
1431 | ||
1432 | if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING) | |
1433 | mcbsp_cfg.pcr0 &= ~CLKXP; | |
1434 | else | |
1435 | mcbsp_cfg.pcr0 |= CLKXP; | |
1436 | ||
1437 | /* Set SCLKME to 0 and CLKSM to 1 */ | |
1438 | mcbsp_cfg.pcr0 &= ~SCLKME; | |
1439 | mcbsp_cfg.srgr2 |= CLKSM; | |
1440 | ||
1441 | /* Set FSXP */ | |
1442 | if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH) | |
1443 | mcbsp_cfg.pcr0 &= ~FSXP; | |
1444 | else | |
1445 | mcbsp_cfg.pcr0 |= FSXP; | |
1446 | ||
1447 | if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) { | |
1448 | mcbsp_cfg.pcr0 |= CLKXM; | |
fb78d808 | 1449 | mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1); |
5e1c5ff4 TL |
1450 | mcbsp_cfg.pcr0 |= FSXM; |
1451 | mcbsp_cfg.srgr2 &= ~FSGM; | |
1452 | mcbsp_cfg.xcr2 |= XDATDLY(1); | |
1453 | mcbsp_cfg.rcr2 |= RDATDLY(1); | |
fb78d808 | 1454 | } else { |
5e1c5ff4 TL |
1455 | mcbsp_cfg.pcr0 &= ~CLKXM; |
1456 | mcbsp_cfg.srgr1 |= CLKGDV(1); | |
1457 | mcbsp_cfg.pcr0 &= ~FSXM; | |
1458 | mcbsp_cfg.xcr2 &= ~XDATDLY(3); | |
1459 | mcbsp_cfg.rcr2 &= ~RDATDLY(3); | |
1460 | } | |
1461 | ||
1462 | mcbsp_cfg.xcr2 &= ~XPHASE; | |
1463 | mcbsp_cfg.rcr2 &= ~RPHASE; | |
1464 | ||
1465 | omap_mcbsp_config(id, &mcbsp_cfg); | |
1466 | } | |
fb78d808 | 1467 | EXPORT_SYMBOL(omap_mcbsp_set_spi_mode); |
5e1c5ff4 | 1468 | |
a8eb7ca0 | 1469 | #ifdef CONFIG_ARCH_OMAP3 |
a1a56f5f EV |
1470 | #define max_thres(m) (mcbsp->pdata->buffer_size) |
1471 | #define valid_threshold(m, val) ((val) <= max_thres(m)) | |
1472 | #define THRESHOLD_PROP_BUILDER(prop) \ | |
1473 | static ssize_t prop##_show(struct device *dev, \ | |
1474 | struct device_attribute *attr, char *buf) \ | |
1475 | { \ | |
1476 | struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \ | |
1477 | \ | |
1478 | return sprintf(buf, "%u\n", mcbsp->prop); \ | |
1479 | } \ | |
1480 | \ | |
1481 | static ssize_t prop##_store(struct device *dev, \ | |
1482 | struct device_attribute *attr, \ | |
1483 | const char *buf, size_t size) \ | |
1484 | { \ | |
1485 | struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \ | |
1486 | unsigned long val; \ | |
1487 | int status; \ | |
1488 | \ | |
1489 | status = strict_strtoul(buf, 0, &val); \ | |
1490 | if (status) \ | |
1491 | return status; \ | |
1492 | \ | |
1493 | if (!valid_threshold(mcbsp, val)) \ | |
1494 | return -EDOM; \ | |
1495 | \ | |
1496 | mcbsp->prop = val; \ | |
1497 | return size; \ | |
1498 | } \ | |
1499 | \ | |
1500 | static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store); | |
1501 | ||
1502 | THRESHOLD_PROP_BUILDER(max_tx_thres); | |
1503 | THRESHOLD_PROP_BUILDER(max_rx_thres); | |
1504 | ||
9b300509 JN |
1505 | static const char *dma_op_modes[] = { |
1506 | "element", "threshold", "frame", | |
1507 | }; | |
1508 | ||
98cb20e8 PU |
1509 | static ssize_t dma_op_mode_show(struct device *dev, |
1510 | struct device_attribute *attr, char *buf) | |
1511 | { | |
1512 | struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); | |
9b300509 JN |
1513 | int dma_op_mode, i = 0; |
1514 | ssize_t len = 0; | |
1515 | const char * const *s; | |
98cb20e8 | 1516 | |
98cb20e8 | 1517 | dma_op_mode = mcbsp->dma_op_mode; |
98cb20e8 | 1518 | |
9b300509 JN |
1519 | for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) { |
1520 | if (dma_op_mode == i) | |
1521 | len += sprintf(buf + len, "[%s] ", *s); | |
1522 | else | |
1523 | len += sprintf(buf + len, "%s ", *s); | |
1524 | } | |
1525 | len += sprintf(buf + len, "\n"); | |
1526 | ||
1527 | return len; | |
98cb20e8 PU |
1528 | } |
1529 | ||
1530 | static ssize_t dma_op_mode_store(struct device *dev, | |
1531 | struct device_attribute *attr, | |
1532 | const char *buf, size_t size) | |
1533 | { | |
1534 | struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); | |
9b300509 JN |
1535 | const char * const *s; |
1536 | int i = 0; | |
98cb20e8 | 1537 | |
9b300509 JN |
1538 | for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) |
1539 | if (sysfs_streq(buf, *s)) | |
1540 | break; | |
98cb20e8 | 1541 | |
9b300509 JN |
1542 | if (i == ARRAY_SIZE(dma_op_modes)) |
1543 | return -EINVAL; | |
98cb20e8 | 1544 | |
9b300509 | 1545 | spin_lock_irq(&mcbsp->lock); |
98cb20e8 PU |
1546 | if (!mcbsp->free) { |
1547 | size = -EBUSY; | |
1548 | goto unlock; | |
1549 | } | |
9b300509 | 1550 | mcbsp->dma_op_mode = i; |
98cb20e8 PU |
1551 | |
1552 | unlock: | |
1553 | spin_unlock_irq(&mcbsp->lock); | |
1554 | ||
1555 | return size; | |
1556 | } | |
1557 | ||
1558 | static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store); | |
1559 | ||
d912fa92 EN |
1560 | static ssize_t st_taps_show(struct device *dev, |
1561 | struct device_attribute *attr, char *buf) | |
1562 | { | |
1563 | struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); | |
1564 | struct omap_mcbsp_st_data *st_data = mcbsp->st_data; | |
1565 | ssize_t status = 0; | |
1566 | int i; | |
1567 | ||
1568 | spin_lock_irq(&mcbsp->lock); | |
1569 | for (i = 0; i < st_data->nr_taps; i++) | |
1570 | status += sprintf(&buf[status], (i ? ", %d" : "%d"), | |
1571 | st_data->taps[i]); | |
1572 | if (i) | |
1573 | status += sprintf(&buf[status], "\n"); | |
1574 | spin_unlock_irq(&mcbsp->lock); | |
1575 | ||
1576 | return status; | |
1577 | } | |
1578 | ||
1579 | static ssize_t st_taps_store(struct device *dev, | |
1580 | struct device_attribute *attr, | |
1581 | const char *buf, size_t size) | |
1582 | { | |
1583 | struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); | |
1584 | struct omap_mcbsp_st_data *st_data = mcbsp->st_data; | |
1585 | int val, tmp, status, i = 0; | |
1586 | ||
1587 | spin_lock_irq(&mcbsp->lock); | |
1588 | memset(st_data->taps, 0, sizeof(st_data->taps)); | |
1589 | st_data->nr_taps = 0; | |
1590 | ||
1591 | do { | |
1592 | status = sscanf(buf, "%d%n", &val, &tmp); | |
1593 | if (status < 0 || status == 0) { | |
1594 | size = -EINVAL; | |
1595 | goto out; | |
1596 | } | |
1597 | if (val < -32768 || val > 32767) { | |
1598 | size = -EINVAL; | |
1599 | goto out; | |
1600 | } | |
1601 | st_data->taps[i++] = val; | |
1602 | buf += tmp; | |
1603 | if (*buf != ',') | |
1604 | break; | |
1605 | buf++; | |
1606 | } while (1); | |
1607 | ||
1608 | st_data->nr_taps = i; | |
1609 | ||
1610 | out: | |
1611 | spin_unlock_irq(&mcbsp->lock); | |
1612 | ||
1613 | return size; | |
1614 | } | |
1615 | ||
1616 | static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store); | |
1617 | ||
4c8200ae | 1618 | static const struct attribute *additional_attrs[] = { |
a1a56f5f EV |
1619 | &dev_attr_max_tx_thres.attr, |
1620 | &dev_attr_max_rx_thres.attr, | |
98cb20e8 | 1621 | &dev_attr_dma_op_mode.attr, |
a1a56f5f EV |
1622 | NULL, |
1623 | }; | |
1624 | ||
4c8200ae EV |
1625 | static const struct attribute_group additional_attr_group = { |
1626 | .attrs = (struct attribute **)additional_attrs, | |
a1a56f5f EV |
1627 | }; |
1628 | ||
4c8200ae | 1629 | static inline int __devinit omap_additional_add(struct device *dev) |
a1a56f5f | 1630 | { |
4c8200ae | 1631 | return sysfs_create_group(&dev->kobj, &additional_attr_group); |
a1a56f5f EV |
1632 | } |
1633 | ||
4c8200ae | 1634 | static inline void __devexit omap_additional_remove(struct device *dev) |
a1a56f5f | 1635 | { |
4c8200ae | 1636 | sysfs_remove_group(&dev->kobj, &additional_attr_group); |
a1a56f5f EV |
1637 | } |
1638 | ||
d912fa92 EN |
1639 | static const struct attribute *sidetone_attrs[] = { |
1640 | &dev_attr_st_taps.attr, | |
1641 | NULL, | |
1642 | }; | |
1643 | ||
1644 | static const struct attribute_group sidetone_attr_group = { | |
1645 | .attrs = (struct attribute **)sidetone_attrs, | |
1646 | }; | |
1647 | ||
b0a330dc | 1648 | static int __devinit omap_st_add(struct omap_mcbsp *mcbsp) |
d912fa92 EN |
1649 | { |
1650 | struct omap_mcbsp_platform_data *pdata = mcbsp->pdata; | |
1651 | struct omap_mcbsp_st_data *st_data; | |
1652 | int err; | |
1653 | ||
1654 | st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL); | |
1655 | if (!st_data) { | |
1656 | err = -ENOMEM; | |
1657 | goto err1; | |
1658 | } | |
1659 | ||
1660 | st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K); | |
1661 | if (!st_data->io_base_st) { | |
1662 | err = -ENOMEM; | |
1663 | goto err2; | |
1664 | } | |
1665 | ||
1666 | err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group); | |
1667 | if (err) | |
1668 | goto err3; | |
1669 | ||
1670 | mcbsp->st_data = st_data; | |
1671 | return 0; | |
1672 | ||
1673 | err3: | |
1674 | iounmap(st_data->io_base_st); | |
1675 | err2: | |
1676 | kfree(st_data); | |
1677 | err1: | |
1678 | return err; | |
1679 | ||
1680 | } | |
1681 | ||
1682 | static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp) | |
1683 | { | |
1684 | struct omap_mcbsp_st_data *st_data = mcbsp->st_data; | |
1685 | ||
1686 | if (st_data) { | |
1687 | sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group); | |
1688 | iounmap(st_data->io_base_st); | |
1689 | kfree(st_data); | |
1690 | } | |
1691 | } | |
1692 | ||
a1a56f5f EV |
1693 | static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) |
1694 | { | |
98cb20e8 | 1695 | mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT; |
a1a56f5f | 1696 | if (cpu_is_omap34xx()) { |
451fd82d PU |
1697 | /* |
1698 | * Initially configure the maximum thresholds to a safe value. | |
1699 | * The McBSP FIFO usage with these values should not go under | |
1700 | * 16 locations. | |
1701 | * If the whole FIFO without safety buffer is used, than there | |
1702 | * is a possibility that the DMA will be not able to push the | |
1703 | * new data on time, causing channel shifts in runtime. | |
1704 | */ | |
1705 | mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10; | |
1706 | mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10; | |
98cb20e8 PU |
1707 | /* |
1708 | * REVISIT: Set dmap_op_mode to THRESHOLD as default | |
1709 | * for mcbsp2 instances. | |
1710 | */ | |
4c8200ae | 1711 | if (omap_additional_add(mcbsp->dev)) |
a1a56f5f | 1712 | dev_warn(mcbsp->dev, |
4c8200ae | 1713 | "Unable to create additional controls\n"); |
d912fa92 EN |
1714 | |
1715 | if (mcbsp->id == 2 || mcbsp->id == 3) | |
1716 | if (omap_st_add(mcbsp)) | |
1717 | dev_warn(mcbsp->dev, | |
1718 | "Unable to create sidetone controls\n"); | |
1719 | ||
a1a56f5f EV |
1720 | } else { |
1721 | mcbsp->max_tx_thres = -EINVAL; | |
1722 | mcbsp->max_rx_thres = -EINVAL; | |
1723 | } | |
1724 | } | |
1725 | ||
1726 | static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) | |
1727 | { | |
d912fa92 | 1728 | if (cpu_is_omap34xx()) { |
4c8200ae | 1729 | omap_additional_remove(mcbsp->dev); |
d912fa92 EN |
1730 | |
1731 | if (mcbsp->id == 2 || mcbsp->id == 3) | |
1732 | omap_st_remove(mcbsp); | |
1733 | } | |
a1a56f5f EV |
1734 | } |
1735 | #else | |
1736 | static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {} | |
1737 | static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {} | |
a8eb7ca0 | 1738 | #endif /* CONFIG_ARCH_OMAP3 */ |
a1a56f5f | 1739 | |
5e1c5ff4 TL |
1740 | /* |
1741 | * McBSP1 and McBSP3 are directly mapped on 1610 and 1510. | |
1742 | * 730 has only 2 McBSP, and both of them are MPU peripherals. | |
1743 | */ | |
25cef225 | 1744 | static int __devinit omap_mcbsp_probe(struct platform_device *pdev) |
bc5d0c89 EV |
1745 | { |
1746 | struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data; | |
b4b58f58 | 1747 | struct omap_mcbsp *mcbsp; |
bc5d0c89 EV |
1748 | int id = pdev->id - 1; |
1749 | int ret = 0; | |
5e1c5ff4 | 1750 | |
bc5d0c89 EV |
1751 | if (!pdata) { |
1752 | dev_err(&pdev->dev, "McBSP device initialized without" | |
1753 | "platform data\n"); | |
1754 | ret = -EINVAL; | |
1755 | goto exit; | |
1756 | } | |
1757 | ||
1758 | dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id); | |
1759 | ||
b4b58f58 | 1760 | if (id >= omap_mcbsp_count) { |
bc5d0c89 EV |
1761 | dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id); |
1762 | ret = -EINVAL; | |
1763 | goto exit; | |
1764 | } | |
1765 | ||
b4b58f58 CS |
1766 | mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL); |
1767 | if (!mcbsp) { | |
1768 | ret = -ENOMEM; | |
1769 | goto exit; | |
1770 | } | |
b4b58f58 CS |
1771 | |
1772 | spin_lock_init(&mcbsp->lock); | |
1773 | mcbsp->id = id + 1; | |
1774 | mcbsp->free = 1; | |
1775 | mcbsp->dma_tx_lch = -1; | |
1776 | mcbsp->dma_rx_lch = -1; | |
bc5d0c89 | 1777 | |
b4b58f58 CS |
1778 | mcbsp->phys_base = pdata->phys_base; |
1779 | mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K); | |
1780 | if (!mcbsp->io_base) { | |
d592dd1a RK |
1781 | ret = -ENOMEM; |
1782 | goto err_ioremap; | |
1783 | } | |
1784 | ||
bc5d0c89 | 1785 | /* Default I/O is IRQ based */ |
b4b58f58 CS |
1786 | mcbsp->io_type = OMAP_MCBSP_IRQ_IO; |
1787 | mcbsp->tx_irq = pdata->tx_irq; | |
1788 | mcbsp->rx_irq = pdata->rx_irq; | |
1789 | mcbsp->dma_rx_sync = pdata->dma_rx_sync; | |
1790 | mcbsp->dma_tx_sync = pdata->dma_tx_sync; | |
bc5d0c89 | 1791 | |
b820ce4e RK |
1792 | mcbsp->iclk = clk_get(&pdev->dev, "ick"); |
1793 | if (IS_ERR(mcbsp->iclk)) { | |
1794 | ret = PTR_ERR(mcbsp->iclk); | |
1795 | dev_err(&pdev->dev, "unable to get ick: %d\n", ret); | |
1796 | goto err_iclk; | |
1797 | } | |
06151158 | 1798 | |
b820ce4e RK |
1799 | mcbsp->fclk = clk_get(&pdev->dev, "fck"); |
1800 | if (IS_ERR(mcbsp->fclk)) { | |
1801 | ret = PTR_ERR(mcbsp->fclk); | |
1802 | dev_err(&pdev->dev, "unable to get fck: %d\n", ret); | |
1803 | goto err_fclk; | |
bc5d0c89 EV |
1804 | } |
1805 | ||
b4b58f58 CS |
1806 | mcbsp->pdata = pdata; |
1807 | mcbsp->dev = &pdev->dev; | |
b820ce4e | 1808 | mcbsp_ptr[id] = mcbsp; |
b4b58f58 | 1809 | platform_set_drvdata(pdev, mcbsp); |
a1a56f5f EV |
1810 | |
1811 | /* Initialize mcbsp properties for OMAP34XX if needed / applicable */ | |
1812 | omap34xx_device_init(mcbsp); | |
1813 | ||
d592dd1a | 1814 | return 0; |
bc5d0c89 | 1815 | |
b820ce4e RK |
1816 | err_fclk: |
1817 | clk_put(mcbsp->iclk); | |
1818 | err_iclk: | |
b4b58f58 | 1819 | iounmap(mcbsp->io_base); |
d592dd1a | 1820 | err_ioremap: |
b820ce4e | 1821 | kfree(mcbsp); |
bc5d0c89 EV |
1822 | exit: |
1823 | return ret; | |
1824 | } | |
120db2cb | 1825 | |
25cef225 | 1826 | static int __devexit omap_mcbsp_remove(struct platform_device *pdev) |
5e1c5ff4 | 1827 | { |
bc5d0c89 | 1828 | struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev); |
5e1c5ff4 | 1829 | |
bc5d0c89 EV |
1830 | platform_set_drvdata(pdev, NULL); |
1831 | if (mcbsp) { | |
5e1c5ff4 | 1832 | |
bc5d0c89 EV |
1833 | if (mcbsp->pdata && mcbsp->pdata->ops && |
1834 | mcbsp->pdata->ops->free) | |
1835 | mcbsp->pdata->ops->free(mcbsp->id); | |
5e1c5ff4 | 1836 | |
a1a56f5f EV |
1837 | omap34xx_device_exit(mcbsp); |
1838 | ||
b820ce4e RK |
1839 | clk_disable(mcbsp->fclk); |
1840 | clk_disable(mcbsp->iclk); | |
1841 | clk_put(mcbsp->fclk); | |
1842 | clk_put(mcbsp->iclk); | |
bc5d0c89 | 1843 | |
d592dd1a RK |
1844 | iounmap(mcbsp->io_base); |
1845 | ||
b820ce4e RK |
1846 | mcbsp->fclk = NULL; |
1847 | mcbsp->iclk = NULL; | |
bc5d0c89 EV |
1848 | mcbsp->free = 0; |
1849 | mcbsp->dev = NULL; | |
5e1c5ff4 TL |
1850 | } |
1851 | ||
1852 | return 0; | |
1853 | } | |
1854 | ||
bc5d0c89 EV |
1855 | static struct platform_driver omap_mcbsp_driver = { |
1856 | .probe = omap_mcbsp_probe, | |
25cef225 | 1857 | .remove = __devexit_p(omap_mcbsp_remove), |
bc5d0c89 EV |
1858 | .driver = { |
1859 | .name = "omap-mcbsp", | |
1860 | }, | |
1861 | }; | |
1862 | ||
1863 | int __init omap_mcbsp_init(void) | |
1864 | { | |
1865 | /* Register the McBSP driver */ | |
1866 | return platform_driver_register(&omap_mcbsp_driver); | |
1867 | } |