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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394...
[deliverable/linux.git] / arch / arm / plat-omap / mcbsp.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/mcbsp.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Multichannel mode not supported.
13 */
14
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/device.h>
bc5d0c89 18#include <linux/platform_device.h>
5e1c5ff4
TL		 19#include <linux/wait.h>
20#include <linux/completion.h>
21#include <linux/interrupt.h>
22#include <linux/err.h>
f8ce2547 23#include <linux/clk.h>
04fbf6a2 24#include <linux/delay.h>
fb78d808 25#include <linux/io.h>
5a0e3ad6 26#include <linux/slab.h>
5e1c5ff4 27
ce491cf8
TL		 28#include <plat/dma.h>
29#include <plat/mcbsp.h>
5e1c5ff4 30
d912fa92
EN		 31#include "../mach-omap2/cm-regbits-34xx.h"
32
b4b58f58 33struct omap_mcbsp **mcbsp_ptr;
c8c99699 34int omap_mcbsp_count, omap_mcbsp_cache_size;
bc5d0c89 35
8ea3200f 36void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
b4b58f58 37{
c8c99699
JK		 38 if (cpu_class_is_omap1()) {
39 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
8ea3200f 40 __raw_writew((u16)val, mcbsp->io_base + reg);
c8c99699
JK		 41 } else if (cpu_is_omap2420()) {
42 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
43 __raw_writew((u16)val, mcbsp->io_base + reg);
44 } else {
45 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
8ea3200f 46 __raw_writel(val, mcbsp->io_base + reg);
c8c99699 47 }
b4b58f58
CS		 48}
49
c8c99699 50int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
b4b58f58 51{
c8c99699
JK		 52 if (cpu_class_is_omap1()) {
53 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
54 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
55 } else if (cpu_is_omap2420()) {
56 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
57 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
58 } else {
59 return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
60 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
61 }
b4b58f58
CS		 62}
63
d912fa92
EN		 64#ifdef CONFIG_ARCH_OMAP3
65void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
66{
67 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
68}
69
70int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
71{
72 return __raw_readl(mcbsp->st_data->io_base_st + reg);
73}
74#endif
75
8ea3200f 76#define MCBSP_READ(mcbsp, reg) \
c8c99699 77 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
8ea3200f
JK		 78#define MCBSP_WRITE(mcbsp, reg, val) \
79 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
c8c99699
JK		 80#define MCBSP_READ_CACHE(mcbsp, reg) \
81 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
b4b58f58
CS		 82
83#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
84#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
5e1c5ff4 85
d912fa92
EN		 86#define MCBSP_ST_READ(mcbsp, reg) \
87 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
88#define MCBSP_ST_WRITE(mcbsp, reg, val) \
89 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
90
5e1c5ff4
TL		 91static void omap_mcbsp_dump_reg(u8 id)
92{
b4b58f58
CS		 93 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
94
95 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
96 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
8ea3200f 97 MCBSP_READ(mcbsp, DRR2));
b4b58f58 98 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
8ea3200f 99 MCBSP_READ(mcbsp, DRR1));
b4b58f58 100 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
8ea3200f 101 MCBSP_READ(mcbsp, DXR2));
b4b58f58 102 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
8ea3200f 103 MCBSP_READ(mcbsp, DXR1));
b4b58f58 104 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
8ea3200f 105 MCBSP_READ(mcbsp, SPCR2));
b4b58f58 106 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
8ea3200f 107 MCBSP_READ(mcbsp, SPCR1));
b4b58f58 108 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
8ea3200f 109 MCBSP_READ(mcbsp, RCR2));
b4b58f58 110 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
8ea3200f 111 MCBSP_READ(mcbsp, RCR1));
b4b58f58 112 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
8ea3200f 113 MCBSP_READ(mcbsp, XCR2));
b4b58f58 114 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
8ea3200f 115 MCBSP_READ(mcbsp, XCR1));
b4b58f58 116 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
8ea3200f 117 MCBSP_READ(mcbsp, SRGR2));
b4b58f58 118 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
8ea3200f 119 MCBSP_READ(mcbsp, SRGR1));
b4b58f58 120 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
8ea3200f 121 MCBSP_READ(mcbsp, PCR0));
b4b58f58 122 dev_dbg(mcbsp->dev, "***********************\n");
5e1c5ff4
TL		 123}
124
0cd61b68 125static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
5e1c5ff4 126{
e8f2af17 127 struct omap_mcbsp *mcbsp_tx = dev_id;
d6d834b0 128 u16 irqst_spcr2;
5e1c5ff4 129
8ea3200f 130 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
d6d834b0 131 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
5e1c5ff4 132
d6d834b0
EN		 133 if (irqst_spcr2 & XSYNC_ERR) {
134 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
135 irqst_spcr2);
136 /* Writing zero to XSYNC_ERR clears the IRQ */
0841cb82 137 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
d6d834b0
EN		 138 } else {
139 complete(&mcbsp_tx->tx_irq_completion);
140 }
fb78d808 141
5e1c5ff4
TL		 142 return IRQ_HANDLED;
143}
144
0cd61b68 145static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
5e1c5ff4 146{
e8f2af17 147 struct omap_mcbsp *mcbsp_rx = dev_id;
d6d834b0
EN		 148 u16 irqst_spcr1;
149
8ea3200f 150 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
d6d834b0
EN		 151 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
152
153 if (irqst_spcr1 & RSYNC_ERR) {
154 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
155 irqst_spcr1);
156 /* Writing zero to RSYNC_ERR clears the IRQ */
0841cb82 157 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
d6d834b0
EN		 158 } else {
159 complete(&mcbsp_rx->tx_irq_completion);
160 }
fb78d808 161
5e1c5ff4
TL		 162 return IRQ_HANDLED;
163}
164
5e1c5ff4
TL		 165static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
166{
e8f2af17 167 struct omap_mcbsp *mcbsp_dma_tx = data;
5e1c5ff4 168
bc5d0c89 169 dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
8ea3200f 170 MCBSP_READ(mcbsp_dma_tx, SPCR2));
5e1c5ff4
TL		 171
172 /* We can free the channels */
173 omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
174 mcbsp_dma_tx->dma_tx_lch = -1;
175
176 complete(&mcbsp_dma_tx->tx_dma_completion);
177}
178
179static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
180{
e8f2af17 181 struct omap_mcbsp *mcbsp_dma_rx = data;
5e1c5ff4 182
bc5d0c89 183 dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
8ea3200f 184 MCBSP_READ(mcbsp_dma_rx, SPCR2));
5e1c5ff4
TL		 185
186 /* We can free the channels */
187 omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
188 mcbsp_dma_rx->dma_rx_lch = -1;
189
190 complete(&mcbsp_dma_rx->rx_dma_completion);
191}
192
5e1c5ff4
TL		 193/*
194 * omap_mcbsp_config simply write a config to the
195 * appropriate McBSP.
196 * You either call this function or set the McBSP registers
197 * by yourself before calling omap_mcbsp_start().
198 */
fb78d808 199void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
5e1c5ff4 200{
b4b58f58 201 struct omap_mcbsp *mcbsp;
5e1c5ff4 202
bc5d0c89
EV		 203 if (!omap_mcbsp_check_valid_id(id)) {
204 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
205 return;
206 }
b4b58f58 207 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 208
b4b58f58
CS		 209 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
210 mcbsp->id, mcbsp->phys_base);
5e1c5ff4
TL		 211
212 /* We write the given config */
8ea3200f
JK		 213 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
214 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
215 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
216 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
217 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
218 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
219 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
220 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
221 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
222 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
223 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
a5b92cc3 224 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
8ea3200f
JK		 225 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
226 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
3127f8f8 227 }
5e1c5ff4 228}
fb78d808 229EXPORT_SYMBOL(omap_mcbsp_config);
5e1c5ff4 230
a8eb7ca0 231#ifdef CONFIG_ARCH_OMAP3
d912fa92
EN		 232static void omap_st_on(struct omap_mcbsp *mcbsp)
233{
234 unsigned int w;
235
236 /*
237 * Sidetone uses McBSP ICLK - which must not idle when sidetones
238 * are enabled or sidetones start sounding ugly.
239 */
240 w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
241 w &= ~(1 << (mcbsp->id - 2));
242 cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
243
244 /* Enable McBSP Sidetone */
245 w = MCBSP_READ(mcbsp, SSELCR);
246 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
247
248 w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
249 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
250
251 /* Enable Sidetone from Sidetone Core */
252 w = MCBSP_ST_READ(mcbsp, SSELCR);
253 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
254}
255
256static void omap_st_off(struct omap_mcbsp *mcbsp)
257{
258 unsigned int w;
259
260 w = MCBSP_ST_READ(mcbsp, SSELCR);
261 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
262
263 w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
264 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE);
265
266 w = MCBSP_READ(mcbsp, SSELCR);
267 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
268
269 w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
270 w |= 1 << (mcbsp->id - 2);
271 cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
272}
273
274static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
275{
276 u16 val, i;
277
278 val = MCBSP_ST_READ(mcbsp, SYSCONFIG);
279 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, val & ~(ST_AUTOIDLE));
280
281 val = MCBSP_ST_READ(mcbsp, SSELCR);
282
283 if (val & ST_COEFFWREN)
284 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
285
286 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
287
288 for (i = 0; i < 128; i++)
289 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
290
291 i = 0;
292
293 val = MCBSP_ST_READ(mcbsp, SSELCR);
294 while (!(val & ST_COEFFWRDONE) && (++i < 1000))
295 val = MCBSP_ST_READ(mcbsp, SSELCR);
296
297 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
298
299 if (i == 1000)
300 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
301}
302
303static void omap_st_chgain(struct omap_mcbsp *mcbsp)
304{
305 u16 w;
306 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
307
308 w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
309 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
310
311 w = MCBSP_ST_READ(mcbsp, SSELCR);
312
313 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
314 ST_CH1GAIN(st_data->ch1gain));
315}
316
317int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
318{
319 struct omap_mcbsp *mcbsp;
320 struct omap_mcbsp_st_data *st_data;
321 int ret = 0;
322
323 if (!omap_mcbsp_check_valid_id(id)) {
324 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
325 return -ENODEV;
326 }
327
328 mcbsp = id_to_mcbsp_ptr(id);
329 st_data = mcbsp->st_data;
330
331 if (!st_data)
332 return -ENOENT;
333
334 spin_lock_irq(&mcbsp->lock);
335 if (channel == 0)
336 st_data->ch0gain = chgain;
337 else if (channel == 1)
338 st_data->ch1gain = chgain;
339 else
340 ret = -EINVAL;
341
342 if (st_data->enabled)
343 omap_st_chgain(mcbsp);
344 spin_unlock_irq(&mcbsp->lock);
345
346 return ret;
347}
348EXPORT_SYMBOL(omap_st_set_chgain);
349
350int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
351{
352 struct omap_mcbsp *mcbsp;
353 struct omap_mcbsp_st_data *st_data;
354 int ret = 0;
355
356 if (!omap_mcbsp_check_valid_id(id)) {
357 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
358 return -ENODEV;
359 }
360
361 mcbsp = id_to_mcbsp_ptr(id);
362 st_data = mcbsp->st_data;
363
364 if (!st_data)
365 return -ENOENT;
366
367 spin_lock_irq(&mcbsp->lock);
368 if (channel == 0)
369 *chgain = st_data->ch0gain;
370 else if (channel == 1)
371 *chgain = st_data->ch1gain;
372 else
373 ret = -EINVAL;
374 spin_unlock_irq(&mcbsp->lock);
375
376 return ret;
377}
378EXPORT_SYMBOL(omap_st_get_chgain);
379
380static int omap_st_start(struct omap_mcbsp *mcbsp)
381{
382 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
383
384 if (st_data && st_data->enabled && !st_data->running) {
385 omap_st_fir_write(mcbsp, st_data->taps);
386 omap_st_chgain(mcbsp);
387
388 if (!mcbsp->free) {
389 omap_st_on(mcbsp);
390 st_data->running = 1;
391 }
392 }
393
394 return 0;
395}
396
397int omap_st_enable(unsigned int id)
398{
399 struct omap_mcbsp *mcbsp;
400 struct omap_mcbsp_st_data *st_data;
401
402 if (!omap_mcbsp_check_valid_id(id)) {
403 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
404 return -ENODEV;
405 }
406
407 mcbsp = id_to_mcbsp_ptr(id);
408 st_data = mcbsp->st_data;
409
410 if (!st_data)
411 return -ENODEV;
412
413 spin_lock_irq(&mcbsp->lock);
414 st_data->enabled = 1;
415 omap_st_start(mcbsp);
416 spin_unlock_irq(&mcbsp->lock);
417
418 return 0;
419}
420EXPORT_SYMBOL(omap_st_enable);
421
422static int omap_st_stop(struct omap_mcbsp *mcbsp)
423{
424 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
425
426 if (st_data && st_data->running) {
427 if (!mcbsp->free) {
428 omap_st_off(mcbsp);
429 st_data->running = 0;
430 }
431 }
432
433 return 0;
434}
435
436int omap_st_disable(unsigned int id)
437{
438 struct omap_mcbsp *mcbsp;
439 struct omap_mcbsp_st_data *st_data;
440 int ret = 0;
441
442 if (!omap_mcbsp_check_valid_id(id)) {
443 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
444 return -ENODEV;
445 }
446
447 mcbsp = id_to_mcbsp_ptr(id);
448 st_data = mcbsp->st_data;
449
450 if (!st_data)
451 return -ENODEV;
452
453 spin_lock_irq(&mcbsp->lock);
454 omap_st_stop(mcbsp);
455 st_data->enabled = 0;
456 spin_unlock_irq(&mcbsp->lock);
457
458 return ret;
459}
460EXPORT_SYMBOL(omap_st_disable);
461
462int omap_st_is_enabled(unsigned int id)
463{
464 struct omap_mcbsp *mcbsp;
465 struct omap_mcbsp_st_data *st_data;
466
467 if (!omap_mcbsp_check_valid_id(id)) {
468 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
469 return -ENODEV;
470 }
471
472 mcbsp = id_to_mcbsp_ptr(id);
473 st_data = mcbsp->st_data;
474
475 if (!st_data)
476 return -ENODEV;
477
478
479 return st_data->enabled;
480}
481EXPORT_SYMBOL(omap_st_is_enabled);
482
7aa9ff56
EV		 483/*
484 * omap_mcbsp_set_tx_threshold configures how to deal
485 * with transmit threshold. the threshold value and handler can be
486 * configure in here.
487 */
488void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
489{
490 struct omap_mcbsp *mcbsp;
7aa9ff56 491
752ec2f2 492 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
7aa9ff56
EV		 493 return;
494
495 if (!omap_mcbsp_check_valid_id(id)) {
496 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
497 return;
498 }
499 mcbsp = id_to_mcbsp_ptr(id);
7aa9ff56 500
8ea3200f 501 MCBSP_WRITE(mcbsp, THRSH2, threshold);
7aa9ff56
EV		 502}
503EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
504
505/*
506 * omap_mcbsp_set_rx_threshold configures how to deal
507 * with receive threshold. the threshold value and handler can be
508 * configure in here.
509 */
510void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
511{
512 struct omap_mcbsp *mcbsp;
7aa9ff56 513
752ec2f2 514 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
7aa9ff56
EV		 515 return;
516
517 if (!omap_mcbsp_check_valid_id(id)) {
518 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
519 return;
520 }
521 mcbsp = id_to_mcbsp_ptr(id);
7aa9ff56 522
8ea3200f 523 MCBSP_WRITE(mcbsp, THRSH1, threshold);
7aa9ff56
EV		 524}
525EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
a1a56f5f
EV		 526
527/*
528 * omap_mcbsp_get_max_tx_thres just return the current configured
529 * maximum threshold for transmission
530 */
531u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
532{
533 struct omap_mcbsp *mcbsp;
534
535 if (!omap_mcbsp_check_valid_id(id)) {
536 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
537 return -ENODEV;
538 }
539 mcbsp = id_to_mcbsp_ptr(id);
540
541 return mcbsp->max_tx_thres;
542}
543EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
544
545/*
546 * omap_mcbsp_get_max_rx_thres just return the current configured
547 * maximum threshold for reception
548 */
549u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
550{
551 struct omap_mcbsp *mcbsp;
552
553 if (!omap_mcbsp_check_valid_id(id)) {
554 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
555 return -ENODEV;
556 }
557 mcbsp = id_to_mcbsp_ptr(id);
558
559 return mcbsp->max_rx_thres;
560}
561EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
98cb20e8 562
7dc976ed
PU		 563#define MCBSP2_FIFO_SIZE 0x500 /* 1024 + 256 locations */
564#define MCBSP1345_FIFO_SIZE 0x80 /* 128 locations */
565/*
566 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
567 */
568u16 omap_mcbsp_get_tx_delay(unsigned int id)
569{
570 struct omap_mcbsp *mcbsp;
571 u16 buffstat;
572
573 if (!omap_mcbsp_check_valid_id(id)) {
574 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
575 return -ENODEV;
576 }
577 mcbsp = id_to_mcbsp_ptr(id);
578
579 /* Returns the number of free locations in the buffer */
580 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
581
582 /* Number of slots are different in McBSP ports */
583 if (mcbsp->id == 2)
584 return MCBSP2_FIFO_SIZE - buffstat;
585 else
586 return MCBSP1345_FIFO_SIZE - buffstat;
587}
588EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
589
590/*
591 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
592 * to reach the threshold value (when the DMA will be triggered to read it)
593 */
594u16 omap_mcbsp_get_rx_delay(unsigned int id)
595{
596 struct omap_mcbsp *mcbsp;
597 u16 buffstat, threshold;
598
599 if (!omap_mcbsp_check_valid_id(id)) {
600 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
601 return -ENODEV;
602 }
603 mcbsp = id_to_mcbsp_ptr(id);
604
605 /* Returns the number of used locations in the buffer */
606 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
607 /* RX threshold */
608 threshold = MCBSP_READ(mcbsp, THRSH1);
609
610 /* Return the number of location till we reach the threshold limit */
611 if (threshold <= buffstat)
612 return 0;
613 else
614 return threshold - buffstat;
615}
616EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
617
98cb20e8
PU		 618/*
619 * omap_mcbsp_get_dma_op_mode just return the current configured
620 * operating mode for the mcbsp channel
621 */
622int omap_mcbsp_get_dma_op_mode(unsigned int id)
623{
624 struct omap_mcbsp *mcbsp;
625 int dma_op_mode;
626
627 if (!omap_mcbsp_check_valid_id(id)) {
628 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
629 return -ENODEV;
630 }
631 mcbsp = id_to_mcbsp_ptr(id);
632
98cb20e8 633 dma_op_mode = mcbsp->dma_op_mode;
98cb20e8
PU		 634
635 return dma_op_mode;
636}
637EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
2122fdc6
EN		 638
639static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
640{
641 /*
642 * Enable wakup behavior, smart idle and all wakeups
643 * REVISIT: some wakeups may be unnecessary
644 */
752ec2f2 645 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
2122fdc6
EN		 646 u16 syscon;
647
8ea3200f 648 syscon = MCBSP_READ(mcbsp, SYSCON);
2ba93f8f 649 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
d99a7454 650
fa3935ba
EN		 651 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
652 syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
653 CLOCKACTIVITY(0x02));
8ea3200f 654 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
fa3935ba 655 } else {
d99a7454 656 syscon |= SIDLEMODE(0x01);
fa3935ba 657 }
d99a7454 658
8ea3200f 659 MCBSP_WRITE(mcbsp, SYSCON, syscon);
2122fdc6
EN		 660 }
661}
662
663static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
664{
665 /*
666 * Disable wakup behavior, smart idle and all wakeups
667 */
752ec2f2 668 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
2122fdc6 669 u16 syscon;
2122fdc6 670
8ea3200f 671 syscon = MCBSP_READ(mcbsp, SYSCON);
2ba93f8f 672 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
72cc6d71
EN		 673 /*
674 * HW bug workaround - If no_idle mode is taken, we need to
675 * go to smart_idle before going to always_idle, or the
676 * device will not hit retention anymore.
677 */
678 syscon |= SIDLEMODE(0x02);
8ea3200f 679 MCBSP_WRITE(mcbsp, SYSCON, syscon);
72cc6d71
EN		 680
681 syscon &= ~(SIDLEMODE(0x03));
8ea3200f 682 MCBSP_WRITE(mcbsp, SYSCON, syscon);
2122fdc6 683
8ea3200f 684 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
2122fdc6
EN		 685 }
686}
687#else
688static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
689static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
d912fa92
EN		 690static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
691static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
7aa9ff56
EV		 692#endif
693
120db2cb
TL		 694/*
695 * We can choose between IRQ based or polled IO.
696 * This needs to be called before omap_mcbsp_request().
697 */
698int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
699{
b4b58f58
CS		 700 struct omap_mcbsp *mcbsp;
701
bc5d0c89
EV		 702 if (!omap_mcbsp_check_valid_id(id)) {
703 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
704 return -ENODEV;
705 }
b4b58f58 706 mcbsp = id_to_mcbsp_ptr(id);
120db2cb 707
b4b58f58 708 spin_lock(&mcbsp->lock);
120db2cb 709
b4b58f58
CS		 710 if (!mcbsp->free) {
711 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
712 mcbsp->id);
713 spin_unlock(&mcbsp->lock);
120db2cb
TL		 714 return -EINVAL;
715 }
716
b4b58f58 717 mcbsp->io_type = io_type;
120db2cb 718
b4b58f58 719 spin_unlock(&mcbsp->lock);
120db2cb
TL		 720
721 return 0;
722}
fb78d808 723EXPORT_SYMBOL(omap_mcbsp_set_io_type);
5e1c5ff4 724
5e1c5ff4
TL		 725int omap_mcbsp_request(unsigned int id)
726{
b4b58f58 727 struct omap_mcbsp *mcbsp;
c8c99699 728 void *reg_cache;
5e1c5ff4
TL		 729 int err;
730
bc5d0c89
EV		 731 if (!omap_mcbsp_check_valid_id(id)) {
732 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
733 return -ENODEV;
120db2cb 734 }
b4b58f58 735 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 736
c8c99699
JK		 737 reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
738 if (!reg_cache) {
739 return -ENOMEM;
740 }
741
b4b58f58
CS		 742 spin_lock(&mcbsp->lock);
743 if (!mcbsp->free) {
744 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
745 mcbsp->id);
c8c99699
JK		 746 err = -EBUSY;
747 goto err_kfree;
5e1c5ff4
TL		 748 }
749
b4b58f58 750 mcbsp->free = 0;
c8c99699 751 mcbsp->reg_cache = reg_cache;
b4b58f58 752 spin_unlock(&mcbsp->lock);
5e1c5ff4 753
b820ce4e
RK		 754 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
755 mcbsp->pdata->ops->request(id);
756
757 clk_enable(mcbsp->iclk);
758 clk_enable(mcbsp->fclk);
759
2122fdc6
EN		 760 /* Do procedure specific to omap34xx arch, if applicable */
761 omap34xx_mcbsp_request(mcbsp);
762
5a07055a
JN		 763 /*
764 * Make sure that transmitter, receiver and sample-rate generator are
765 * not running before activating IRQs.
766 */
8ea3200f
JK		 767 MCBSP_WRITE(mcbsp, SPCR1, 0);
768 MCBSP_WRITE(mcbsp, SPCR2, 0);
5a07055a 769
b4b58f58 770 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
120db2cb 771 /* We need to get IRQs here */
5a07055a 772 init_completion(&mcbsp->tx_irq_completion);
b4b58f58
CS		 773 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
774 0, "McBSP", (void *)mcbsp);
120db2cb 775 if (err != 0) {
b4b58f58
CS		 776 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
777 "for McBSP%d\n", mcbsp->tx_irq,
778 mcbsp->id);
c8c99699 779 goto err_clk_disable;
120db2cb 780 }
5e1c5ff4 781
9319b9da
JEC		 782 if (mcbsp->rx_irq) {
783 init_completion(&mcbsp->rx_irq_completion);
784 err = request_irq(mcbsp->rx_irq,
785 omap_mcbsp_rx_irq_handler,
b4b58f58 786 0, "McBSP", (void *)mcbsp);
9319b9da
JEC		 787 if (err != 0) {
788 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
789 "for McBSP%d\n", mcbsp->rx_irq,
790 mcbsp->id);
791 goto err_free_irq;
792 }
120db2cb 793 }
5e1c5ff4
TL		 794 }
795
5e1c5ff4 796 return 0;
c8c99699 797err_free_irq:
1866b545 798 free_irq(mcbsp->tx_irq, (void *)mcbsp);
c8c99699 799err_clk_disable:
1866b545 800 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
c8c99699 801 mcbsp->pdata->ops->free(id);
1866b545
JK		 802
803 /* Do procedure specific to omap34xx arch, if applicable */
804 omap34xx_mcbsp_free(mcbsp);
805
806 clk_disable(mcbsp->fclk);
807 clk_disable(mcbsp->iclk);
808
c8c99699 809 spin_lock(&mcbsp->lock);
1866b545 810 mcbsp->free = 1;
c8c99699
JK		 811 mcbsp->reg_cache = NULL;
812err_kfree:
813 spin_unlock(&mcbsp->lock);
814 kfree(reg_cache);
1866b545
JK		 815
816 return err;
5e1c5ff4 817}
fb78d808 818EXPORT_SYMBOL(omap_mcbsp_request);
5e1c5ff4
TL		 819
820void omap_mcbsp_free(unsigned int id)
821{
b4b58f58 822 struct omap_mcbsp *mcbsp;
c8c99699 823 void *reg_cache;
b4b58f58 824
bc5d0c89
EV		 825 if (!omap_mcbsp_check_valid_id(id)) {
826 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 827 return;
120db2cb 828 }
b4b58f58 829 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 830
b4b58f58
CS		 831 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
832 mcbsp->pdata->ops->free(id);
bc5d0c89 833
2122fdc6
EN		 834 /* Do procedure specific to omap34xx arch, if applicable */
835 omap34xx_mcbsp_free(mcbsp);
836
b820ce4e
RK		 837 clk_disable(mcbsp->fclk);
838 clk_disable(mcbsp->iclk);
839
840 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
841 /* Free IRQs */
9319b9da
JEC		 842 if (mcbsp->rx_irq)
843 free_irq(mcbsp->rx_irq, (void *)mcbsp);
b820ce4e
RK		 844 free_irq(mcbsp->tx_irq, (void *)mcbsp);
845 }
5e1c5ff4 846
c8c99699 847 reg_cache = mcbsp->reg_cache;
5e1c5ff4 848
c8c99699
JK		 849 spin_lock(&mcbsp->lock);
850 if (mcbsp->free)
851 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
852 else
853 mcbsp->free = 1;
854 mcbsp->reg_cache = NULL;
b4b58f58 855 spin_unlock(&mcbsp->lock);
c8c99699
JK		 856
857 if (reg_cache)
858 kfree(reg_cache);
5e1c5ff4 859}
fb78d808 860EXPORT_SYMBOL(omap_mcbsp_free);
5e1c5ff4
TL		 861
862/*
c12abc01
JN		 863 * Here we start the McBSP, by enabling transmitter, receiver or both.
864 * If no transmitter or receiver is active prior calling, then sample-rate
865 * generator and frame sync are started.
5e1c5ff4 866 */
c12abc01 867void omap_mcbsp_start(unsigned int id, int tx, int rx)
5e1c5ff4 868{
b4b58f58 869 struct omap_mcbsp *mcbsp;
c12abc01 870 int idle;
5e1c5ff4
TL		 871 u16 w;
872
bc5d0c89
EV		 873 if (!omap_mcbsp_check_valid_id(id)) {
874 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 875 return;
bc5d0c89 876 }
b4b58f58 877 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 878
d912fa92
EN		 879 if (cpu_is_omap34xx())
880 omap_st_start(mcbsp);
881
96fbd745
JK		 882 mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
883 mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
5e1c5ff4 884
96fbd745
JK		 885 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
886 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
c12abc01
JN		 887
888 if (idle) {
889 /* Start the sample generator */
96fbd745 890 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 891 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
c12abc01 892 }
5e1c5ff4
TL		 893
894 /* Enable transmitter and receiver */
d09a2afc 895 tx &= 1;
96fbd745 896 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 897 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
5e1c5ff4 898
d09a2afc 899 rx &= 1;
96fbd745 900 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
8ea3200f 901 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
5e1c5ff4 902
44a6311c
EV		 903 /*
904 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
905 * REVISIT: 100us may give enough time for two CLKSRG, however
906 * due to some unknown PM related, clock gating etc. reason it
907 * is now at 500us.
908 */
909 udelay(500);
5e1c5ff4 910
c12abc01
JN		 911 if (idle) {
912 /* Start frame sync */
96fbd745 913 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 914 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
c12abc01 915 }
5e1c5ff4 916
752ec2f2 917 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
d09a2afc 918 /* Release the transmitter and receiver */
96fbd745 919 w = MCBSP_READ_CACHE(mcbsp, XCCR);
d09a2afc 920 w &= ~(tx ? XDISABLE : 0);
8ea3200f 921 MCBSP_WRITE(mcbsp, XCCR, w);
96fbd745 922 w = MCBSP_READ_CACHE(mcbsp, RCCR);
d09a2afc 923 w &= ~(rx ? RDISABLE : 0);
8ea3200f 924 MCBSP_WRITE(mcbsp, RCCR, w);
d09a2afc
JN		 925 }
926
5e1c5ff4
TL		 927 /* Dump McBSP Regs */
928 omap_mcbsp_dump_reg(id);
5e1c5ff4 929}
fb78d808 930EXPORT_SYMBOL(omap_mcbsp_start);
5e1c5ff4 931
c12abc01 932void omap_mcbsp_stop(unsigned int id, int tx, int rx)
5e1c5ff4 933{
b4b58f58 934 struct omap_mcbsp *mcbsp;
c12abc01 935 int idle;
5e1c5ff4
TL		 936 u16 w;
937
bc5d0c89
EV		 938 if (!omap_mcbsp_check_valid_id(id)) {
939 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 940 return;
bc5d0c89 941 }
5e1c5ff4 942
b4b58f58 943 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 944
fb78d808 945 /* Reset transmitter */
d09a2afc 946 tx &= 1;
752ec2f2 947 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
96fbd745 948 w = MCBSP_READ_CACHE(mcbsp, XCCR);
d09a2afc 949 w |= (tx ? XDISABLE : 0);
8ea3200f 950 MCBSP_WRITE(mcbsp, XCCR, w);
d09a2afc 951 }
96fbd745 952 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 953 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
5e1c5ff4
TL		 954
955 /* Reset receiver */
d09a2afc 956 rx &= 1;
752ec2f2 957 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
96fbd745 958 w = MCBSP_READ_CACHE(mcbsp, RCCR);
a93d4ed2 959 w |= (rx ? RDISABLE : 0);
8ea3200f 960 MCBSP_WRITE(mcbsp, RCCR, w);
d09a2afc 961 }
96fbd745 962 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
8ea3200f 963 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
5e1c5ff4 964
96fbd745
JK		 965 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
966 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
c12abc01
JN		 967
968 if (idle) {
969 /* Reset the sample rate generator */
96fbd745 970 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 971 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
c12abc01 972 }
d912fa92
EN		 973
974 if (cpu_is_omap34xx())
975 omap_st_stop(mcbsp);
5e1c5ff4 976}
fb78d808 977EXPORT_SYMBOL(omap_mcbsp_stop);
5e1c5ff4 978
bb13b5fd
TL		 979/* polled mcbsp i/o operations */
980int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
981{
b4b58f58 982 struct omap_mcbsp *mcbsp;
bc5d0c89
EV		 983
984 if (!omap_mcbsp_check_valid_id(id)) {
985 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
986 return -ENODEV;
987 }
988
b4b58f58 989 mcbsp = id_to_mcbsp_ptr(id);
b4b58f58 990
8ea3200f 991 MCBSP_WRITE(mcbsp, DXR1, buf);
bb13b5fd 992 /* if frame sync error - clear the error */
8ea3200f 993 if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
bb13b5fd 994 /* clear error */
0841cb82 995 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
bb13b5fd
TL		 996 /* resend */
997 return -1;
998 } else {
999 /* wait for transmit confirmation */
1000 int attemps = 0;
8ea3200f 1001 while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
bb13b5fd 1002 if (attemps++ > 1000) {
8ea3200f 1003 MCBSP_WRITE(mcbsp, SPCR2,
96fbd745
JK		 1004 MCBSP_READ_CACHE(mcbsp, SPCR2) &
1005 (~XRST));
bb13b5fd 1006 udelay(10);
8ea3200f 1007 MCBSP_WRITE(mcbsp, SPCR2,
96fbd745
JK		 1008 MCBSP_READ_CACHE(mcbsp, SPCR2) |
1009 (XRST));
bb13b5fd 1010 udelay(10);
b4b58f58
CS		 1011 dev_err(mcbsp->dev, "Could not write to"
1012 " McBSP%d Register\n", mcbsp->id);
bb13b5fd
TL		 1013 return -2;
1014 }
1015 }
1016 }
fb78d808 1017
bb13b5fd
TL		 1018 return 0;
1019}
fb78d808 1020EXPORT_SYMBOL(omap_mcbsp_pollwrite);
bb13b5fd 1021
fb78d808 1022int omap_mcbsp_pollread(unsigned int id, u16 *buf)
bb13b5fd 1023{
b4b58f58 1024 struct omap_mcbsp *mcbsp;
bc5d0c89
EV		 1025
1026 if (!omap_mcbsp_check_valid_id(id)) {
1027 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1028 return -ENODEV;
1029 }
b4b58f58 1030 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 1031
bb13b5fd 1032 /* if frame sync error - clear the error */
8ea3200f 1033 if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
bb13b5fd 1034 /* clear error */
0841cb82 1035 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
bb13b5fd
TL		 1036 /* resend */
1037 return -1;
1038 } else {
1039 /* wait for recieve confirmation */
1040 int attemps = 0;
8ea3200f 1041 while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
bb13b5fd 1042 if (attemps++ > 1000) {
8ea3200f 1043 MCBSP_WRITE(mcbsp, SPCR1,
96fbd745
JK		 1044 MCBSP_READ_CACHE(mcbsp, SPCR1) &
1045 (~RRST));
bb13b5fd 1046 udelay(10);
8ea3200f 1047 MCBSP_WRITE(mcbsp, SPCR1,
96fbd745
JK		 1048 MCBSP_READ_CACHE(mcbsp, SPCR1) |
1049 (RRST));
bb13b5fd 1050 udelay(10);
b4b58f58
CS		 1051 dev_err(mcbsp->dev, "Could not read from"
1052 " McBSP%d Register\n", mcbsp->id);
bb13b5fd
TL		 1053 return -2;
1054 }
1055 }
1056 }
8ea3200f 1057 *buf = MCBSP_READ(mcbsp, DRR1);
fb78d808 1058
bb13b5fd
TL		 1059 return 0;
1060}
fb78d808 1061EXPORT_SYMBOL(omap_mcbsp_pollread);
bb13b5fd 1062
5e1c5ff4
TL		 1063/*
1064 * IRQ based word transmission.
1065 */
1066void omap_mcbsp_xmit_word(unsigned int id, u32 word)
1067{
b4b58f58 1068 struct omap_mcbsp *mcbsp;
bc5d0c89 1069 omap_mcbsp_word_length word_length;
5e1c5ff4 1070
bc5d0c89
EV		 1071 if (!omap_mcbsp_check_valid_id(id)) {
1072 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 1073 return;
bc5d0c89 1074 }
5e1c5ff4 1075
b4b58f58 1076 mcbsp = id_to_mcbsp_ptr(id);
b4b58f58 1077 word_length = mcbsp->tx_word_length;
5e1c5ff4 1078
b4b58f58 1079 wait_for_completion(&mcbsp->tx_irq_completion);
5e1c5ff4
TL		 1080
1081 if (word_length > OMAP_MCBSP_WORD_16)
8ea3200f
JK		 1082 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1083 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
5e1c5ff4 1084}
fb78d808 1085EXPORT_SYMBOL(omap_mcbsp_xmit_word);
5e1c5ff4
TL		 1086
1087u32 omap_mcbsp_recv_word(unsigned int id)
1088{
b4b58f58 1089 struct omap_mcbsp *mcbsp;
5e1c5ff4 1090 u16 word_lsb, word_msb = 0;
bc5d0c89 1091 omap_mcbsp_word_length word_length;
5e1c5ff4 1092
bc5d0c89
EV		 1093 if (!omap_mcbsp_check_valid_id(id)) {
1094 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1095 return -ENODEV;
1096 }
b4b58f58 1097 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 1098
b4b58f58 1099 word_length = mcbsp->rx_word_length;
5e1c5ff4 1100
b4b58f58 1101 wait_for_completion(&mcbsp->rx_irq_completion);
5e1c5ff4
TL		 1102
1103 if (word_length > OMAP_MCBSP_WORD_16)
8ea3200f
JK		 1104 word_msb = MCBSP_READ(mcbsp, DRR2);
1105 word_lsb = MCBSP_READ(mcbsp, DRR1);
5e1c5ff4
TL		 1106
1107 return (word_lsb | (word_msb << 16));
1108}
fb78d808 1109EXPORT_SYMBOL(omap_mcbsp_recv_word);
5e1c5ff4 1110
120db2cb
TL		 1111int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
1112{
b4b58f58 1113 struct omap_mcbsp *mcbsp;
bc5d0c89
EV		 1114 omap_mcbsp_word_length tx_word_length;
1115 omap_mcbsp_word_length rx_word_length;
120db2cb
TL		 1116 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1117
bc5d0c89
EV		 1118 if (!omap_mcbsp_check_valid_id(id)) {
1119 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1120 return -ENODEV;
1121 }
b4b58f58 1122 mcbsp = id_to_mcbsp_ptr(id);
b4b58f58
CS		 1123 tx_word_length = mcbsp->tx_word_length;
1124 rx_word_length = mcbsp->rx_word_length;
bc5d0c89 1125
120db2cb
TL		 1126 if (tx_word_length != rx_word_length)
1127 return -EINVAL;
1128
1129 /* First we wait for the transmitter to be ready */
8ea3200f 1130 spcr2 = MCBSP_READ(mcbsp, SPCR2);
120db2cb 1131 while (!(spcr2 & XRDY)) {
8ea3200f 1132 spcr2 = MCBSP_READ(mcbsp, SPCR2);
120db2cb
TL		 1133 if (attempts++ > 1000) {
1134 /* We must reset the transmitter */
96fbd745
JK		 1135 MCBSP_WRITE(mcbsp, SPCR2,
1136 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
120db2cb 1137 udelay(10);
96fbd745
JK		 1138 MCBSP_WRITE(mcbsp, SPCR2,
1139 MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
120db2cb 1140 udelay(10);
b4b58f58
CS		 1141 dev_err(mcbsp->dev, "McBSP%d transmitter not "
1142 "ready\n", mcbsp->id);
120db2cb
TL		 1143 return -EAGAIN;
1144 }
1145 }
1146
1147 /* Now we can push the data */
1148 if (tx_word_length > OMAP_MCBSP_WORD_16)
8ea3200f
JK		 1149 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1150 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
120db2cb
TL		 1151
1152 /* We wait for the receiver to be ready */
8ea3200f 1153 spcr1 = MCBSP_READ(mcbsp, SPCR1);
120db2cb 1154 while (!(spcr1 & RRDY)) {
8ea3200f 1155 spcr1 = MCBSP_READ(mcbsp, SPCR1);
120db2cb
TL		 1156 if (attempts++ > 1000) {
1157 /* We must reset the receiver */
96fbd745
JK		 1158 MCBSP_WRITE(mcbsp, SPCR1,
1159 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
120db2cb 1160 udelay(10);
96fbd745
JK		 1161 MCBSP_WRITE(mcbsp, SPCR1,
1162 MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
120db2cb 1163 udelay(10);
b4b58f58
CS		 1164 dev_err(mcbsp->dev, "McBSP%d receiver not "
1165 "ready\n", mcbsp->id);
120db2cb
TL		 1166 return -EAGAIN;
1167 }
1168 }
1169
1170 /* Receiver is ready, let's read the dummy data */
1171 if (rx_word_length > OMAP_MCBSP_WORD_16)
8ea3200f
JK		 1172 word_msb = MCBSP_READ(mcbsp, DRR2);
1173 word_lsb = MCBSP_READ(mcbsp, DRR1);
120db2cb
TL		 1174
1175 return 0;
1176}
fb78d808 1177EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
120db2cb 1178
fb78d808 1179int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
120db2cb 1180{
b4b58f58 1181 struct omap_mcbsp *mcbsp;
d592dd1a 1182 u32 clock_word = 0;
bc5d0c89
EV		 1183 omap_mcbsp_word_length tx_word_length;
1184 omap_mcbsp_word_length rx_word_length;
120db2cb
TL		 1185 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1186
bc5d0c89
EV		 1187 if (!omap_mcbsp_check_valid_id(id)) {
1188 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1189 return -ENODEV;
1190 }
1191
b4b58f58 1192 mcbsp = id_to_mcbsp_ptr(id);
b4b58f58
CS		 1193
1194 tx_word_length = mcbsp->tx_word_length;
1195 rx_word_length = mcbsp->rx_word_length;
bc5d0c89 1196
120db2cb
TL		 1197 if (tx_word_length != rx_word_length)
1198 return -EINVAL;
1199
1200 /* First we wait for the transmitter to be ready */
8ea3200f 1201 spcr2 = MCBSP_READ(mcbsp, SPCR2);
120db2cb 1202 while (!(spcr2 & XRDY)) {
8ea3200f 1203 spcr2 = MCBSP_READ(mcbsp, SPCR2);
120db2cb
TL		 1204 if (attempts++ > 1000) {
1205 /* We must reset the transmitter */
96fbd745
JK		 1206 MCBSP_WRITE(mcbsp, SPCR2,
1207 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
120db2cb 1208 udelay(10);
96fbd745
JK		 1209 MCBSP_WRITE(mcbsp, SPCR2,
1210 MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
120db2cb 1211 udelay(10);
b4b58f58
CS		 1212 dev_err(mcbsp->dev, "McBSP%d transmitter not "
1213 "ready\n", mcbsp->id);
120db2cb
TL		 1214 return -EAGAIN;
1215 }
1216 }
1217
1218 /* We first need to enable the bus clock */
1219 if (tx_word_length > OMAP_MCBSP_WORD_16)
8ea3200f
JK		 1220 MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
1221 MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
120db2cb
TL		 1222
1223 /* We wait for the receiver to be ready */
8ea3200f 1224 spcr1 = MCBSP_READ(mcbsp, SPCR1);
120db2cb 1225 while (!(spcr1 & RRDY)) {
8ea3200f 1226 spcr1 = MCBSP_READ(mcbsp, SPCR1);
120db2cb
TL		 1227 if (attempts++ > 1000) {
1228 /* We must reset the receiver */
96fbd745
JK		 1229 MCBSP_WRITE(mcbsp, SPCR1,
1230 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
120db2cb 1231 udelay(10);
96fbd745
JK		 1232 MCBSP_WRITE(mcbsp, SPCR1,
1233 MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
120db2cb 1234 udelay(10);
b4b58f58
CS		 1235 dev_err(mcbsp->dev, "McBSP%d receiver not "
1236 "ready\n", mcbsp->id);
120db2cb
TL		 1237 return -EAGAIN;
1238 }
1239 }
1240
1241 /* Receiver is ready, there is something for us */
1242 if (rx_word_length > OMAP_MCBSP_WORD_16)
8ea3200f
JK		 1243 word_msb = MCBSP_READ(mcbsp, DRR2);
1244 word_lsb = MCBSP_READ(mcbsp, DRR1);
120db2cb
TL		 1245
1246 word[0] = (word_lsb | (word_msb << 16));
1247
1248 return 0;
1249}
fb78d808 1250EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
120db2cb 1251
5e1c5ff4
TL		 1252/*
1253 * Simple DMA based buffer rx/tx routines.
1254 * Nothing fancy, just a single buffer tx/rx through DMA.
1255 * The DMA resources are released once the transfer is done.
1256 * For anything fancier, you should use your own customized DMA
1257 * routines and callbacks.
1258 */
fb78d808
EV		 1259int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
1260 unsigned int length)
5e1c5ff4 1261{
b4b58f58 1262 struct omap_mcbsp *mcbsp;
5e1c5ff4 1263 int dma_tx_ch;
120db2cb
TL		 1264 int src_port = 0;
1265 int dest_port = 0;
1266 int sync_dev = 0;
5e1c5ff4 1267
bc5d0c89
EV		 1268 if (!omap_mcbsp_check_valid_id(id)) {
1269 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1270 return -ENODEV;
1271 }
b4b58f58 1272 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 1273
b4b58f58 1274 if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
fb78d808 1275 omap_mcbsp_tx_dma_callback,
b4b58f58 1276 mcbsp,
fb78d808 1277 &dma_tx_ch)) {
b4b58f58 1278 dev_err(mcbsp->dev, " Unable to request DMA channel for "
bc5d0c89 1279 "McBSP%d TX. Trying IRQ based TX\n",
b4b58f58 1280 mcbsp->id);
5e1c5ff4
TL		 1281 return -EAGAIN;
1282 }
b4b58f58 1283 mcbsp->dma_tx_lch = dma_tx_ch;
5e1c5ff4 1284
b4b58f58 1285 dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
bc5d0c89 1286 dma_tx_ch);
5e1c5ff4 1287
b4b58f58 1288 init_completion(&mcbsp->tx_dma_completion);
5e1c5ff4 1289
120db2cb
TL		 1290 if (cpu_class_is_omap1()) {
1291 src_port = OMAP_DMA_PORT_TIPB;
1292 dest_port = OMAP_DMA_PORT_EMIFF;
1293 }
bc5d0c89 1294 if (cpu_class_is_omap2())
b4b58f58 1295 sync_dev = mcbsp->dma_tx_sync;
120db2cb 1296
b4b58f58 1297 omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
5e1c5ff4
TL		 1298 OMAP_DMA_DATA_TYPE_S16,
1299 length >> 1, 1,
1a8bfa1e 1300 OMAP_DMA_SYNC_ELEMENT,
120db2cb 1301 sync_dev, 0);
5e1c5ff4 1302
b4b58f58 1303 omap_set_dma_dest_params(mcbsp->dma_tx_lch,
120db2cb 1304 src_port,
5e1c5ff4 1305 OMAP_DMA_AMODE_CONSTANT,
b4b58f58 1306 mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
1a8bfa1e 1307 0, 0);
5e1c5ff4 1308
b4b58f58 1309 omap_set_dma_src_params(mcbsp->dma_tx_lch,
120db2cb 1310 dest_port,
5e1c5ff4 1311 OMAP_DMA_AMODE_POST_INC,
1a8bfa1e
TL		 1312 buffer,
1313 0, 0);
5e1c5ff4 1314
b4b58f58
CS		 1315 omap_start_dma(mcbsp->dma_tx_lch);
1316 wait_for_completion(&mcbsp->tx_dma_completion);
fb78d808 1317
5e1c5ff4
TL		 1318 return 0;
1319}
fb78d808 1320EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
5e1c5ff4 1321
fb78d808
EV		 1322int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
1323 unsigned int length)
5e1c5ff4 1324{
b4b58f58 1325 struct omap_mcbsp *mcbsp;
5e1c5ff4 1326 int dma_rx_ch;
120db2cb
TL		 1327 int src_port = 0;
1328 int dest_port = 0;
1329 int sync_dev = 0;
5e1c5ff4 1330
bc5d0c89
EV		 1331 if (!omap_mcbsp_check_valid_id(id)) {
1332 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1333 return -ENODEV;
1334 }
b4b58f58 1335 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 1336
b4b58f58 1337 if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
fb78d808 1338 omap_mcbsp_rx_dma_callback,
b4b58f58 1339 mcbsp,
fb78d808 1340 &dma_rx_ch)) {
b4b58f58 1341 dev_err(mcbsp->dev, "Unable to request DMA channel for "
bc5d0c89 1342 "McBSP%d RX. Trying IRQ based RX\n",
b4b58f58 1343 mcbsp->id);
5e1c5ff4
TL		 1344 return -EAGAIN;
1345 }
b4b58f58 1346 mcbsp->dma_rx_lch = dma_rx_ch;
5e1c5ff4 1347
b4b58f58 1348 dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
bc5d0c89 1349 dma_rx_ch);
5e1c5ff4 1350
b4b58f58 1351 init_completion(&mcbsp->rx_dma_completion);
5e1c5ff4 1352
120db2cb
TL		 1353 if (cpu_class_is_omap1()) {
1354 src_port = OMAP_DMA_PORT_TIPB;
1355 dest_port = OMAP_DMA_PORT_EMIFF;
1356 }
bc5d0c89 1357 if (cpu_class_is_omap2())
b4b58f58 1358 sync_dev = mcbsp->dma_rx_sync;
120db2cb 1359
b4b58f58 1360 omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
fb78d808
EV		 1361 OMAP_DMA_DATA_TYPE_S16,
1362 length >> 1, 1,
1363 OMAP_DMA_SYNC_ELEMENT,
1364 sync_dev, 0);
5e1c5ff4 1365
b4b58f58 1366 omap_set_dma_src_params(mcbsp->dma_rx_lch,
120db2cb 1367 src_port,
5e1c5ff4 1368 OMAP_DMA_AMODE_CONSTANT,
b4b58f58 1369 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1a8bfa1e 1370 0, 0);
5e1c5ff4 1371
b4b58f58 1372 omap_set_dma_dest_params(mcbsp->dma_rx_lch,
fb78d808
EV		 1373 dest_port,
1374 OMAP_DMA_AMODE_POST_INC,
1375 buffer,
1376 0, 0);
5e1c5ff4 1377
b4b58f58
CS		 1378 omap_start_dma(mcbsp->dma_rx_lch);
1379 wait_for_completion(&mcbsp->rx_dma_completion);
fb78d808 1380
5e1c5ff4
TL		 1381 return 0;
1382}
fb78d808 1383EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
5e1c5ff4
TL		 1384
1385/*
1386 * SPI wrapper.
1387 * Since SPI setup is much simpler than the generic McBSP one,
1388 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1389 * Once this is done, you can call omap_mcbsp_start().
1390 */
fb78d808
EV		 1391void omap_mcbsp_set_spi_mode(unsigned int id,
1392 const struct omap_mcbsp_spi_cfg *spi_cfg)
5e1c5ff4 1393{
b4b58f58 1394 struct omap_mcbsp *mcbsp;
5e1c5ff4
TL		 1395 struct omap_mcbsp_reg_cfg mcbsp_cfg;
1396
bc5d0c89
EV		 1397 if (!omap_mcbsp_check_valid_id(id)) {
1398 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 1399 return;
bc5d0c89 1400 }
b4b58f58 1401 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4
TL		 1402
1403 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1404
1405 /* SPI has only one frame */
1406 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1407 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1408
fb78d808 1409 /* Clock stop mode */
5e1c5ff4
TL		 1410 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1411 mcbsp_cfg.spcr1 |= (1 << 12);
1412 else
1413 mcbsp_cfg.spcr1 |= (3 << 11);
1414
1415 /* Set clock parities */
1416 if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1417 mcbsp_cfg.pcr0 |= CLKRP;
1418 else
1419 mcbsp_cfg.pcr0 &= ~CLKRP;
1420
1421 if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1422 mcbsp_cfg.pcr0 &= ~CLKXP;
1423 else
1424 mcbsp_cfg.pcr0 |= CLKXP;
1425
1426 /* Set SCLKME to 0 and CLKSM to 1 */
1427 mcbsp_cfg.pcr0 &= ~SCLKME;
1428 mcbsp_cfg.srgr2 |= CLKSM;
1429
1430 /* Set FSXP */
1431 if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1432 mcbsp_cfg.pcr0 &= ~FSXP;
1433 else
1434 mcbsp_cfg.pcr0 |= FSXP;
1435
1436 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1437 mcbsp_cfg.pcr0 |= CLKXM;
fb78d808 1438 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
5e1c5ff4
TL		 1439 mcbsp_cfg.pcr0 |= FSXM;
1440 mcbsp_cfg.srgr2 &= ~FSGM;
1441 mcbsp_cfg.xcr2 |= XDATDLY(1);
1442 mcbsp_cfg.rcr2 |= RDATDLY(1);
fb78d808 1443 } else {
5e1c5ff4
TL		 1444 mcbsp_cfg.pcr0 &= ~CLKXM;
1445 mcbsp_cfg.srgr1 |= CLKGDV(1);
1446 mcbsp_cfg.pcr0 &= ~FSXM;
1447 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1448 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1449 }
1450
1451 mcbsp_cfg.xcr2 &= ~XPHASE;
1452 mcbsp_cfg.rcr2 &= ~RPHASE;
1453
1454 omap_mcbsp_config(id, &mcbsp_cfg);
1455}
fb78d808 1456EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
5e1c5ff4 1457
a8eb7ca0 1458#ifdef CONFIG_ARCH_OMAP3
a1a56f5f
EV		 1459#define max_thres(m) (mcbsp->pdata->buffer_size)
1460#define valid_threshold(m, val) ((val) <= max_thres(m))
1461#define THRESHOLD_PROP_BUILDER(prop) \
1462static ssize_t prop##_show(struct device *dev, \
1463 struct device_attribute *attr, char *buf) \
1464{ \
1465 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1466 \
1467 return sprintf(buf, "%u\n", mcbsp->prop); \
1468} \
1469 \
1470static ssize_t prop##_store(struct device *dev, \
1471 struct device_attribute *attr, \
1472 const char *buf, size_t size) \
1473{ \
1474 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1475 unsigned long val; \
1476 int status; \
1477 \
1478 status = strict_strtoul(buf, 0, &val); \
1479 if (status) \
1480 return status; \
1481 \
1482 if (!valid_threshold(mcbsp, val)) \
1483 return -EDOM; \
1484 \
1485 mcbsp->prop = val; \
1486 return size; \
1487} \
1488 \
1489static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1490
1491THRESHOLD_PROP_BUILDER(max_tx_thres);
1492THRESHOLD_PROP_BUILDER(max_rx_thres);
1493
9b300509
JN		 1494static const char *dma_op_modes[] = {
1495 "element", "threshold", "frame",
1496};
1497
98cb20e8
PU		 1498static ssize_t dma_op_mode_show(struct device *dev,
1499 struct device_attribute *attr, char *buf)
1500{
1501 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
9b300509
JN		 1502 int dma_op_mode, i = 0;
1503 ssize_t len = 0;
1504 const char * const *s;
98cb20e8 1505
98cb20e8 1506 dma_op_mode = mcbsp->dma_op_mode;
98cb20e8 1507
9b300509
JN		 1508 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1509 if (dma_op_mode == i)
1510 len += sprintf(buf + len, "[%s] ", *s);
1511 else
1512 len += sprintf(buf + len, "%s ", *s);
1513 }
1514 len += sprintf(buf + len, "\n");
1515
1516 return len;
98cb20e8
PU		 1517}
1518
1519static ssize_t dma_op_mode_store(struct device *dev,
1520 struct device_attribute *attr,
1521 const char *buf, size_t size)
1522{
1523 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
9b300509
JN		 1524 const char * const *s;
1525 int i = 0;
98cb20e8 1526
9b300509
JN		 1527 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1528 if (sysfs_streq(buf, *s))
1529 break;
98cb20e8 1530
9b300509
JN		 1531 if (i == ARRAY_SIZE(dma_op_modes))
1532 return -EINVAL;
98cb20e8 1533
9b300509 1534 spin_lock_irq(&mcbsp->lock);
98cb20e8
PU		 1535 if (!mcbsp->free) {
1536 size = -EBUSY;
1537 goto unlock;
1538 }
9b300509 1539 mcbsp->dma_op_mode = i;
98cb20e8
PU		 1540
1541unlock:
1542 spin_unlock_irq(&mcbsp->lock);
1543
1544 return size;
1545}
1546
1547static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1548
d912fa92
EN		 1549static ssize_t st_taps_show(struct device *dev,
1550 struct device_attribute *attr, char *buf)
1551{
1552 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1553 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1554 ssize_t status = 0;
1555 int i;
1556
1557 spin_lock_irq(&mcbsp->lock);
1558 for (i = 0; i < st_data->nr_taps; i++)
1559 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1560 st_data->taps[i]);
1561 if (i)
1562 status += sprintf(&buf[status], "\n");
1563 spin_unlock_irq(&mcbsp->lock);
1564
1565 return status;
1566}
1567
1568static ssize_t st_taps_store(struct device *dev,
1569 struct device_attribute *attr,
1570 const char *buf, size_t size)
1571{
1572 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1573 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1574 int val, tmp, status, i = 0;
1575
1576 spin_lock_irq(&mcbsp->lock);
1577 memset(st_data->taps, 0, sizeof(st_data->taps));
1578 st_data->nr_taps = 0;
1579
1580 do {
1581 status = sscanf(buf, "%d%n", &val, &tmp);
1582 if (status < 0 || status == 0) {
1583 size = -EINVAL;
1584 goto out;
1585 }
1586 if (val < -32768 || val > 32767) {
1587 size = -EINVAL;
1588 goto out;
1589 }
1590 st_data->taps[i++] = val;
1591 buf += tmp;
1592 if (*buf != ',')
1593 break;
1594 buf++;
1595 } while (1);
1596
1597 st_data->nr_taps = i;
1598
1599out:
1600 spin_unlock_irq(&mcbsp->lock);
1601
1602 return size;
1603}
1604
1605static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1606
4c8200ae 1607static const struct attribute *additional_attrs[] = {
a1a56f5f
EV		 1608 &dev_attr_max_tx_thres.attr,
1609 &dev_attr_max_rx_thres.attr,
98cb20e8 1610 &dev_attr_dma_op_mode.attr,
a1a56f5f
EV		 1611 NULL,
1612};
1613
4c8200ae
EV		 1614static const struct attribute_group additional_attr_group = {
1615 .attrs = (struct attribute **)additional_attrs,
a1a56f5f
EV		 1616};
1617
4c8200ae 1618static inline int __devinit omap_additional_add(struct device *dev)
a1a56f5f 1619{
4c8200ae 1620 return sysfs_create_group(&dev->kobj, &additional_attr_group);
a1a56f5f
EV		 1621}
1622
4c8200ae 1623static inline void __devexit omap_additional_remove(struct device *dev)
a1a56f5f 1624{
4c8200ae 1625 sysfs_remove_group(&dev->kobj, &additional_attr_group);
a1a56f5f
EV		 1626}
1627
d912fa92
EN		 1628static const struct attribute *sidetone_attrs[] = {
1629 &dev_attr_st_taps.attr,
1630 NULL,
1631};
1632
1633static const struct attribute_group sidetone_attr_group = {
1634 .attrs = (struct attribute **)sidetone_attrs,
1635};
1636
1637int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1638{
1639 struct omap_mcbsp_platform_data *pdata = mcbsp->pdata;
1640 struct omap_mcbsp_st_data *st_data;
1641 int err;
1642
1643 st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1644 if (!st_data) {
1645 err = -ENOMEM;
1646 goto err1;
1647 }
1648
1649 st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K);
1650 if (!st_data->io_base_st) {
1651 err = -ENOMEM;
1652 goto err2;
1653 }
1654
1655 err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1656 if (err)
1657 goto err3;
1658
1659 mcbsp->st_data = st_data;
1660 return 0;
1661
1662err3:
1663 iounmap(st_data->io_base_st);
1664err2:
1665 kfree(st_data);
1666err1:
1667 return err;
1668
1669}
1670
1671static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1672{
1673 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1674
1675 if (st_data) {
1676 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1677 iounmap(st_data->io_base_st);
1678 kfree(st_data);
1679 }
1680}
1681
a1a56f5f
EV		 1682static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1683{
98cb20e8 1684 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
a1a56f5f
EV		 1685 if (cpu_is_omap34xx()) {
1686 mcbsp->max_tx_thres = max_thres(mcbsp);
1687 mcbsp->max_rx_thres = max_thres(mcbsp);
98cb20e8
PU		 1688 /*
1689 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1690 * for mcbsp2 instances.
1691 */
4c8200ae 1692 if (omap_additional_add(mcbsp->dev))
a1a56f5f 1693 dev_warn(mcbsp->dev,
4c8200ae 1694 "Unable to create additional controls\n");
d912fa92
EN		 1695
1696 if (mcbsp->id == 2 || mcbsp->id == 3)
1697 if (omap_st_add(mcbsp))
1698 dev_warn(mcbsp->dev,
1699 "Unable to create sidetone controls\n");
1700
a1a56f5f
EV		 1701 } else {
1702 mcbsp->max_tx_thres = -EINVAL;
1703 mcbsp->max_rx_thres = -EINVAL;
1704 }
1705}
1706
1707static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1708{
d912fa92 1709 if (cpu_is_omap34xx()) {
4c8200ae 1710 omap_additional_remove(mcbsp->dev);
d912fa92
EN		 1711
1712 if (mcbsp->id == 2 || mcbsp->id == 3)
1713 omap_st_remove(mcbsp);
1714 }
a1a56f5f
EV		 1715}
1716#else
1717static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1718static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
a8eb7ca0 1719#endif /* CONFIG_ARCH_OMAP3 */
a1a56f5f 1720
5e1c5ff4
TL		 1721/*
1722 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1723 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1724 */
25cef225 1725static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
bc5d0c89
EV		 1726{
1727 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
b4b58f58 1728 struct omap_mcbsp *mcbsp;
bc5d0c89
EV		 1729 int id = pdev->id - 1;
1730 int ret = 0;
5e1c5ff4 1731
bc5d0c89
EV		 1732 if (!pdata) {
1733 dev_err(&pdev->dev, "McBSP device initialized without"
1734 "platform data\n");
1735 ret = -EINVAL;
1736 goto exit;
1737 }
1738
1739 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1740
b4b58f58 1741 if (id >= omap_mcbsp_count) {
bc5d0c89
EV		 1742 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1743 ret = -EINVAL;
1744 goto exit;
1745 }
1746
b4b58f58
CS		 1747 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1748 if (!mcbsp) {
1749 ret = -ENOMEM;
1750 goto exit;
1751 }
b4b58f58
CS		 1752
1753 spin_lock_init(&mcbsp->lock);
1754 mcbsp->id = id + 1;
1755 mcbsp->free = 1;
1756 mcbsp->dma_tx_lch = -1;
1757 mcbsp->dma_rx_lch = -1;
bc5d0c89 1758
b4b58f58
CS		 1759 mcbsp->phys_base = pdata->phys_base;
1760 mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
1761 if (!mcbsp->io_base) {
d592dd1a
RK		 1762 ret = -ENOMEM;
1763 goto err_ioremap;
1764 }
1765
bc5d0c89 1766 /* Default I/O is IRQ based */
b4b58f58
CS		 1767 mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1768 mcbsp->tx_irq = pdata->tx_irq;
1769 mcbsp->rx_irq = pdata->rx_irq;
1770 mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1771 mcbsp->dma_tx_sync = pdata->dma_tx_sync;
bc5d0c89 1772
b820ce4e
RK		 1773 mcbsp->iclk = clk_get(&pdev->dev, "ick");
1774 if (IS_ERR(mcbsp->iclk)) {
1775 ret = PTR_ERR(mcbsp->iclk);
1776 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1777 goto err_iclk;
1778 }
06151158 1779
b820ce4e
RK		 1780 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1781 if (IS_ERR(mcbsp->fclk)) {
1782 ret = PTR_ERR(mcbsp->fclk);
1783 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1784 goto err_fclk;
bc5d0c89
EV		 1785 }
1786
b4b58f58
CS		 1787 mcbsp->pdata = pdata;
1788 mcbsp->dev = &pdev->dev;
b820ce4e 1789 mcbsp_ptr[id] = mcbsp;
b4b58f58 1790 platform_set_drvdata(pdev, mcbsp);
a1a56f5f
EV		 1791
1792 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1793 omap34xx_device_init(mcbsp);
1794
d592dd1a 1795 return 0;
bc5d0c89 1796
b820ce4e
RK		 1797err_fclk:
1798 clk_put(mcbsp->iclk);
1799err_iclk:
b4b58f58 1800 iounmap(mcbsp->io_base);
d592dd1a 1801err_ioremap:
b820ce4e 1802 kfree(mcbsp);
bc5d0c89
EV		 1803exit:
1804 return ret;
1805}
120db2cb 1806
25cef225 1807static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
5e1c5ff4 1808{
bc5d0c89 1809 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
5e1c5ff4 1810
bc5d0c89
EV		 1811 platform_set_drvdata(pdev, NULL);
1812 if (mcbsp) {
5e1c5ff4 1813
bc5d0c89
EV		 1814 if (mcbsp->pdata && mcbsp->pdata->ops &&
1815 mcbsp->pdata->ops->free)
1816 mcbsp->pdata->ops->free(mcbsp->id);
5e1c5ff4 1817
a1a56f5f
EV		 1818 omap34xx_device_exit(mcbsp);
1819
b820ce4e
RK		 1820 clk_disable(mcbsp->fclk);
1821 clk_disable(mcbsp->iclk);
1822 clk_put(mcbsp->fclk);
1823 clk_put(mcbsp->iclk);
bc5d0c89 1824
d592dd1a
RK		 1825 iounmap(mcbsp->io_base);
1826
b820ce4e
RK		 1827 mcbsp->fclk = NULL;
1828 mcbsp->iclk = NULL;
bc5d0c89
EV		 1829 mcbsp->free = 0;
1830 mcbsp->dev = NULL;
5e1c5ff4
TL		 1831 }
1832
1833 return 0;
1834}
1835
bc5d0c89
EV		 1836static struct platform_driver omap_mcbsp_driver = {
1837 .probe = omap_mcbsp_probe,
25cef225 1838 .remove = __devexit_p(omap_mcbsp_remove),
bc5d0c89
EV		 1839 .driver = {
1840 .name = "omap-mcbsp",
1841 },
1842};
1843
1844int __init omap_mcbsp_init(void)
1845{
1846 /* Register the McBSP driver */
1847 return platform_driver_register(&omap_mcbsp_driver);
1848}
Linux kernel - Deliverables
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