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ARM: OMAP: mcbsp: Make tranceiver configuration control register access generic
[deliverable/linux.git] / arch / arm / plat-omap / mcbsp.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/mcbsp.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Multichannel mode not supported.
13 */
14
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/device.h>
bc5d0c89 18#include <linux/platform_device.h>
5e1c5ff4
TL		 19#include <linux/interrupt.h>
20#include <linux/err.h>
f8ce2547 21#include <linux/clk.h>
04fbf6a2 22#include <linux/delay.h>
fb78d808 23#include <linux/io.h>
5a0e3ad6 24#include <linux/slab.h>
5e1c5ff4 25
ce491cf8 26#include <plat/mcbsp.h>
e95496d4 27#include <linux/pm_runtime.h>
5e1c5ff4 28
59fb659b
PW		 29/* XXX These "sideways" includes are a sign that something is wrong */
30#include "../mach-omap2/cm2xxx_3xxx.h"
d912fa92
EN		 31#include "../mach-omap2/cm-regbits-34xx.h"
32
b4b58f58 33struct omap_mcbsp **mcbsp_ptr;
c8c99699 34int omap_mcbsp_count, omap_mcbsp_cache_size;
bc5d0c89 35
b0a330dc 36static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
b4b58f58 37{
cdc71514
JN		 38 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
39
40 if (mcbsp->pdata->reg_size == 2) {
41 ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
42 __raw_writew((u16)val, addr);
c8c99699 43 } else {
cdc71514
JN		 44 ((u32 *)mcbsp->reg_cache)[reg] = val;
45 __raw_writel(val, addr);
c8c99699 46 }
b4b58f58
CS		 47}
48
b0a330dc 49static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
b4b58f58 50{
cdc71514
JN		 51 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
52
53 if (mcbsp->pdata->reg_size == 2) {
54 return !from_cache ? __raw_readw(addr) :
55 ((u16 *)mcbsp->reg_cache)[reg];
c8c99699 56 } else {
cdc71514
JN		 57 return !from_cache ? __raw_readl(addr) :
58 ((u32 *)mcbsp->reg_cache)[reg];
c8c99699 59 }
b4b58f58
CS		 60}
61
d912fa92 62#ifdef CONFIG_ARCH_OMAP3
b0a330dc 63static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
d912fa92
EN		 64{
65 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
66}
67
b0a330dc 68static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
d912fa92
EN		 69{
70 return __raw_readl(mcbsp->st_data->io_base_st + reg);
71}
72#endif
73
8ea3200f 74#define MCBSP_READ(mcbsp, reg) \
c8c99699 75 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
8ea3200f
JK		 76#define MCBSP_WRITE(mcbsp, reg, val) \
77 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
c8c99699
JK		 78#define MCBSP_READ_CACHE(mcbsp, reg) \
79 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
b4b58f58 80
d912fa92
EN		 81#define MCBSP_ST_READ(mcbsp, reg) \
82 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
83#define MCBSP_ST_WRITE(mcbsp, reg, val) \
84 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
85
5e1c5ff4
TL		 86static void omap_mcbsp_dump_reg(u8 id)
87{
b4b58f58
CS		 88 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
89
90 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
91 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
8ea3200f 92 MCBSP_READ(mcbsp, DRR2));
b4b58f58 93 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
8ea3200f 94 MCBSP_READ(mcbsp, DRR1));
b4b58f58 95 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
8ea3200f 96 MCBSP_READ(mcbsp, DXR2));
b4b58f58 97 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
8ea3200f 98 MCBSP_READ(mcbsp, DXR1));
b4b58f58 99 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
8ea3200f 100 MCBSP_READ(mcbsp, SPCR2));
b4b58f58 101 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
8ea3200f 102 MCBSP_READ(mcbsp, SPCR1));
b4b58f58 103 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
8ea3200f 104 MCBSP_READ(mcbsp, RCR2));
b4b58f58 105 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
8ea3200f 106 MCBSP_READ(mcbsp, RCR1));
b4b58f58 107 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
8ea3200f 108 MCBSP_READ(mcbsp, XCR2));
b4b58f58 109 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
8ea3200f 110 MCBSP_READ(mcbsp, XCR1));
b4b58f58 111 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
8ea3200f 112 MCBSP_READ(mcbsp, SRGR2));
b4b58f58 113 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
8ea3200f 114 MCBSP_READ(mcbsp, SRGR1));
b4b58f58 115 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
8ea3200f 116 MCBSP_READ(mcbsp, PCR0));
b4b58f58 117 dev_dbg(mcbsp->dev, "***********************\n");
5e1c5ff4
TL		 118}
119
0cd61b68 120static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
5e1c5ff4 121{
e8f2af17 122 struct omap_mcbsp *mcbsp_tx = dev_id;
d6d834b0 123 u16 irqst_spcr2;
5e1c5ff4 124
8ea3200f 125 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
d6d834b0 126 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
5e1c5ff4 127
d6d834b0
EN		 128 if (irqst_spcr2 & XSYNC_ERR) {
129 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
130 irqst_spcr2);
131 /* Writing zero to XSYNC_ERR clears the IRQ */
0841cb82 132 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
d6d834b0 133 }
fb78d808 134
5e1c5ff4
TL		 135 return IRQ_HANDLED;
136}
137
0cd61b68 138static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
5e1c5ff4 139{
e8f2af17 140 struct omap_mcbsp *mcbsp_rx = dev_id;
d6d834b0
EN		 141 u16 irqst_spcr1;
142
8ea3200f 143 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
d6d834b0
EN		 144 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
145
146 if (irqst_spcr1 & RSYNC_ERR) {
147 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
148 irqst_spcr1);
149 /* Writing zero to RSYNC_ERR clears the IRQ */
0841cb82 150 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
d6d834b0 151 }
fb78d808 152
5e1c5ff4
TL		 153 return IRQ_HANDLED;
154}
155
5e1c5ff4
TL		 156/*
157 * omap_mcbsp_config simply write a config to the
158 * appropriate McBSP.
159 * You either call this function or set the McBSP registers
160 * by yourself before calling omap_mcbsp_start().
161 */
fb78d808 162void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
5e1c5ff4 163{
b4b58f58 164 struct omap_mcbsp *mcbsp;
5e1c5ff4 165
bc5d0c89
EV		 166 if (!omap_mcbsp_check_valid_id(id)) {
167 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
168 return;
169 }
b4b58f58 170 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 171
b4b58f58
CS		 172 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
173 mcbsp->id, mcbsp->phys_base);
5e1c5ff4
TL		 174
175 /* We write the given config */
8ea3200f
JK		 176 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
177 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
178 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
179 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
180 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
181 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
182 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
183 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
184 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
185 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
186 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
88408230 187 if (mcbsp->pdata->has_ccr) {
8ea3200f
JK		 188 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
189 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
3127f8f8 190 }
5e1c5ff4 191}
fb78d808 192EXPORT_SYMBOL(omap_mcbsp_config);
5e1c5ff4 193
9504ba64
KVA		 194/**
195 * omap_mcbsp_dma_params - returns the dma channel number
196 * @id - mcbsp id
197 * @stream - indicates the direction of data flow (rx or tx)
198 *
199 * Returns the dma channel number for the rx channel or tx channel
200 * based on the value of @stream for the requested mcbsp given by @id
201 */
202int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream)
203{
204 struct omap_mcbsp *mcbsp;
205
206 if (!omap_mcbsp_check_valid_id(id)) {
207 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
208 return -ENODEV;
209 }
210 mcbsp = id_to_mcbsp_ptr(id);
211
212 if (stream)
213 return mcbsp->dma_rx_sync;
214 else
215 return mcbsp->dma_tx_sync;
216}
217EXPORT_SYMBOL(omap_mcbsp_dma_ch_params);
218
219/**
220 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
221 * @id - mcbsp id
222 * @stream - indicates the direction of data flow (rx or tx)
223 *
224 * Returns the address of mcbsp data transmit register or data receive register
225 * to be used by DMA for transferring/receiving data based on the value of
226 * @stream for the requested mcbsp given by @id
227 */
228int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
229{
230 struct omap_mcbsp *mcbsp;
231 int data_reg;
232
233 if (!omap_mcbsp_check_valid_id(id)) {
234 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
235 return -ENODEV;
236 }
237 mcbsp = id_to_mcbsp_ptr(id);
238
cdc71514 239 if (mcbsp->pdata->reg_size == 2) {
9504ba64 240 if (stream)
cdc71514 241 data_reg = OMAP_MCBSP_REG_DRR1;
9504ba64 242 else
cdc71514 243 data_reg = OMAP_MCBSP_REG_DXR1;
9504ba64
KVA		 244 } else {
245 if (stream)
cdc71514 246 data_reg = OMAP_MCBSP_REG_DRR;
9504ba64 247 else
cdc71514 248 data_reg = OMAP_MCBSP_REG_DXR;
9504ba64
KVA		 249 }
250
cdc71514 251 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
9504ba64
KVA		 252}
253EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
254
a8eb7ca0 255#ifdef CONFIG_ARCH_OMAP3
d912fa92
EN		 256static void omap_st_on(struct omap_mcbsp *mcbsp)
257{
258 unsigned int w;
259
260 /*
261 * Sidetone uses McBSP ICLK - which must not idle when sidetones
262 * are enabled or sidetones start sounding ugly.
263 */
c4d7e58f 264 w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
d912fa92 265 w &= ~(1 << (mcbsp->id - 2));
c4d7e58f 266 omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
d912fa92
EN		 267
268 /* Enable McBSP Sidetone */
269 w = MCBSP_READ(mcbsp, SSELCR);
270 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
271
d912fa92
EN		 272 /* Enable Sidetone from Sidetone Core */
273 w = MCBSP_ST_READ(mcbsp, SSELCR);
274 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
275}
276
277static void omap_st_off(struct omap_mcbsp *mcbsp)
278{
279 unsigned int w;
280
281 w = MCBSP_ST_READ(mcbsp, SSELCR);
282 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
283
d912fa92
EN		 284 w = MCBSP_READ(mcbsp, SSELCR);
285 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
286
c4d7e58f 287 w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
d912fa92 288 w |= 1 << (mcbsp->id - 2);
c4d7e58f 289 omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
d912fa92
EN		 290}
291
292static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
293{
294 u16 val, i;
d912fa92
EN		 295
296 val = MCBSP_ST_READ(mcbsp, SSELCR);
297
298 if (val & ST_COEFFWREN)
299 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
300
301 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
302
303 for (i = 0; i < 128; i++)
304 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
305
306 i = 0;
307
308 val = MCBSP_ST_READ(mcbsp, SSELCR);
309 while (!(val & ST_COEFFWRDONE) && (++i < 1000))
310 val = MCBSP_ST_READ(mcbsp, SSELCR);
311
312 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
313
314 if (i == 1000)
315 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
316}
317
318static void omap_st_chgain(struct omap_mcbsp *mcbsp)
319{
320 u16 w;
321 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
d912fa92
EN		 322
323 w = MCBSP_ST_READ(mcbsp, SSELCR);
324
325 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
326 ST_CH1GAIN(st_data->ch1gain));
327}
328
329int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
330{
331 struct omap_mcbsp *mcbsp;
332 struct omap_mcbsp_st_data *st_data;
333 int ret = 0;
334
335 if (!omap_mcbsp_check_valid_id(id)) {
336 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
337 return -ENODEV;
338 }
339
340 mcbsp = id_to_mcbsp_ptr(id);
341 st_data = mcbsp->st_data;
342
343 if (!st_data)
344 return -ENOENT;
345
346 spin_lock_irq(&mcbsp->lock);
347 if (channel == 0)
348 st_data->ch0gain = chgain;
349 else if (channel == 1)
350 st_data->ch1gain = chgain;
351 else
352 ret = -EINVAL;
353
354 if (st_data->enabled)
355 omap_st_chgain(mcbsp);
356 spin_unlock_irq(&mcbsp->lock);
357
358 return ret;
359}
360EXPORT_SYMBOL(omap_st_set_chgain);
361
362int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
363{
364 struct omap_mcbsp *mcbsp;
365 struct omap_mcbsp_st_data *st_data;
366 int ret = 0;
367
368 if (!omap_mcbsp_check_valid_id(id)) {
369 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
370 return -ENODEV;
371 }
372
373 mcbsp = id_to_mcbsp_ptr(id);
374 st_data = mcbsp->st_data;
375
376 if (!st_data)
377 return -ENOENT;
378
379 spin_lock_irq(&mcbsp->lock);
380 if (channel == 0)
381 *chgain = st_data->ch0gain;
382 else if (channel == 1)
383 *chgain = st_data->ch1gain;
384 else
385 ret = -EINVAL;
386 spin_unlock_irq(&mcbsp->lock);
387
388 return ret;
389}
390EXPORT_SYMBOL(omap_st_get_chgain);
391
392static int omap_st_start(struct omap_mcbsp *mcbsp)
393{
394 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
395
396 if (st_data && st_data->enabled && !st_data->running) {
397 omap_st_fir_write(mcbsp, st_data->taps);
398 omap_st_chgain(mcbsp);
399
400 if (!mcbsp->free) {
401 omap_st_on(mcbsp);
402 st_data->running = 1;
403 }
404 }
405
406 return 0;
407}
408
409int omap_st_enable(unsigned int id)
410{
411 struct omap_mcbsp *mcbsp;
412 struct omap_mcbsp_st_data *st_data;
413
414 if (!omap_mcbsp_check_valid_id(id)) {
415 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
416 return -ENODEV;
417 }
418
419 mcbsp = id_to_mcbsp_ptr(id);
420 st_data = mcbsp->st_data;
421
422 if (!st_data)
423 return -ENODEV;
424
425 spin_lock_irq(&mcbsp->lock);
426 st_data->enabled = 1;
427 omap_st_start(mcbsp);
428 spin_unlock_irq(&mcbsp->lock);
429
430 return 0;
431}
432EXPORT_SYMBOL(omap_st_enable);
433
434static int omap_st_stop(struct omap_mcbsp *mcbsp)
435{
436 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
437
438 if (st_data && st_data->running) {
439 if (!mcbsp->free) {
440 omap_st_off(mcbsp);
441 st_data->running = 0;
442 }
443 }
444
445 return 0;
446}
447
448int omap_st_disable(unsigned int id)
449{
450 struct omap_mcbsp *mcbsp;
451 struct omap_mcbsp_st_data *st_data;
452 int ret = 0;
453
454 if (!omap_mcbsp_check_valid_id(id)) {
455 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
456 return -ENODEV;
457 }
458
459 mcbsp = id_to_mcbsp_ptr(id);
460 st_data = mcbsp->st_data;
461
462 if (!st_data)
463 return -ENODEV;
464
465 spin_lock_irq(&mcbsp->lock);
466 omap_st_stop(mcbsp);
467 st_data->enabled = 0;
468 spin_unlock_irq(&mcbsp->lock);
469
470 return ret;
471}
472EXPORT_SYMBOL(omap_st_disable);
473
474int omap_st_is_enabled(unsigned int id)
475{
476 struct omap_mcbsp *mcbsp;
477 struct omap_mcbsp_st_data *st_data;
478
479 if (!omap_mcbsp_check_valid_id(id)) {
480 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
481 return -ENODEV;
482 }
483
484 mcbsp = id_to_mcbsp_ptr(id);
485 st_data = mcbsp->st_data;
486
487 if (!st_data)
488 return -ENODEV;
489
490
491 return st_data->enabled;
492}
493EXPORT_SYMBOL(omap_st_is_enabled);
494
7aa9ff56 495/*
451fd82d
PU		 496 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
497 * The threshold parameter is 1 based, and it is converted (threshold - 1)
498 * for the THRSH2 register.
7aa9ff56
EV		 499 */
500void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
501{
502 struct omap_mcbsp *mcbsp;
7aa9ff56 503
752ec2f2 504 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
7aa9ff56
EV		 505 return;
506
507 if (!omap_mcbsp_check_valid_id(id)) {
508 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
509 return;
510 }
511 mcbsp = id_to_mcbsp_ptr(id);
7aa9ff56 512
451fd82d
PU		 513 if (threshold && threshold <= mcbsp->max_tx_thres)
514 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
7aa9ff56
EV		 515}
516EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
517
518/*
451fd82d
PU		 519 * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
520 * The threshold parameter is 1 based, and it is converted (threshold - 1)
521 * for the THRSH1 register.
7aa9ff56
EV		 522 */
523void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
524{
525 struct omap_mcbsp *mcbsp;
7aa9ff56 526
752ec2f2 527 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
7aa9ff56
EV		 528 return;
529
530 if (!omap_mcbsp_check_valid_id(id)) {
531 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
532 return;
533 }
534 mcbsp = id_to_mcbsp_ptr(id);
7aa9ff56 535
451fd82d
PU		 536 if (threshold && threshold <= mcbsp->max_rx_thres)
537 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
7aa9ff56
EV		 538}
539EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
a1a56f5f
EV		 540
541/*
542 * omap_mcbsp_get_max_tx_thres just return the current configured
543 * maximum threshold for transmission
544 */
545u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
546{
547 struct omap_mcbsp *mcbsp;
548
549 if (!omap_mcbsp_check_valid_id(id)) {
550 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
551 return -ENODEV;
552 }
553 mcbsp = id_to_mcbsp_ptr(id);
554
555 return mcbsp->max_tx_thres;
556}
557EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
558
559/*
560 * omap_mcbsp_get_max_rx_thres just return the current configured
561 * maximum threshold for reception
562 */
563u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
564{
565 struct omap_mcbsp *mcbsp;
566
567 if (!omap_mcbsp_check_valid_id(id)) {
568 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
569 return -ENODEV;
570 }
571 mcbsp = id_to_mcbsp_ptr(id);
572
573 return mcbsp->max_rx_thres;
574}
575EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
98cb20e8 576
0acce82b
PU		 577u16 omap_mcbsp_get_fifo_size(unsigned int id)
578{
579 struct omap_mcbsp *mcbsp;
580
581 if (!omap_mcbsp_check_valid_id(id)) {
582 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
583 return -ENODEV;
584 }
585 mcbsp = id_to_mcbsp_ptr(id);
586
587 return mcbsp->pdata->buffer_size;
588}
589EXPORT_SYMBOL(omap_mcbsp_get_fifo_size);
590
7dc976ed
PU		 591/*
592 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
593 */
594u16 omap_mcbsp_get_tx_delay(unsigned int id)
595{
596 struct omap_mcbsp *mcbsp;
597 u16 buffstat;
598
599 if (!omap_mcbsp_check_valid_id(id)) {
600 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
601 return -ENODEV;
602 }
603 mcbsp = id_to_mcbsp_ptr(id);
604
605 /* Returns the number of free locations in the buffer */
606 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
607
608 /* Number of slots are different in McBSP ports */
f10b8ad1 609 return mcbsp->pdata->buffer_size - buffstat;
7dc976ed
PU		 610}
611EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
612
613/*
614 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
615 * to reach the threshold value (when the DMA will be triggered to read it)
616 */
617u16 omap_mcbsp_get_rx_delay(unsigned int id)
618{
619 struct omap_mcbsp *mcbsp;
620 u16 buffstat, threshold;
621
622 if (!omap_mcbsp_check_valid_id(id)) {
623 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
624 return -ENODEV;
625 }
626 mcbsp = id_to_mcbsp_ptr(id);
627
628 /* Returns the number of used locations in the buffer */
629 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
630 /* RX threshold */
631 threshold = MCBSP_READ(mcbsp, THRSH1);
632
633 /* Return the number of location till we reach the threshold limit */
634 if (threshold <= buffstat)
635 return 0;
636 else
637 return threshold - buffstat;
638}
639EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
640
98cb20e8
PU		 641/*
642 * omap_mcbsp_get_dma_op_mode just return the current configured
643 * operating mode for the mcbsp channel
644 */
645int omap_mcbsp_get_dma_op_mode(unsigned int id)
646{
647 struct omap_mcbsp *mcbsp;
648 int dma_op_mode;
649
650 if (!omap_mcbsp_check_valid_id(id)) {
651 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
652 return -ENODEV;
653 }
654 mcbsp = id_to_mcbsp_ptr(id);
655
98cb20e8 656 dma_op_mode = mcbsp->dma_op_mode;
98cb20e8
PU		 657
658 return dma_op_mode;
659}
660EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
2122fdc6 661
2122fdc6 662#else
d912fa92
EN		 663static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
664static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
7aa9ff56
EV		 665#endif
666
5e1c5ff4
TL		 667int omap_mcbsp_request(unsigned int id)
668{
b4b58f58 669 struct omap_mcbsp *mcbsp;
c8c99699 670 void *reg_cache;
5e1c5ff4
TL		 671 int err;
672
bc5d0c89
EV		 673 if (!omap_mcbsp_check_valid_id(id)) {
674 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
675 return -ENODEV;
120db2cb 676 }
b4b58f58 677 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 678
c8c99699
JK		 679 reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
680 if (!reg_cache) {
681 return -ENOMEM;
682 }
683
b4b58f58
CS		 684 spin_lock(&mcbsp->lock);
685 if (!mcbsp->free) {
686 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
687 mcbsp->id);
c8c99699
JK		 688 err = -EBUSY;
689 goto err_kfree;
5e1c5ff4
TL		 690 }
691
6722a723 692 mcbsp->free = false;
c8c99699 693 mcbsp->reg_cache = reg_cache;
b4b58f58 694 spin_unlock(&mcbsp->lock);
5e1c5ff4 695
b820ce4e
RK		 696 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
697 mcbsp->pdata->ops->request(id);
698
e95496d4 699 pm_runtime_get_sync(mcbsp->dev);
b820ce4e 700
1a645884
JN		 701 /* Enable wakeup behavior */
702 if (mcbsp->pdata->has_wakeup)
703 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
2122fdc6 704
5a07055a
JN		 705 /*
706 * Make sure that transmitter, receiver and sample-rate generator are
707 * not running before activating IRQs.
708 */
8ea3200f
JK		 709 MCBSP_WRITE(mcbsp, SPCR1, 0);
710 MCBSP_WRITE(mcbsp, SPCR2, 0);
5a07055a 711
bafe2721
JN		 712 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
713 0, "McBSP", (void *)mcbsp);
714 if (err != 0) {
715 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
716 "for McBSP%d\n", mcbsp->tx_irq,
717 mcbsp->id);
718 goto err_clk_disable;
719 }
720
721 if (mcbsp->rx_irq) {
722 err = request_irq(mcbsp->rx_irq,
723 omap_mcbsp_rx_irq_handler,
724 0, "McBSP", (void *)mcbsp);
120db2cb 725 if (err != 0) {
bafe2721
JN		 726 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
727 "for McBSP%d\n", mcbsp->rx_irq,
b4b58f58 728 mcbsp->id);
bafe2721 729 goto err_free_irq;
120db2cb 730 }
5e1c5ff4
TL		 731 }
732
5e1c5ff4 733 return 0;
c8c99699 734err_free_irq:
1866b545 735 free_irq(mcbsp->tx_irq, (void *)mcbsp);
c8c99699 736err_clk_disable:
1866b545 737 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
c8c99699 738 mcbsp->pdata->ops->free(id);
1866b545 739
1a645884
JN		 740 /* Disable wakeup behavior */
741 if (mcbsp->pdata->has_wakeup)
742 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
1866b545 743
e95496d4 744 pm_runtime_put_sync(mcbsp->dev);
1866b545 745
c8c99699 746 spin_lock(&mcbsp->lock);
6722a723 747 mcbsp->free = true;
c8c99699
JK		 748 mcbsp->reg_cache = NULL;
749err_kfree:
750 spin_unlock(&mcbsp->lock);
751 kfree(reg_cache);
1866b545
JK		 752
753 return err;
5e1c5ff4 754}
fb78d808 755EXPORT_SYMBOL(omap_mcbsp_request);
5e1c5ff4
TL		 756
757void omap_mcbsp_free(unsigned int id)
758{
b4b58f58 759 struct omap_mcbsp *mcbsp;
c8c99699 760 void *reg_cache;
b4b58f58 761
bc5d0c89
EV		 762 if (!omap_mcbsp_check_valid_id(id)) {
763 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 764 return;
120db2cb 765 }
b4b58f58 766 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 767
b4b58f58
CS		 768 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
769 mcbsp->pdata->ops->free(id);
bc5d0c89 770
1a645884
JN		 771 /* Disable wakeup behavior */
772 if (mcbsp->pdata->has_wakeup)
773 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
2122fdc6 774
e95496d4 775 pm_runtime_put_sync(mcbsp->dev);
b820ce4e 776
bafe2721
JN		 777 if (mcbsp->rx_irq)
778 free_irq(mcbsp->rx_irq, (void *)mcbsp);
779 free_irq(mcbsp->tx_irq, (void *)mcbsp);
5e1c5ff4 780
c8c99699 781 reg_cache = mcbsp->reg_cache;
5e1c5ff4 782
c8c99699
JK		 783 spin_lock(&mcbsp->lock);
784 if (mcbsp->free)
785 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
786 else
6722a723 787 mcbsp->free = true;
c8c99699 788 mcbsp->reg_cache = NULL;
b4b58f58 789 spin_unlock(&mcbsp->lock);
c8c99699
JK		 790
791 if (reg_cache)
792 kfree(reg_cache);
5e1c5ff4 793}
fb78d808 794EXPORT_SYMBOL(omap_mcbsp_free);
5e1c5ff4
TL		 795
796/*
c12abc01
JN		 797 * Here we start the McBSP, by enabling transmitter, receiver or both.
798 * If no transmitter or receiver is active prior calling, then sample-rate
799 * generator and frame sync are started.
5e1c5ff4 800 */
c12abc01 801void omap_mcbsp_start(unsigned int id, int tx, int rx)
5e1c5ff4 802{
b4b58f58 803 struct omap_mcbsp *mcbsp;
ce3f054b 804 int enable_srg = 0;
5e1c5ff4
TL		 805 u16 w;
806
bc5d0c89
EV		 807 if (!omap_mcbsp_check_valid_id(id)) {
808 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 809 return;
bc5d0c89 810 }
b4b58f58 811 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 812
d912fa92
EN		 813 if (cpu_is_omap34xx())
814 omap_st_start(mcbsp);
815
ce3f054b
PU		 816 /* Only enable SRG, if McBSP is master */
817 w = MCBSP_READ_CACHE(mcbsp, PCR0);
818 if (w & (FSXM | FSRM | CLKXM | CLKRM))
819 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
820 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
c12abc01 821
ce3f054b 822 if (enable_srg) {
c12abc01 823 /* Start the sample generator */
96fbd745 824 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 825 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
c12abc01 826 }
5e1c5ff4
TL		 827
828 /* Enable transmitter and receiver */
d09a2afc 829 tx &= 1;
96fbd745 830 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 831 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
5e1c5ff4 832
d09a2afc 833 rx &= 1;
96fbd745 834 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
8ea3200f 835 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
5e1c5ff4 836
44a6311c
EV		 837 /*
838 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
839 * REVISIT: 100us may give enough time for two CLKSRG, however
840 * due to some unknown PM related, clock gating etc. reason it
841 * is now at 500us.
842 */
843 udelay(500);
5e1c5ff4 844
ce3f054b 845 if (enable_srg) {
c12abc01 846 /* Start frame sync */
96fbd745 847 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 848 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
c12abc01 849 }
5e1c5ff4 850
88408230 851 if (mcbsp->pdata->has_ccr) {
d09a2afc 852 /* Release the transmitter and receiver */
96fbd745 853 w = MCBSP_READ_CACHE(mcbsp, XCCR);
d09a2afc 854 w &= ~(tx ? XDISABLE : 0);
8ea3200f 855 MCBSP_WRITE(mcbsp, XCCR, w);
96fbd745 856 w = MCBSP_READ_CACHE(mcbsp, RCCR);
d09a2afc 857 w &= ~(rx ? RDISABLE : 0);
8ea3200f 858 MCBSP_WRITE(mcbsp, RCCR, w);
d09a2afc
JN		 859 }
860
5e1c5ff4
TL		 861 /* Dump McBSP Regs */
862 omap_mcbsp_dump_reg(id);
5e1c5ff4 863}
fb78d808 864EXPORT_SYMBOL(omap_mcbsp_start);
5e1c5ff4 865
c12abc01 866void omap_mcbsp_stop(unsigned int id, int tx, int rx)
5e1c5ff4 867{
b4b58f58 868 struct omap_mcbsp *mcbsp;
c12abc01 869 int idle;
5e1c5ff4
TL		 870 u16 w;
871
bc5d0c89
EV		 872 if (!omap_mcbsp_check_valid_id(id)) {
873 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 874 return;
bc5d0c89 875 }
5e1c5ff4 876
b4b58f58 877 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 878
fb78d808 879 /* Reset transmitter */
d09a2afc 880 tx &= 1;
88408230 881 if (mcbsp->pdata->has_ccr) {
96fbd745 882 w = MCBSP_READ_CACHE(mcbsp, XCCR);
d09a2afc 883 w |= (tx ? XDISABLE : 0);
8ea3200f 884 MCBSP_WRITE(mcbsp, XCCR, w);
d09a2afc 885 }
96fbd745 886 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 887 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
5e1c5ff4
TL		 888
889 /* Reset receiver */
d09a2afc 890 rx &= 1;
88408230 891 if (mcbsp->pdata->has_ccr) {
96fbd745 892 w = MCBSP_READ_CACHE(mcbsp, RCCR);
a93d4ed2 893 w |= (rx ? RDISABLE : 0);
8ea3200f 894 MCBSP_WRITE(mcbsp, RCCR, w);
d09a2afc 895 }
96fbd745 896 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
8ea3200f 897 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
5e1c5ff4 898
96fbd745
JK		 899 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
900 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
c12abc01
JN		 901
902 if (idle) {
903 /* Reset the sample rate generator */
96fbd745 904 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 905 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
c12abc01 906 }
d912fa92
EN		 907
908 if (cpu_is_omap34xx())
909 omap_st_stop(mcbsp);
5e1c5ff4 910}
fb78d808 911EXPORT_SYMBOL(omap_mcbsp_stop);
5e1c5ff4 912
69d042d1
PW		 913/*
914 * The following functions are only required on an OMAP1-only build.
915 * mach-omap2/mcbsp.c contains the real functions
916 */
917#ifndef CONFIG_ARCH_OMAP2PLUS
918int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
919{
920 WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
921 __func__);
922 return -EINVAL;
923}
924
925void omap2_mcbsp1_mux_clkr_src(u8 mux)
926{
927 WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
928 __func__);
929 return;
930}
931
932void omap2_mcbsp1_mux_fsr_src(u8 mux)
933{
934 WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
935 __func__);
936 return;
937}
938#endif
939
a8eb7ca0 940#ifdef CONFIG_ARCH_OMAP3
a1a56f5f
EV		 941#define max_thres(m) (mcbsp->pdata->buffer_size)
942#define valid_threshold(m, val) ((val) <= max_thres(m))
943#define THRESHOLD_PROP_BUILDER(prop) \
944static ssize_t prop##_show(struct device *dev, \
945 struct device_attribute *attr, char *buf) \
946{ \
947 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
948 \
949 return sprintf(buf, "%u\n", mcbsp->prop); \
950} \
951 \
952static ssize_t prop##_store(struct device *dev, \
953 struct device_attribute *attr, \
954 const char *buf, size_t size) \
955{ \
956 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
957 unsigned long val; \
958 int status; \
959 \
960 status = strict_strtoul(buf, 0, &val); \
961 if (status) \
962 return status; \
963 \
964 if (!valid_threshold(mcbsp, val)) \
965 return -EDOM; \
966 \
967 mcbsp->prop = val; \
968 return size; \
969} \
970 \
971static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
972
973THRESHOLD_PROP_BUILDER(max_tx_thres);
974THRESHOLD_PROP_BUILDER(max_rx_thres);
975
9b300509
JN		 976static const char *dma_op_modes[] = {
977 "element", "threshold", "frame",
978};
979
98cb20e8
PU		 980static ssize_t dma_op_mode_show(struct device *dev,
981 struct device_attribute *attr, char *buf)
982{
983 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
9b300509
JN		 984 int dma_op_mode, i = 0;
985 ssize_t len = 0;
986 const char * const *s;
98cb20e8 987
98cb20e8 988 dma_op_mode = mcbsp->dma_op_mode;
98cb20e8 989
9b300509
JN		 990 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
991 if (dma_op_mode == i)
992 len += sprintf(buf + len, "[%s] ", *s);
993 else
994 len += sprintf(buf + len, "%s ", *s);
995 }
996 len += sprintf(buf + len, "\n");
997
998 return len;
98cb20e8
PU		 999}
1000
1001static ssize_t dma_op_mode_store(struct device *dev,
1002 struct device_attribute *attr,
1003 const char *buf, size_t size)
1004{
1005 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
9b300509
JN		 1006 const char * const *s;
1007 int i = 0;
98cb20e8 1008
9b300509
JN		 1009 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1010 if (sysfs_streq(buf, *s))
1011 break;
98cb20e8 1012
9b300509
JN		 1013 if (i == ARRAY_SIZE(dma_op_modes))
1014 return -EINVAL;
98cb20e8 1015
9b300509 1016 spin_lock_irq(&mcbsp->lock);
98cb20e8
PU		 1017 if (!mcbsp->free) {
1018 size = -EBUSY;
1019 goto unlock;
1020 }
9b300509 1021 mcbsp->dma_op_mode = i;
98cb20e8
PU		 1022
1023unlock:
1024 spin_unlock_irq(&mcbsp->lock);
1025
1026 return size;
1027}
1028
1029static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1030
d912fa92
EN		 1031static ssize_t st_taps_show(struct device *dev,
1032 struct device_attribute *attr, char *buf)
1033{
1034 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1035 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1036 ssize_t status = 0;
1037 int i;
1038
1039 spin_lock_irq(&mcbsp->lock);
1040 for (i = 0; i < st_data->nr_taps; i++)
1041 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1042 st_data->taps[i]);
1043 if (i)
1044 status += sprintf(&buf[status], "\n");
1045 spin_unlock_irq(&mcbsp->lock);
1046
1047 return status;
1048}
1049
1050static ssize_t st_taps_store(struct device *dev,
1051 struct device_attribute *attr,
1052 const char *buf, size_t size)
1053{
1054 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1055 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1056 int val, tmp, status, i = 0;
1057
1058 spin_lock_irq(&mcbsp->lock);
1059 memset(st_data->taps, 0, sizeof(st_data->taps));
1060 st_data->nr_taps = 0;
1061
1062 do {
1063 status = sscanf(buf, "%d%n", &val, &tmp);
1064 if (status < 0 || status == 0) {
1065 size = -EINVAL;
1066 goto out;
1067 }
1068 if (val < -32768 || val > 32767) {
1069 size = -EINVAL;
1070 goto out;
1071 }
1072 st_data->taps[i++] = val;
1073 buf += tmp;
1074 if (*buf != ',')
1075 break;
1076 buf++;
1077 } while (1);
1078
1079 st_data->nr_taps = i;
1080
1081out:
1082 spin_unlock_irq(&mcbsp->lock);
1083
1084 return size;
1085}
1086
1087static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1088
4c8200ae 1089static const struct attribute *additional_attrs[] = {
a1a56f5f
EV		 1090 &dev_attr_max_tx_thres.attr,
1091 &dev_attr_max_rx_thres.attr,
98cb20e8 1092 &dev_attr_dma_op_mode.attr,
a1a56f5f
EV		 1093 NULL,
1094};
1095
4c8200ae
EV		 1096static const struct attribute_group additional_attr_group = {
1097 .attrs = (struct attribute **)additional_attrs,
a1a56f5f
EV		 1098};
1099
4c8200ae 1100static inline int __devinit omap_additional_add(struct device *dev)
a1a56f5f 1101{
4c8200ae 1102 return sysfs_create_group(&dev->kobj, &additional_attr_group);
a1a56f5f
EV		 1103}
1104
4c8200ae 1105static inline void __devexit omap_additional_remove(struct device *dev)
a1a56f5f 1106{
4c8200ae 1107 sysfs_remove_group(&dev->kobj, &additional_attr_group);
a1a56f5f
EV		 1108}
1109
d912fa92
EN		 1110static const struct attribute *sidetone_attrs[] = {
1111 &dev_attr_st_taps.attr,
1112 NULL,
1113};
1114
1115static const struct attribute_group sidetone_attr_group = {
1116 .attrs = (struct attribute **)sidetone_attrs,
1117};
1118
b0a330dc 1119static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
d912fa92 1120{
3cf32bba
KVA		 1121 struct platform_device *pdev;
1122 struct resource *res;
d912fa92
EN		 1123 struct omap_mcbsp_st_data *st_data;
1124 int err;
1125
1126 st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1127 if (!st_data) {
1128 err = -ENOMEM;
1129 goto err1;
1130 }
1131
3cf32bba
KVA		 1132 pdev = container_of(mcbsp->dev, struct platform_device, dev);
1133
1134 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1135 st_data->io_base_st = ioremap(res->start, resource_size(res));
d912fa92
EN		 1136 if (!st_data->io_base_st) {
1137 err = -ENOMEM;
1138 goto err2;
1139 }
1140
1141 err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1142 if (err)
1143 goto err3;
1144
1145 mcbsp->st_data = st_data;
1146 return 0;
1147
1148err3:
1149 iounmap(st_data->io_base_st);
1150err2:
1151 kfree(st_data);
1152err1:
1153 return err;
1154
1155}
1156
1157static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1158{
1159 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1160
1161 if (st_data) {
1162 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1163 iounmap(st_data->io_base_st);
1164 kfree(st_data);
1165 }
1166}
1167
a1a56f5f
EV		 1168static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1169{
98cb20e8 1170 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
a1a56f5f 1171 if (cpu_is_omap34xx()) {
451fd82d
PU		 1172 /*
1173 * Initially configure the maximum thresholds to a safe value.
1174 * The McBSP FIFO usage with these values should not go under
1175 * 16 locations.
1176 * If the whole FIFO without safety buffer is used, than there
1177 * is a possibility that the DMA will be not able to push the
1178 * new data on time, causing channel shifts in runtime.
1179 */
1180 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1181 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
98cb20e8
PU		 1182 /*
1183 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1184 * for mcbsp2 instances.
1185 */
4c8200ae 1186 if (omap_additional_add(mcbsp->dev))
a1a56f5f 1187 dev_warn(mcbsp->dev,
4c8200ae 1188 "Unable to create additional controls\n");
d912fa92
EN		 1189
1190 if (mcbsp->id == 2 || mcbsp->id == 3)
1191 if (omap_st_add(mcbsp))
1192 dev_warn(mcbsp->dev,
1193 "Unable to create sidetone controls\n");
1194
a1a56f5f
EV		 1195 } else {
1196 mcbsp->max_tx_thres = -EINVAL;
1197 mcbsp->max_rx_thres = -EINVAL;
1198 }
1199}
1200
1201static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1202{
d912fa92 1203 if (cpu_is_omap34xx()) {
4c8200ae 1204 omap_additional_remove(mcbsp->dev);
d912fa92
EN		 1205
1206 if (mcbsp->id == 2 || mcbsp->id == 3)
1207 omap_st_remove(mcbsp);
1208 }
a1a56f5f
EV		 1209}
1210#else
1211static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1212static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
a8eb7ca0 1213#endif /* CONFIG_ARCH_OMAP3 */
a1a56f5f 1214
5e1c5ff4
TL		 1215/*
1216 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1217 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1218 */
25cef225 1219static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
bc5d0c89
EV		 1220{
1221 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
b4b58f58 1222 struct omap_mcbsp *mcbsp;
bc5d0c89 1223 int id = pdev->id - 1;
3cf32bba 1224 struct resource *res;
bc5d0c89 1225 int ret = 0;
5e1c5ff4 1226
bc5d0c89
EV		 1227 if (!pdata) {
1228 dev_err(&pdev->dev, "McBSP device initialized without"
1229 "platform data\n");
1230 ret = -EINVAL;
1231 goto exit;
1232 }
1233
1234 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1235
b4b58f58 1236 if (id >= omap_mcbsp_count) {
bc5d0c89
EV		 1237 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1238 ret = -EINVAL;
1239 goto exit;
1240 }
1241
b4b58f58
CS		 1242 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1243 if (!mcbsp) {
1244 ret = -ENOMEM;
1245 goto exit;
1246 }
b4b58f58
CS		 1247
1248 spin_lock_init(&mcbsp->lock);
1249 mcbsp->id = id + 1;
6722a723 1250 mcbsp->free = true;
bc5d0c89 1251
3cf32bba
KVA		 1252 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1253 if (!res) {
1254 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1255 if (!res) {
1256 dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory"
1257 "resource\n", __func__, pdev->id);
1258 ret = -ENOMEM;
1259 goto exit;
1260 }
1261 }
1262 mcbsp->phys_base = res->start;
1263 omap_mcbsp_cache_size = resource_size(res);
1264 mcbsp->io_base = ioremap(res->start, resource_size(res));
b4b58f58 1265 if (!mcbsp->io_base) {
d592dd1a
RK		 1266 ret = -ENOMEM;
1267 goto err_ioremap;
1268 }
1269
3cf32bba
KVA		 1270 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
1271 if (!res)
1272 mcbsp->phys_dma_base = mcbsp->phys_base;
1273 else
1274 mcbsp->phys_dma_base = res->start;
1275
3cf32bba
KVA		 1276 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1277 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1278
cb7e9ded
KVA		 1279 /* From OMAP4 there will be a single irq line */
1280 if (mcbsp->tx_irq == -ENXIO)
1281 mcbsp->tx_irq = platform_get_irq(pdev, 0);
1282
3cf32bba
KVA		 1283 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1284 if (!res) {
1285 dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
1286 __func__, pdev->id);
1287 ret = -ENODEV;
1288 goto err_res;
1289 }
1290 mcbsp->dma_rx_sync = res->start;
1291
1292 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1293 if (!res) {
1294 dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n",
1295 __func__, pdev->id);
1296 ret = -ENODEV;
1297 goto err_res;
1298 }
1299 mcbsp->dma_tx_sync = res->start;
bc5d0c89 1300
b820ce4e
RK		 1301 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1302 if (IS_ERR(mcbsp->fclk)) {
1303 ret = PTR_ERR(mcbsp->fclk);
1304 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
e95496d4 1305 goto err_res;
bc5d0c89
EV		 1306 }
1307
b4b58f58
CS		 1308 mcbsp->pdata = pdata;
1309 mcbsp->dev = &pdev->dev;
b820ce4e 1310 mcbsp_ptr[id] = mcbsp;
b4b58f58 1311 platform_set_drvdata(pdev, mcbsp);
e95496d4 1312 pm_runtime_enable(mcbsp->dev);
a1a56f5f
EV		 1313
1314 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1315 omap34xx_device_init(mcbsp);
1316
d592dd1a 1317 return 0;
bc5d0c89 1318
3cf32bba 1319err_res:
b4b58f58 1320 iounmap(mcbsp->io_base);
d592dd1a 1321err_ioremap:
b820ce4e 1322 kfree(mcbsp);
bc5d0c89
EV		 1323exit:
1324 return ret;
1325}
120db2cb 1326
25cef225 1327static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
5e1c5ff4 1328{
bc5d0c89 1329 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
5e1c5ff4 1330
bc5d0c89
EV		 1331 platform_set_drvdata(pdev, NULL);
1332 if (mcbsp) {
5e1c5ff4 1333
bc5d0c89
EV		 1334 if (mcbsp->pdata && mcbsp->pdata->ops &&
1335 mcbsp->pdata->ops->free)
1336 mcbsp->pdata->ops->free(mcbsp->id);
5e1c5ff4 1337
a1a56f5f
EV		 1338 omap34xx_device_exit(mcbsp);
1339
b820ce4e 1340 clk_put(mcbsp->fclk);
bc5d0c89 1341
d592dd1a 1342 iounmap(mcbsp->io_base);
5f3b7284 1343 kfree(mcbsp);
5e1c5ff4
TL		 1344 }
1345
1346 return 0;
1347}
1348
bc5d0c89
EV		 1349static struct platform_driver omap_mcbsp_driver = {
1350 .probe = omap_mcbsp_probe,
25cef225 1351 .remove = __devexit_p(omap_mcbsp_remove),
bc5d0c89
EV		 1352 .driver = {
1353 .name = "omap-mcbsp",
1354 },
1355};
1356
1357int __init omap_mcbsp_init(void)
1358{
1359 /* Register the McBSP driver */
1360 return platform_driver_register(&omap_mcbsp_driver);
1361}
Linux kernel - Deliverables
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