projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ARM: McBSP: Fix request for irq in OMAP4
[deliverable/linux.git] / arch / arm / plat-omap / mcbsp.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/mcbsp.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Multichannel mode not supported.
13 */
14
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/device.h>
bc5d0c89 18#include <linux/platform_device.h>
5e1c5ff4
TL		 19#include <linux/wait.h>
20#include <linux/completion.h>
21#include <linux/interrupt.h>
22#include <linux/err.h>
f8ce2547 23#include <linux/clk.h>
04fbf6a2 24#include <linux/delay.h>
fb78d808 25#include <linux/io.h>
5e1c5ff4 26
ce491cf8
TL		 27#include <plat/dma.h>
28#include <plat/mcbsp.h>
5e1c5ff4 29
d912fa92
EN		 30#include "../mach-omap2/cm-regbits-34xx.h"
31
b4b58f58 32struct omap_mcbsp **mcbsp_ptr;
c8c99699 33int omap_mcbsp_count, omap_mcbsp_cache_size;
bc5d0c89 34
8ea3200f 35void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
b4b58f58 36{
c8c99699
JK		 37 if (cpu_class_is_omap1()) {
38 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
8ea3200f 39 __raw_writew((u16)val, mcbsp->io_base + reg);
c8c99699
JK		 40 } else if (cpu_is_omap2420()) {
41 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
42 __raw_writew((u16)val, mcbsp->io_base + reg);
43 } else {
44 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
8ea3200f 45 __raw_writel(val, mcbsp->io_base + reg);
c8c99699 46 }
b4b58f58
CS		 47}
48
c8c99699 49int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
b4b58f58 50{
c8c99699
JK		 51 if (cpu_class_is_omap1()) {
52 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
53 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
54 } else if (cpu_is_omap2420()) {
55 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
56 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
57 } else {
58 return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
59 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
60 }
b4b58f58
CS		 61}
62
d912fa92
EN		 63#ifdef CONFIG_ARCH_OMAP3
64void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
65{
66 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
67}
68
69int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
70{
71 return __raw_readl(mcbsp->st_data->io_base_st + reg);
72}
73#endif
74
8ea3200f 75#define MCBSP_READ(mcbsp, reg) \
c8c99699 76 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
8ea3200f
JK		 77#define MCBSP_WRITE(mcbsp, reg, val) \
78 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
c8c99699
JK		 79#define MCBSP_READ_CACHE(mcbsp, reg) \
80 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
b4b58f58
CS		 81
82#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
83#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
5e1c5ff4 84
d912fa92
EN		 85#define MCBSP_ST_READ(mcbsp, reg) \
86 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
87#define MCBSP_ST_WRITE(mcbsp, reg, val) \
88 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
89
5e1c5ff4
TL		 90static void omap_mcbsp_dump_reg(u8 id)
91{
b4b58f58
CS		 92 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
93
94 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
95 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
8ea3200f 96 MCBSP_READ(mcbsp, DRR2));
b4b58f58 97 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
8ea3200f 98 MCBSP_READ(mcbsp, DRR1));
b4b58f58 99 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
8ea3200f 100 MCBSP_READ(mcbsp, DXR2));
b4b58f58 101 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
8ea3200f 102 MCBSP_READ(mcbsp, DXR1));
b4b58f58 103 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
8ea3200f 104 MCBSP_READ(mcbsp, SPCR2));
b4b58f58 105 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
8ea3200f 106 MCBSP_READ(mcbsp, SPCR1));
b4b58f58 107 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
8ea3200f 108 MCBSP_READ(mcbsp, RCR2));
b4b58f58 109 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
8ea3200f 110 MCBSP_READ(mcbsp, RCR1));
b4b58f58 111 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
8ea3200f 112 MCBSP_READ(mcbsp, XCR2));
b4b58f58 113 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
8ea3200f 114 MCBSP_READ(mcbsp, XCR1));
b4b58f58 115 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
8ea3200f 116 MCBSP_READ(mcbsp, SRGR2));
b4b58f58 117 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
8ea3200f 118 MCBSP_READ(mcbsp, SRGR1));
b4b58f58 119 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
8ea3200f 120 MCBSP_READ(mcbsp, PCR0));
b4b58f58 121 dev_dbg(mcbsp->dev, "***********************\n");
5e1c5ff4
TL		 122}
123
0cd61b68 124static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
5e1c5ff4 125{
e8f2af17 126 struct omap_mcbsp *mcbsp_tx = dev_id;
d6d834b0 127 u16 irqst_spcr2;
5e1c5ff4 128
8ea3200f 129 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
d6d834b0 130 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
5e1c5ff4 131
d6d834b0
EN		 132 if (irqst_spcr2 & XSYNC_ERR) {
133 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
134 irqst_spcr2);
135 /* Writing zero to XSYNC_ERR clears the IRQ */
0841cb82 136 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
d6d834b0
EN		 137 } else {
138 complete(&mcbsp_tx->tx_irq_completion);
139 }
fb78d808 140
5e1c5ff4
TL		 141 return IRQ_HANDLED;
142}
143
0cd61b68 144static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
5e1c5ff4 145{
e8f2af17 146 struct omap_mcbsp *mcbsp_rx = dev_id;
d6d834b0
EN		 147 u16 irqst_spcr1;
148
8ea3200f 149 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
d6d834b0
EN		 150 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
151
152 if (irqst_spcr1 & RSYNC_ERR) {
153 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
154 irqst_spcr1);
155 /* Writing zero to RSYNC_ERR clears the IRQ */
0841cb82 156 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
d6d834b0
EN		 157 } else {
158 complete(&mcbsp_rx->tx_irq_completion);
159 }
fb78d808 160
5e1c5ff4
TL		 161 return IRQ_HANDLED;
162}
163
5e1c5ff4
TL		 164static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
165{
e8f2af17 166 struct omap_mcbsp *mcbsp_dma_tx = data;
5e1c5ff4 167
bc5d0c89 168 dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
8ea3200f 169 MCBSP_READ(mcbsp_dma_tx, SPCR2));
5e1c5ff4
TL		 170
171 /* We can free the channels */
172 omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
173 mcbsp_dma_tx->dma_tx_lch = -1;
174
175 complete(&mcbsp_dma_tx->tx_dma_completion);
176}
177
178static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
179{
e8f2af17 180 struct omap_mcbsp *mcbsp_dma_rx = data;
5e1c5ff4 181
bc5d0c89 182 dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
8ea3200f 183 MCBSP_READ(mcbsp_dma_rx, SPCR2));
5e1c5ff4
TL		 184
185 /* We can free the channels */
186 omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
187 mcbsp_dma_rx->dma_rx_lch = -1;
188
189 complete(&mcbsp_dma_rx->rx_dma_completion);
190}
191
5e1c5ff4
TL		 192/*
193 * omap_mcbsp_config simply write a config to the
194 * appropriate McBSP.
195 * You either call this function or set the McBSP registers
196 * by yourself before calling omap_mcbsp_start().
197 */
fb78d808 198void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
5e1c5ff4 199{
b4b58f58 200 struct omap_mcbsp *mcbsp;
5e1c5ff4 201
bc5d0c89
EV		 202 if (!omap_mcbsp_check_valid_id(id)) {
203 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
204 return;
205 }
b4b58f58 206 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 207
b4b58f58
CS		 208 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
209 mcbsp->id, mcbsp->phys_base);
5e1c5ff4
TL		 210
211 /* We write the given config */
8ea3200f
JK		 212 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
213 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
214 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
215 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
216 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
217 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
218 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
219 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
220 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
221 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
222 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
a5b92cc3 223 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
8ea3200f
JK		 224 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
225 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
3127f8f8 226 }
5e1c5ff4 227}
fb78d808 228EXPORT_SYMBOL(omap_mcbsp_config);
5e1c5ff4 229
a8eb7ca0 230#ifdef CONFIG_ARCH_OMAP3
d912fa92
EN		 231static void omap_st_on(struct omap_mcbsp *mcbsp)
232{
233 unsigned int w;
234
235 /*
236 * Sidetone uses McBSP ICLK - which must not idle when sidetones
237 * are enabled or sidetones start sounding ugly.
238 */
239 w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
240 w &= ~(1 << (mcbsp->id - 2));
241 cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
242
243 /* Enable McBSP Sidetone */
244 w = MCBSP_READ(mcbsp, SSELCR);
245 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
246
247 w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
248 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
249
250 /* Enable Sidetone from Sidetone Core */
251 w = MCBSP_ST_READ(mcbsp, SSELCR);
252 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
253}
254
255static void omap_st_off(struct omap_mcbsp *mcbsp)
256{
257 unsigned int w;
258
259 w = MCBSP_ST_READ(mcbsp, SSELCR);
260 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
261
262 w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
263 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE);
264
265 w = MCBSP_READ(mcbsp, SSELCR);
266 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
267
268 w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
269 w |= 1 << (mcbsp->id - 2);
270 cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
271}
272
273static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
274{
275 u16 val, i;
276
277 val = MCBSP_ST_READ(mcbsp, SYSCONFIG);
278 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, val & ~(ST_AUTOIDLE));
279
280 val = MCBSP_ST_READ(mcbsp, SSELCR);
281
282 if (val & ST_COEFFWREN)
283 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
284
285 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
286
287 for (i = 0; i < 128; i++)
288 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
289
290 i = 0;
291
292 val = MCBSP_ST_READ(mcbsp, SSELCR);
293 while (!(val & ST_COEFFWRDONE) && (++i < 1000))
294 val = MCBSP_ST_READ(mcbsp, SSELCR);
295
296 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
297
298 if (i == 1000)
299 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
300}
301
302static void omap_st_chgain(struct omap_mcbsp *mcbsp)
303{
304 u16 w;
305 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
306
307 w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
308 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
309
310 w = MCBSP_ST_READ(mcbsp, SSELCR);
311
312 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
313 ST_CH1GAIN(st_data->ch1gain));
314}
315
316int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
317{
318 struct omap_mcbsp *mcbsp;
319 struct omap_mcbsp_st_data *st_data;
320 int ret = 0;
321
322 if (!omap_mcbsp_check_valid_id(id)) {
323 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
324 return -ENODEV;
325 }
326
327 mcbsp = id_to_mcbsp_ptr(id);
328 st_data = mcbsp->st_data;
329
330 if (!st_data)
331 return -ENOENT;
332
333 spin_lock_irq(&mcbsp->lock);
334 if (channel == 0)
335 st_data->ch0gain = chgain;
336 else if (channel == 1)
337 st_data->ch1gain = chgain;
338 else
339 ret = -EINVAL;
340
341 if (st_data->enabled)
342 omap_st_chgain(mcbsp);
343 spin_unlock_irq(&mcbsp->lock);
344
345 return ret;
346}
347EXPORT_SYMBOL(omap_st_set_chgain);
348
349int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
350{
351 struct omap_mcbsp *mcbsp;
352 struct omap_mcbsp_st_data *st_data;
353 int ret = 0;
354
355 if (!omap_mcbsp_check_valid_id(id)) {
356 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
357 return -ENODEV;
358 }
359
360 mcbsp = id_to_mcbsp_ptr(id);
361 st_data = mcbsp->st_data;
362
363 if (!st_data)
364 return -ENOENT;
365
366 spin_lock_irq(&mcbsp->lock);
367 if (channel == 0)
368 *chgain = st_data->ch0gain;
369 else if (channel == 1)
370 *chgain = st_data->ch1gain;
371 else
372 ret = -EINVAL;
373 spin_unlock_irq(&mcbsp->lock);
374
375 return ret;
376}
377EXPORT_SYMBOL(omap_st_get_chgain);
378
379static int omap_st_start(struct omap_mcbsp *mcbsp)
380{
381 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
382
383 if (st_data && st_data->enabled && !st_data->running) {
384 omap_st_fir_write(mcbsp, st_data->taps);
385 omap_st_chgain(mcbsp);
386
387 if (!mcbsp->free) {
388 omap_st_on(mcbsp);
389 st_data->running = 1;
390 }
391 }
392
393 return 0;
394}
395
396int omap_st_enable(unsigned int id)
397{
398 struct omap_mcbsp *mcbsp;
399 struct omap_mcbsp_st_data *st_data;
400
401 if (!omap_mcbsp_check_valid_id(id)) {
402 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
403 return -ENODEV;
404 }
405
406 mcbsp = id_to_mcbsp_ptr(id);
407 st_data = mcbsp->st_data;
408
409 if (!st_data)
410 return -ENODEV;
411
412 spin_lock_irq(&mcbsp->lock);
413 st_data->enabled = 1;
414 omap_st_start(mcbsp);
415 spin_unlock_irq(&mcbsp->lock);
416
417 return 0;
418}
419EXPORT_SYMBOL(omap_st_enable);
420
421static int omap_st_stop(struct omap_mcbsp *mcbsp)
422{
423 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
424
425 if (st_data && st_data->running) {
426 if (!mcbsp->free) {
427 omap_st_off(mcbsp);
428 st_data->running = 0;
429 }
430 }
431
432 return 0;
433}
434
435int omap_st_disable(unsigned int id)
436{
437 struct omap_mcbsp *mcbsp;
438 struct omap_mcbsp_st_data *st_data;
439 int ret = 0;
440
441 if (!omap_mcbsp_check_valid_id(id)) {
442 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
443 return -ENODEV;
444 }
445
446 mcbsp = id_to_mcbsp_ptr(id);
447 st_data = mcbsp->st_data;
448
449 if (!st_data)
450 return -ENODEV;
451
452 spin_lock_irq(&mcbsp->lock);
453 omap_st_stop(mcbsp);
454 st_data->enabled = 0;
455 spin_unlock_irq(&mcbsp->lock);
456
457 return ret;
458}
459EXPORT_SYMBOL(omap_st_disable);
460
461int omap_st_is_enabled(unsigned int id)
462{
463 struct omap_mcbsp *mcbsp;
464 struct omap_mcbsp_st_data *st_data;
465
466 if (!omap_mcbsp_check_valid_id(id)) {
467 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
468 return -ENODEV;
469 }
470
471 mcbsp = id_to_mcbsp_ptr(id);
472 st_data = mcbsp->st_data;
473
474 if (!st_data)
475 return -ENODEV;
476
477
478 return st_data->enabled;
479}
480EXPORT_SYMBOL(omap_st_is_enabled);
481
7aa9ff56
EV		 482/*
483 * omap_mcbsp_set_tx_threshold configures how to deal
484 * with transmit threshold. the threshold value and handler can be
485 * configure in here.
486 */
487void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
488{
489 struct omap_mcbsp *mcbsp;
7aa9ff56
EV		 490
491 if (!cpu_is_omap34xx())
492 return;
493
494 if (!omap_mcbsp_check_valid_id(id)) {
495 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
496 return;
497 }
498 mcbsp = id_to_mcbsp_ptr(id);
7aa9ff56 499
8ea3200f 500 MCBSP_WRITE(mcbsp, THRSH2, threshold);
7aa9ff56
EV		 501}
502EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
503
504/*
505 * omap_mcbsp_set_rx_threshold configures how to deal
506 * with receive threshold. the threshold value and handler can be
507 * configure in here.
508 */
509void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
510{
511 struct omap_mcbsp *mcbsp;
7aa9ff56
EV		 512
513 if (!cpu_is_omap34xx())
514 return;
515
516 if (!omap_mcbsp_check_valid_id(id)) {
517 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
518 return;
519 }
520 mcbsp = id_to_mcbsp_ptr(id);
7aa9ff56 521
8ea3200f 522 MCBSP_WRITE(mcbsp, THRSH1, threshold);
7aa9ff56
EV		 523}
524EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
a1a56f5f
EV		 525
526/*
527 * omap_mcbsp_get_max_tx_thres just return the current configured
528 * maximum threshold for transmission
529 */
530u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
531{
532 struct omap_mcbsp *mcbsp;
533
534 if (!omap_mcbsp_check_valid_id(id)) {
535 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
536 return -ENODEV;
537 }
538 mcbsp = id_to_mcbsp_ptr(id);
539
540 return mcbsp->max_tx_thres;
541}
542EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
543
544/*
545 * omap_mcbsp_get_max_rx_thres just return the current configured
546 * maximum threshold for reception
547 */
548u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
549{
550 struct omap_mcbsp *mcbsp;
551
552 if (!omap_mcbsp_check_valid_id(id)) {
553 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
554 return -ENODEV;
555 }
556 mcbsp = id_to_mcbsp_ptr(id);
557
558 return mcbsp->max_rx_thres;
559}
560EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
98cb20e8 561
7dc976ed
PU		 562#define MCBSP2_FIFO_SIZE 0x500 /* 1024 + 256 locations */
563#define MCBSP1345_FIFO_SIZE 0x80 /* 128 locations */
564/*
565 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
566 */
567u16 omap_mcbsp_get_tx_delay(unsigned int id)
568{
569 struct omap_mcbsp *mcbsp;
570 u16 buffstat;
571
572 if (!omap_mcbsp_check_valid_id(id)) {
573 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
574 return -ENODEV;
575 }
576 mcbsp = id_to_mcbsp_ptr(id);
577
578 /* Returns the number of free locations in the buffer */
579 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
580
581 /* Number of slots are different in McBSP ports */
582 if (mcbsp->id == 2)
583 return MCBSP2_FIFO_SIZE - buffstat;
584 else
585 return MCBSP1345_FIFO_SIZE - buffstat;
586}
587EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
588
589/*
590 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
591 * to reach the threshold value (when the DMA will be triggered to read it)
592 */
593u16 omap_mcbsp_get_rx_delay(unsigned int id)
594{
595 struct omap_mcbsp *mcbsp;
596 u16 buffstat, threshold;
597
598 if (!omap_mcbsp_check_valid_id(id)) {
599 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
600 return -ENODEV;
601 }
602 mcbsp = id_to_mcbsp_ptr(id);
603
604 /* Returns the number of used locations in the buffer */
605 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
606 /* RX threshold */
607 threshold = MCBSP_READ(mcbsp, THRSH1);
608
609 /* Return the number of location till we reach the threshold limit */
610 if (threshold <= buffstat)
611 return 0;
612 else
613 return threshold - buffstat;
614}
615EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
616
98cb20e8
PU		 617/*
618 * omap_mcbsp_get_dma_op_mode just return the current configured
619 * operating mode for the mcbsp channel
620 */
621int omap_mcbsp_get_dma_op_mode(unsigned int id)
622{
623 struct omap_mcbsp *mcbsp;
624 int dma_op_mode;
625
626 if (!omap_mcbsp_check_valid_id(id)) {
627 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
628 return -ENODEV;
629 }
630 mcbsp = id_to_mcbsp_ptr(id);
631
98cb20e8 632 dma_op_mode = mcbsp->dma_op_mode;
98cb20e8
PU		 633
634 return dma_op_mode;
635}
636EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
2122fdc6
EN		 637
638static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
639{
640 /*
641 * Enable wakup behavior, smart idle and all wakeups
642 * REVISIT: some wakeups may be unnecessary
643 */
644 if (cpu_is_omap34xx()) {
645 u16 syscon;
646
8ea3200f 647 syscon = MCBSP_READ(mcbsp, SYSCON);
2ba93f8f 648 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
d99a7454 649
fa3935ba
EN		 650 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
651 syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
652 CLOCKACTIVITY(0x02));
8ea3200f 653 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
fa3935ba 654 } else {
d99a7454 655 syscon |= SIDLEMODE(0x01);
fa3935ba 656 }
d99a7454 657
8ea3200f 658 MCBSP_WRITE(mcbsp, SYSCON, syscon);
2122fdc6
EN		 659 }
660}
661
662static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
663{
664 /*
665 * Disable wakup behavior, smart idle and all wakeups
666 */
667 if (cpu_is_omap34xx()) {
668 u16 syscon;
2122fdc6 669
8ea3200f 670 syscon = MCBSP_READ(mcbsp, SYSCON);
2ba93f8f 671 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
72cc6d71
EN		 672 /*
673 * HW bug workaround - If no_idle mode is taken, we need to
674 * go to smart_idle before going to always_idle, or the
675 * device will not hit retention anymore.
676 */
677 syscon |= SIDLEMODE(0x02);
8ea3200f 678 MCBSP_WRITE(mcbsp, SYSCON, syscon);
72cc6d71
EN		 679
680 syscon &= ~(SIDLEMODE(0x03));
8ea3200f 681 MCBSP_WRITE(mcbsp, SYSCON, syscon);
2122fdc6 682
8ea3200f 683 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
2122fdc6
EN		 684 }
685}
686#else
687static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
688static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
d912fa92
EN		 689static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
690static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
7aa9ff56
EV		 691#endif
692
120db2cb
TL		 693/*
694 * We can choose between IRQ based or polled IO.
695 * This needs to be called before omap_mcbsp_request().
696 */
697int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
698{
b4b58f58
CS		 699 struct omap_mcbsp *mcbsp;
700
bc5d0c89
EV		 701 if (!omap_mcbsp_check_valid_id(id)) {
702 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
703 return -ENODEV;
704 }
b4b58f58 705 mcbsp = id_to_mcbsp_ptr(id);
120db2cb 706
b4b58f58 707 spin_lock(&mcbsp->lock);
120db2cb 708
b4b58f58
CS		 709 if (!mcbsp->free) {
710 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
711 mcbsp->id);
712 spin_unlock(&mcbsp->lock);
120db2cb
TL		 713 return -EINVAL;
714 }
715
b4b58f58 716 mcbsp->io_type = io_type;
120db2cb 717
b4b58f58 718 spin_unlock(&mcbsp->lock);
120db2cb
TL		 719
720 return 0;
721}
fb78d808 722EXPORT_SYMBOL(omap_mcbsp_set_io_type);
5e1c5ff4 723
5e1c5ff4
TL		 724int omap_mcbsp_request(unsigned int id)
725{
b4b58f58 726 struct omap_mcbsp *mcbsp;
c8c99699 727 void *reg_cache;
5e1c5ff4
TL		 728 int err;
729
bc5d0c89
EV		 730 if (!omap_mcbsp_check_valid_id(id)) {
731 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
732 return -ENODEV;
120db2cb 733 }
b4b58f58 734 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 735
c8c99699
JK		 736 reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
737 if (!reg_cache) {
738 return -ENOMEM;
739 }
740
b4b58f58
CS		 741 spin_lock(&mcbsp->lock);
742 if (!mcbsp->free) {
743 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
744 mcbsp->id);
c8c99699
JK		 745 err = -EBUSY;
746 goto err_kfree;
5e1c5ff4
TL		 747 }
748
b4b58f58 749 mcbsp->free = 0;
c8c99699 750 mcbsp->reg_cache = reg_cache;
b4b58f58 751 spin_unlock(&mcbsp->lock);
5e1c5ff4 752
b820ce4e
RK		 753 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
754 mcbsp->pdata->ops->request(id);
755
756 clk_enable(mcbsp->iclk);
757 clk_enable(mcbsp->fclk);
758
2122fdc6
EN		 759 /* Do procedure specific to omap34xx arch, if applicable */
760 omap34xx_mcbsp_request(mcbsp);
761
5a07055a
JN		 762 /*
763 * Make sure that transmitter, receiver and sample-rate generator are
764 * not running before activating IRQs.
765 */
8ea3200f
JK		 766 MCBSP_WRITE(mcbsp, SPCR1, 0);
767 MCBSP_WRITE(mcbsp, SPCR2, 0);
5a07055a 768
b4b58f58 769 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
120db2cb 770 /* We need to get IRQs here */
5a07055a 771 init_completion(&mcbsp->tx_irq_completion);
b4b58f58
CS		 772 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
773 0, "McBSP", (void *)mcbsp);
120db2cb 774 if (err != 0) {
b4b58f58
CS		 775 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
776 "for McBSP%d\n", mcbsp->tx_irq,
777 mcbsp->id);
c8c99699 778 goto err_clk_disable;
120db2cb 779 }
5e1c5ff4 780
9319b9da
JEC		 781 if (mcbsp->rx_irq) {
782 init_completion(&mcbsp->rx_irq_completion);
783 err = request_irq(mcbsp->rx_irq,
784 omap_mcbsp_rx_irq_handler,
b4b58f58 785 0, "McBSP", (void *)mcbsp);
9319b9da
JEC		 786 if (err != 0) {
787 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
788 "for McBSP%d\n", mcbsp->rx_irq,
789 mcbsp->id);
790 goto err_free_irq;
791 }
120db2cb 792 }
5e1c5ff4
TL		 793 }
794
5e1c5ff4 795 return 0;
c8c99699 796err_free_irq:
1866b545 797 free_irq(mcbsp->tx_irq, (void *)mcbsp);
c8c99699 798err_clk_disable:
1866b545 799 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
c8c99699 800 mcbsp->pdata->ops->free(id);
1866b545
JK		 801
802 /* Do procedure specific to omap34xx arch, if applicable */
803 omap34xx_mcbsp_free(mcbsp);
804
805 clk_disable(mcbsp->fclk);
806 clk_disable(mcbsp->iclk);
807
c8c99699 808 spin_lock(&mcbsp->lock);
1866b545 809 mcbsp->free = 1;
c8c99699
JK		 810 mcbsp->reg_cache = NULL;
811err_kfree:
812 spin_unlock(&mcbsp->lock);
813 kfree(reg_cache);
1866b545
JK		 814
815 return err;
5e1c5ff4 816}
fb78d808 817EXPORT_SYMBOL(omap_mcbsp_request);
5e1c5ff4
TL		 818
819void omap_mcbsp_free(unsigned int id)
820{
b4b58f58 821 struct omap_mcbsp *mcbsp;
c8c99699 822 void *reg_cache;
b4b58f58 823
bc5d0c89
EV		 824 if (!omap_mcbsp_check_valid_id(id)) {
825 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 826 return;
120db2cb 827 }
b4b58f58 828 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 829
b4b58f58
CS		 830 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
831 mcbsp->pdata->ops->free(id);
bc5d0c89 832
2122fdc6
EN		 833 /* Do procedure specific to omap34xx arch, if applicable */
834 omap34xx_mcbsp_free(mcbsp);
835
b820ce4e
RK		 836 clk_disable(mcbsp->fclk);
837 clk_disable(mcbsp->iclk);
838
839 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
840 /* Free IRQs */
9319b9da
JEC		 841 if (mcbsp->rx_irq)
842 free_irq(mcbsp->rx_irq, (void *)mcbsp);
b820ce4e
RK		 843 free_irq(mcbsp->tx_irq, (void *)mcbsp);
844 }
5e1c5ff4 845
c8c99699 846 reg_cache = mcbsp->reg_cache;
5e1c5ff4 847
c8c99699
JK		 848 spin_lock(&mcbsp->lock);
849 if (mcbsp->free)
850 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
851 else
852 mcbsp->free = 1;
853 mcbsp->reg_cache = NULL;
b4b58f58 854 spin_unlock(&mcbsp->lock);
c8c99699
JK		 855
856 if (reg_cache)
857 kfree(reg_cache);
5e1c5ff4 858}
fb78d808 859EXPORT_SYMBOL(omap_mcbsp_free);
5e1c5ff4
TL		 860
861/*
c12abc01
JN		 862 * Here we start the McBSP, by enabling transmitter, receiver or both.
863 * If no transmitter or receiver is active prior calling, then sample-rate
864 * generator and frame sync are started.
5e1c5ff4 865 */
c12abc01 866void omap_mcbsp_start(unsigned int id, int tx, int rx)
5e1c5ff4 867{
b4b58f58 868 struct omap_mcbsp *mcbsp;
c12abc01 869 int idle;
5e1c5ff4
TL		 870 u16 w;
871
bc5d0c89
EV		 872 if (!omap_mcbsp_check_valid_id(id)) {
873 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 874 return;
bc5d0c89 875 }
b4b58f58 876 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 877
d912fa92
EN		 878 if (cpu_is_omap34xx())
879 omap_st_start(mcbsp);
880
96fbd745
JK		 881 mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
882 mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
5e1c5ff4 883
96fbd745
JK		 884 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
885 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
c12abc01
JN		 886
887 if (idle) {
888 /* Start the sample generator */
96fbd745 889 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 890 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
c12abc01 891 }
5e1c5ff4
TL		 892
893 /* Enable transmitter and receiver */
d09a2afc 894 tx &= 1;
96fbd745 895 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 896 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
5e1c5ff4 897
d09a2afc 898 rx &= 1;
96fbd745 899 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
8ea3200f 900 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
5e1c5ff4 901
44a6311c
EV		 902 /*
903 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
904 * REVISIT: 100us may give enough time for two CLKSRG, however
905 * due to some unknown PM related, clock gating etc. reason it
906 * is now at 500us.
907 */
908 udelay(500);
5e1c5ff4 909
c12abc01
JN		 910 if (idle) {
911 /* Start frame sync */
96fbd745 912 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 913 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
c12abc01 914 }
5e1c5ff4 915
d09a2afc
JN		 916 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
917 /* Release the transmitter and receiver */
96fbd745 918 w = MCBSP_READ_CACHE(mcbsp, XCCR);
d09a2afc 919 w &= ~(tx ? XDISABLE : 0);
8ea3200f 920 MCBSP_WRITE(mcbsp, XCCR, w);
96fbd745 921 w = MCBSP_READ_CACHE(mcbsp, RCCR);
d09a2afc 922 w &= ~(rx ? RDISABLE : 0);
8ea3200f 923 MCBSP_WRITE(mcbsp, RCCR, w);
d09a2afc
JN		 924 }
925
5e1c5ff4
TL		 926 /* Dump McBSP Regs */
927 omap_mcbsp_dump_reg(id);
5e1c5ff4 928}
fb78d808 929EXPORT_SYMBOL(omap_mcbsp_start);
5e1c5ff4 930
c12abc01 931void omap_mcbsp_stop(unsigned int id, int tx, int rx)
5e1c5ff4 932{
b4b58f58 933 struct omap_mcbsp *mcbsp;
c12abc01 934 int idle;
5e1c5ff4
TL		 935 u16 w;
936
bc5d0c89
EV		 937 if (!omap_mcbsp_check_valid_id(id)) {
938 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 939 return;
bc5d0c89 940 }
5e1c5ff4 941
b4b58f58 942 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 943
fb78d808 944 /* Reset transmitter */
d09a2afc
JN		 945 tx &= 1;
946 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
96fbd745 947 w = MCBSP_READ_CACHE(mcbsp, XCCR);
d09a2afc 948 w |= (tx ? XDISABLE : 0);
8ea3200f 949 MCBSP_WRITE(mcbsp, XCCR, w);
d09a2afc 950 }
96fbd745 951 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 952 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
5e1c5ff4
TL		 953
954 /* Reset receiver */
d09a2afc
JN		 955 rx &= 1;
956 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
96fbd745 957 w = MCBSP_READ_CACHE(mcbsp, RCCR);
a93d4ed2 958 w |= (rx ? RDISABLE : 0);
8ea3200f 959 MCBSP_WRITE(mcbsp, RCCR, w);
d09a2afc 960 }
96fbd745 961 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
8ea3200f 962 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
5e1c5ff4 963
96fbd745
JK		 964 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
965 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
c12abc01
JN		 966
967 if (idle) {
968 /* Reset the sample rate generator */
96fbd745 969 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 970 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
c12abc01 971 }
d912fa92
EN		 972
973 if (cpu_is_omap34xx())
974 omap_st_stop(mcbsp);
5e1c5ff4 975}
fb78d808 976EXPORT_SYMBOL(omap_mcbsp_stop);
5e1c5ff4 977
bb13b5fd
TL		 978/* polled mcbsp i/o operations */
979int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
980{
b4b58f58 981 struct omap_mcbsp *mcbsp;
bc5d0c89
EV		 982
983 if (!omap_mcbsp_check_valid_id(id)) {
984 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
985 return -ENODEV;
986 }
987
b4b58f58 988 mcbsp = id_to_mcbsp_ptr(id);
b4b58f58 989
8ea3200f 990 MCBSP_WRITE(mcbsp, DXR1, buf);
bb13b5fd 991 /* if frame sync error - clear the error */
8ea3200f 992 if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
bb13b5fd 993 /* clear error */
0841cb82 994 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
bb13b5fd
TL		 995 /* resend */
996 return -1;
997 } else {
998 /* wait for transmit confirmation */
999 int attemps = 0;
8ea3200f 1000 while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
bb13b5fd 1001 if (attemps++ > 1000) {
8ea3200f 1002 MCBSP_WRITE(mcbsp, SPCR2,
96fbd745
JK		 1003 MCBSP_READ_CACHE(mcbsp, SPCR2) &
1004 (~XRST));
bb13b5fd 1005 udelay(10);
8ea3200f 1006 MCBSP_WRITE(mcbsp, SPCR2,
96fbd745
JK		 1007 MCBSP_READ_CACHE(mcbsp, SPCR2) |
1008 (XRST));
bb13b5fd 1009 udelay(10);
b4b58f58
CS		 1010 dev_err(mcbsp->dev, "Could not write to"
1011 " McBSP%d Register\n", mcbsp->id);
bb13b5fd
TL		 1012 return -2;
1013 }
1014 }
1015 }
fb78d808 1016
bb13b5fd
TL		 1017 return 0;
1018}
fb78d808 1019EXPORT_SYMBOL(omap_mcbsp_pollwrite);
bb13b5fd 1020
fb78d808 1021int omap_mcbsp_pollread(unsigned int id, u16 *buf)
bb13b5fd 1022{
b4b58f58 1023 struct omap_mcbsp *mcbsp;
bc5d0c89
EV		 1024
1025 if (!omap_mcbsp_check_valid_id(id)) {
1026 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1027 return -ENODEV;
1028 }
b4b58f58 1029 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 1030
bb13b5fd 1031 /* if frame sync error - clear the error */
8ea3200f 1032 if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
bb13b5fd 1033 /* clear error */
0841cb82 1034 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
bb13b5fd
TL		 1035 /* resend */
1036 return -1;
1037 } else {
1038 /* wait for recieve confirmation */
1039 int attemps = 0;
8ea3200f 1040 while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
bb13b5fd 1041 if (attemps++ > 1000) {
8ea3200f 1042 MCBSP_WRITE(mcbsp, SPCR1,
96fbd745
JK		 1043 MCBSP_READ_CACHE(mcbsp, SPCR1) &
1044 (~RRST));
bb13b5fd 1045 udelay(10);
8ea3200f 1046 MCBSP_WRITE(mcbsp, SPCR1,
96fbd745
JK		 1047 MCBSP_READ_CACHE(mcbsp, SPCR1) |
1048 (RRST));
bb13b5fd 1049 udelay(10);
b4b58f58
CS		 1050 dev_err(mcbsp->dev, "Could not read from"
1051 " McBSP%d Register\n", mcbsp->id);
bb13b5fd
TL		 1052 return -2;
1053 }
1054 }
1055 }
8ea3200f 1056 *buf = MCBSP_READ(mcbsp, DRR1);
fb78d808 1057
bb13b5fd
TL		 1058 return 0;
1059}
fb78d808 1060EXPORT_SYMBOL(omap_mcbsp_pollread);
bb13b5fd 1061
5e1c5ff4
TL		 1062/*
1063 * IRQ based word transmission.
1064 */
1065void omap_mcbsp_xmit_word(unsigned int id, u32 word)
1066{
b4b58f58 1067 struct omap_mcbsp *mcbsp;
bc5d0c89 1068 omap_mcbsp_word_length word_length;
5e1c5ff4 1069
bc5d0c89
EV		 1070 if (!omap_mcbsp_check_valid_id(id)) {
1071 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 1072 return;
bc5d0c89 1073 }
5e1c5ff4 1074
b4b58f58 1075 mcbsp = id_to_mcbsp_ptr(id);
b4b58f58 1076 word_length = mcbsp->tx_word_length;
5e1c5ff4 1077
b4b58f58 1078 wait_for_completion(&mcbsp->tx_irq_completion);
5e1c5ff4
TL		 1079
1080 if (word_length > OMAP_MCBSP_WORD_16)
8ea3200f
JK		 1081 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1082 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
5e1c5ff4 1083}
fb78d808 1084EXPORT_SYMBOL(omap_mcbsp_xmit_word);
5e1c5ff4
TL		 1085
1086u32 omap_mcbsp_recv_word(unsigned int id)
1087{
b4b58f58 1088 struct omap_mcbsp *mcbsp;
5e1c5ff4 1089 u16 word_lsb, word_msb = 0;
bc5d0c89 1090 omap_mcbsp_word_length word_length;
5e1c5ff4 1091
bc5d0c89
EV		 1092 if (!omap_mcbsp_check_valid_id(id)) {
1093 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1094 return -ENODEV;
1095 }
b4b58f58 1096 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 1097
b4b58f58 1098 word_length = mcbsp->rx_word_length;
5e1c5ff4 1099
b4b58f58 1100 wait_for_completion(&mcbsp->rx_irq_completion);
5e1c5ff4
TL		 1101
1102 if (word_length > OMAP_MCBSP_WORD_16)
8ea3200f
JK		 1103 word_msb = MCBSP_READ(mcbsp, DRR2);
1104 word_lsb = MCBSP_READ(mcbsp, DRR1);
5e1c5ff4
TL		 1105
1106 return (word_lsb | (word_msb << 16));
1107}
fb78d808 1108EXPORT_SYMBOL(omap_mcbsp_recv_word);
5e1c5ff4 1109
120db2cb
TL		 1110int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
1111{
b4b58f58 1112 struct omap_mcbsp *mcbsp;
bc5d0c89
EV		 1113 omap_mcbsp_word_length tx_word_length;
1114 omap_mcbsp_word_length rx_word_length;
120db2cb
TL		 1115 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1116
bc5d0c89
EV		 1117 if (!omap_mcbsp_check_valid_id(id)) {
1118 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1119 return -ENODEV;
1120 }
b4b58f58 1121 mcbsp = id_to_mcbsp_ptr(id);
b4b58f58
CS		 1122 tx_word_length = mcbsp->tx_word_length;
1123 rx_word_length = mcbsp->rx_word_length;
bc5d0c89 1124
120db2cb
TL		 1125 if (tx_word_length != rx_word_length)
1126 return -EINVAL;
1127
1128 /* First we wait for the transmitter to be ready */
8ea3200f 1129 spcr2 = MCBSP_READ(mcbsp, SPCR2);
120db2cb 1130 while (!(spcr2 & XRDY)) {
8ea3200f 1131 spcr2 = MCBSP_READ(mcbsp, SPCR2);
120db2cb
TL		 1132 if (attempts++ > 1000) {
1133 /* We must reset the transmitter */
96fbd745
JK		 1134 MCBSP_WRITE(mcbsp, SPCR2,
1135 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
120db2cb 1136 udelay(10);
96fbd745
JK		 1137 MCBSP_WRITE(mcbsp, SPCR2,
1138 MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
120db2cb 1139 udelay(10);
b4b58f58
CS		 1140 dev_err(mcbsp->dev, "McBSP%d transmitter not "
1141 "ready\n", mcbsp->id);
120db2cb
TL		 1142 return -EAGAIN;
1143 }
1144 }
1145
1146 /* Now we can push the data */
1147 if (tx_word_length > OMAP_MCBSP_WORD_16)
8ea3200f
JK		 1148 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1149 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
120db2cb
TL		 1150
1151 /* We wait for the receiver to be ready */
8ea3200f 1152 spcr1 = MCBSP_READ(mcbsp, SPCR1);
120db2cb 1153 while (!(spcr1 & RRDY)) {
8ea3200f 1154 spcr1 = MCBSP_READ(mcbsp, SPCR1);
120db2cb
TL		 1155 if (attempts++ > 1000) {
1156 /* We must reset the receiver */
96fbd745
JK		 1157 MCBSP_WRITE(mcbsp, SPCR1,
1158 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
120db2cb 1159 udelay(10);
96fbd745
JK		 1160 MCBSP_WRITE(mcbsp, SPCR1,
1161 MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
120db2cb 1162 udelay(10);
b4b58f58
CS		 1163 dev_err(mcbsp->dev, "McBSP%d receiver not "
1164 "ready\n", mcbsp->id);
120db2cb
TL		 1165 return -EAGAIN;
1166 }
1167 }
1168
1169 /* Receiver is ready, let's read the dummy data */
1170 if (rx_word_length > OMAP_MCBSP_WORD_16)
8ea3200f
JK		 1171 word_msb = MCBSP_READ(mcbsp, DRR2);
1172 word_lsb = MCBSP_READ(mcbsp, DRR1);
120db2cb
TL		 1173
1174 return 0;
1175}
fb78d808 1176EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
120db2cb 1177
fb78d808 1178int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
120db2cb 1179{
b4b58f58 1180 struct omap_mcbsp *mcbsp;
d592dd1a 1181 u32 clock_word = 0;
bc5d0c89
EV		 1182 omap_mcbsp_word_length tx_word_length;
1183 omap_mcbsp_word_length rx_word_length;
120db2cb
TL		 1184 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1185
bc5d0c89
EV		 1186 if (!omap_mcbsp_check_valid_id(id)) {
1187 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1188 return -ENODEV;
1189 }
1190
b4b58f58 1191 mcbsp = id_to_mcbsp_ptr(id);
b4b58f58
CS		 1192
1193 tx_word_length = mcbsp->tx_word_length;
1194 rx_word_length = mcbsp->rx_word_length;
bc5d0c89 1195
120db2cb
TL		 1196 if (tx_word_length != rx_word_length)
1197 return -EINVAL;
1198
1199 /* First we wait for the transmitter to be ready */
8ea3200f 1200 spcr2 = MCBSP_READ(mcbsp, SPCR2);
120db2cb 1201 while (!(spcr2 & XRDY)) {
8ea3200f 1202 spcr2 = MCBSP_READ(mcbsp, SPCR2);
120db2cb
TL		 1203 if (attempts++ > 1000) {
1204 /* We must reset the transmitter */
96fbd745
JK		 1205 MCBSP_WRITE(mcbsp, SPCR2,
1206 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
120db2cb 1207 udelay(10);
96fbd745
JK		 1208 MCBSP_WRITE(mcbsp, SPCR2,
1209 MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
120db2cb 1210 udelay(10);
b4b58f58
CS		 1211 dev_err(mcbsp->dev, "McBSP%d transmitter not "
1212 "ready\n", mcbsp->id);
120db2cb
TL		 1213 return -EAGAIN;
1214 }
1215 }
1216
1217 /* We first need to enable the bus clock */
1218 if (tx_word_length > OMAP_MCBSP_WORD_16)
8ea3200f
JK		 1219 MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
1220 MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
120db2cb
TL		 1221
1222 /* We wait for the receiver to be ready */
8ea3200f 1223 spcr1 = MCBSP_READ(mcbsp, SPCR1);
120db2cb 1224 while (!(spcr1 & RRDY)) {
8ea3200f 1225 spcr1 = MCBSP_READ(mcbsp, SPCR1);
120db2cb
TL		 1226 if (attempts++ > 1000) {
1227 /* We must reset the receiver */
96fbd745
JK		 1228 MCBSP_WRITE(mcbsp, SPCR1,
1229 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
120db2cb 1230 udelay(10);
96fbd745
JK		 1231 MCBSP_WRITE(mcbsp, SPCR1,
1232 MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
120db2cb 1233 udelay(10);
b4b58f58
CS		 1234 dev_err(mcbsp->dev, "McBSP%d receiver not "
1235 "ready\n", mcbsp->id);
120db2cb
TL		 1236 return -EAGAIN;
1237 }
1238 }
1239
1240 /* Receiver is ready, there is something for us */
1241 if (rx_word_length > OMAP_MCBSP_WORD_16)
8ea3200f
JK		 1242 word_msb = MCBSP_READ(mcbsp, DRR2);
1243 word_lsb = MCBSP_READ(mcbsp, DRR1);
120db2cb
TL		 1244
1245 word[0] = (word_lsb | (word_msb << 16));
1246
1247 return 0;
1248}
fb78d808 1249EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
120db2cb 1250
5e1c5ff4
TL		 1251/*
1252 * Simple DMA based buffer rx/tx routines.
1253 * Nothing fancy, just a single buffer tx/rx through DMA.
1254 * The DMA resources are released once the transfer is done.
1255 * For anything fancier, you should use your own customized DMA
1256 * routines and callbacks.
1257 */
fb78d808
EV		 1258int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
1259 unsigned int length)
5e1c5ff4 1260{
b4b58f58 1261 struct omap_mcbsp *mcbsp;
5e1c5ff4 1262 int dma_tx_ch;
120db2cb
TL		 1263 int src_port = 0;
1264 int dest_port = 0;
1265 int sync_dev = 0;
5e1c5ff4 1266
bc5d0c89
EV		 1267 if (!omap_mcbsp_check_valid_id(id)) {
1268 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1269 return -ENODEV;
1270 }
b4b58f58 1271 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 1272
b4b58f58 1273 if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
fb78d808 1274 omap_mcbsp_tx_dma_callback,
b4b58f58 1275 mcbsp,
fb78d808 1276 &dma_tx_ch)) {
b4b58f58 1277 dev_err(mcbsp->dev, " Unable to request DMA channel for "
bc5d0c89 1278 "McBSP%d TX. Trying IRQ based TX\n",
b4b58f58 1279 mcbsp->id);
5e1c5ff4
TL		 1280 return -EAGAIN;
1281 }
b4b58f58 1282 mcbsp->dma_tx_lch = dma_tx_ch;
5e1c5ff4 1283
b4b58f58 1284 dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
bc5d0c89 1285 dma_tx_ch);
5e1c5ff4 1286
b4b58f58 1287 init_completion(&mcbsp->tx_dma_completion);
5e1c5ff4 1288
120db2cb
TL		 1289 if (cpu_class_is_omap1()) {
1290 src_port = OMAP_DMA_PORT_TIPB;
1291 dest_port = OMAP_DMA_PORT_EMIFF;
1292 }
bc5d0c89 1293 if (cpu_class_is_omap2())
b4b58f58 1294 sync_dev = mcbsp->dma_tx_sync;
120db2cb 1295
b4b58f58 1296 omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
5e1c5ff4
TL		 1297 OMAP_DMA_DATA_TYPE_S16,
1298 length >> 1, 1,
1a8bfa1e 1299 OMAP_DMA_SYNC_ELEMENT,
120db2cb 1300 sync_dev, 0);
5e1c5ff4 1301
b4b58f58 1302 omap_set_dma_dest_params(mcbsp->dma_tx_lch,
120db2cb 1303 src_port,
5e1c5ff4 1304 OMAP_DMA_AMODE_CONSTANT,
b4b58f58 1305 mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
1a8bfa1e 1306 0, 0);
5e1c5ff4 1307
b4b58f58 1308 omap_set_dma_src_params(mcbsp->dma_tx_lch,
120db2cb 1309 dest_port,
5e1c5ff4 1310 OMAP_DMA_AMODE_POST_INC,
1a8bfa1e
TL		 1311 buffer,
1312 0, 0);
5e1c5ff4 1313
b4b58f58
CS		 1314 omap_start_dma(mcbsp->dma_tx_lch);
1315 wait_for_completion(&mcbsp->tx_dma_completion);
fb78d808 1316
5e1c5ff4
TL		 1317 return 0;
1318}
fb78d808 1319EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
5e1c5ff4 1320
fb78d808
EV		 1321int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
1322 unsigned int length)
5e1c5ff4 1323{
b4b58f58 1324 struct omap_mcbsp *mcbsp;
5e1c5ff4 1325 int dma_rx_ch;
120db2cb
TL		 1326 int src_port = 0;
1327 int dest_port = 0;
1328 int sync_dev = 0;
5e1c5ff4 1329
bc5d0c89
EV		 1330 if (!omap_mcbsp_check_valid_id(id)) {
1331 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1332 return -ENODEV;
1333 }
b4b58f58 1334 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 1335
b4b58f58 1336 if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
fb78d808 1337 omap_mcbsp_rx_dma_callback,
b4b58f58 1338 mcbsp,
fb78d808 1339 &dma_rx_ch)) {
b4b58f58 1340 dev_err(mcbsp->dev, "Unable to request DMA channel for "
bc5d0c89 1341 "McBSP%d RX. Trying IRQ based RX\n",
b4b58f58 1342 mcbsp->id);
5e1c5ff4
TL		 1343 return -EAGAIN;
1344 }
b4b58f58 1345 mcbsp->dma_rx_lch = dma_rx_ch;
5e1c5ff4 1346
b4b58f58 1347 dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
bc5d0c89 1348 dma_rx_ch);
5e1c5ff4 1349
b4b58f58 1350 init_completion(&mcbsp->rx_dma_completion);
5e1c5ff4 1351
120db2cb
TL		 1352 if (cpu_class_is_omap1()) {
1353 src_port = OMAP_DMA_PORT_TIPB;
1354 dest_port = OMAP_DMA_PORT_EMIFF;
1355 }
bc5d0c89 1356 if (cpu_class_is_omap2())
b4b58f58 1357 sync_dev = mcbsp->dma_rx_sync;
120db2cb 1358
b4b58f58 1359 omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
fb78d808
EV		 1360 OMAP_DMA_DATA_TYPE_S16,
1361 length >> 1, 1,
1362 OMAP_DMA_SYNC_ELEMENT,
1363 sync_dev, 0);
5e1c5ff4 1364
b4b58f58 1365 omap_set_dma_src_params(mcbsp->dma_rx_lch,
120db2cb 1366 src_port,
5e1c5ff4 1367 OMAP_DMA_AMODE_CONSTANT,
b4b58f58 1368 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1a8bfa1e 1369 0, 0);
5e1c5ff4 1370
b4b58f58 1371 omap_set_dma_dest_params(mcbsp->dma_rx_lch,
fb78d808
EV		 1372 dest_port,
1373 OMAP_DMA_AMODE_POST_INC,
1374 buffer,
1375 0, 0);
5e1c5ff4 1376
b4b58f58
CS		 1377 omap_start_dma(mcbsp->dma_rx_lch);
1378 wait_for_completion(&mcbsp->rx_dma_completion);
fb78d808 1379
5e1c5ff4
TL		 1380 return 0;
1381}
fb78d808 1382EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
5e1c5ff4
TL		 1383
1384/*
1385 * SPI wrapper.
1386 * Since SPI setup is much simpler than the generic McBSP one,
1387 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1388 * Once this is done, you can call omap_mcbsp_start().
1389 */
fb78d808
EV		 1390void omap_mcbsp_set_spi_mode(unsigned int id,
1391 const struct omap_mcbsp_spi_cfg *spi_cfg)
5e1c5ff4 1392{
b4b58f58 1393 struct omap_mcbsp *mcbsp;
5e1c5ff4
TL		 1394 struct omap_mcbsp_reg_cfg mcbsp_cfg;
1395
bc5d0c89
EV		 1396 if (!omap_mcbsp_check_valid_id(id)) {
1397 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 1398 return;
bc5d0c89 1399 }
b4b58f58 1400 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4
TL		 1401
1402 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1403
1404 /* SPI has only one frame */
1405 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1406 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1407
fb78d808 1408 /* Clock stop mode */
5e1c5ff4
TL		 1409 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1410 mcbsp_cfg.spcr1 |= (1 << 12);
1411 else
1412 mcbsp_cfg.spcr1 |= (3 << 11);
1413
1414 /* Set clock parities */
1415 if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1416 mcbsp_cfg.pcr0 |= CLKRP;
1417 else
1418 mcbsp_cfg.pcr0 &= ~CLKRP;
1419
1420 if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1421 mcbsp_cfg.pcr0 &= ~CLKXP;
1422 else
1423 mcbsp_cfg.pcr0 |= CLKXP;
1424
1425 /* Set SCLKME to 0 and CLKSM to 1 */
1426 mcbsp_cfg.pcr0 &= ~SCLKME;
1427 mcbsp_cfg.srgr2 |= CLKSM;
1428
1429 /* Set FSXP */
1430 if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1431 mcbsp_cfg.pcr0 &= ~FSXP;
1432 else
1433 mcbsp_cfg.pcr0 |= FSXP;
1434
1435 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1436 mcbsp_cfg.pcr0 |= CLKXM;
fb78d808 1437 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
5e1c5ff4
TL		 1438 mcbsp_cfg.pcr0 |= FSXM;
1439 mcbsp_cfg.srgr2 &= ~FSGM;
1440 mcbsp_cfg.xcr2 |= XDATDLY(1);
1441 mcbsp_cfg.rcr2 |= RDATDLY(1);
fb78d808 1442 } else {
5e1c5ff4
TL		 1443 mcbsp_cfg.pcr0 &= ~CLKXM;
1444 mcbsp_cfg.srgr1 |= CLKGDV(1);
1445 mcbsp_cfg.pcr0 &= ~FSXM;
1446 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1447 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1448 }
1449
1450 mcbsp_cfg.xcr2 &= ~XPHASE;
1451 mcbsp_cfg.rcr2 &= ~RPHASE;
1452
1453 omap_mcbsp_config(id, &mcbsp_cfg);
1454}
fb78d808 1455EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
5e1c5ff4 1456
a8eb7ca0 1457#ifdef CONFIG_ARCH_OMAP3
a1a56f5f
EV		 1458#define max_thres(m) (mcbsp->pdata->buffer_size)
1459#define valid_threshold(m, val) ((val) <= max_thres(m))
1460#define THRESHOLD_PROP_BUILDER(prop) \
1461static ssize_t prop##_show(struct device *dev, \
1462 struct device_attribute *attr, char *buf) \
1463{ \
1464 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1465 \
1466 return sprintf(buf, "%u\n", mcbsp->prop); \
1467} \
1468 \
1469static ssize_t prop##_store(struct device *dev, \
1470 struct device_attribute *attr, \
1471 const char *buf, size_t size) \
1472{ \
1473 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1474 unsigned long val; \
1475 int status; \
1476 \
1477 status = strict_strtoul(buf, 0, &val); \
1478 if (status) \
1479 return status; \
1480 \
1481 if (!valid_threshold(mcbsp, val)) \
1482 return -EDOM; \
1483 \
1484 mcbsp->prop = val; \
1485 return size; \
1486} \
1487 \
1488static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1489
1490THRESHOLD_PROP_BUILDER(max_tx_thres);
1491THRESHOLD_PROP_BUILDER(max_rx_thres);
1492
9b300509
JN		 1493static const char *dma_op_modes[] = {
1494 "element", "threshold", "frame",
1495};
1496
98cb20e8
PU		 1497static ssize_t dma_op_mode_show(struct device *dev,
1498 struct device_attribute *attr, char *buf)
1499{
1500 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
9b300509
JN		 1501 int dma_op_mode, i = 0;
1502 ssize_t len = 0;
1503 const char * const *s;
98cb20e8 1504
98cb20e8 1505 dma_op_mode = mcbsp->dma_op_mode;
98cb20e8 1506
9b300509
JN		 1507 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1508 if (dma_op_mode == i)
1509 len += sprintf(buf + len, "[%s] ", *s);
1510 else
1511 len += sprintf(buf + len, "%s ", *s);
1512 }
1513 len += sprintf(buf + len, "\n");
1514
1515 return len;
98cb20e8
PU		 1516}
1517
1518static ssize_t dma_op_mode_store(struct device *dev,
1519 struct device_attribute *attr,
1520 const char *buf, size_t size)
1521{
1522 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
9b300509
JN		 1523 const char * const *s;
1524 int i = 0;
98cb20e8 1525
9b300509
JN		 1526 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1527 if (sysfs_streq(buf, *s))
1528 break;
98cb20e8 1529
9b300509
JN		 1530 if (i == ARRAY_SIZE(dma_op_modes))
1531 return -EINVAL;
98cb20e8 1532
9b300509 1533 spin_lock_irq(&mcbsp->lock);
98cb20e8
PU		 1534 if (!mcbsp->free) {
1535 size = -EBUSY;
1536 goto unlock;
1537 }
9b300509 1538 mcbsp->dma_op_mode = i;
98cb20e8
PU		 1539
1540unlock:
1541 spin_unlock_irq(&mcbsp->lock);
1542
1543 return size;
1544}
1545
1546static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1547
d912fa92
EN		 1548static ssize_t st_taps_show(struct device *dev,
1549 struct device_attribute *attr, char *buf)
1550{
1551 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1552 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1553 ssize_t status = 0;
1554 int i;
1555
1556 spin_lock_irq(&mcbsp->lock);
1557 for (i = 0; i < st_data->nr_taps; i++)
1558 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1559 st_data->taps[i]);
1560 if (i)
1561 status += sprintf(&buf[status], "\n");
1562 spin_unlock_irq(&mcbsp->lock);
1563
1564 return status;
1565}
1566
1567static ssize_t st_taps_store(struct device *dev,
1568 struct device_attribute *attr,
1569 const char *buf, size_t size)
1570{
1571 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1572 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1573 int val, tmp, status, i = 0;
1574
1575 spin_lock_irq(&mcbsp->lock);
1576 memset(st_data->taps, 0, sizeof(st_data->taps));
1577 st_data->nr_taps = 0;
1578
1579 do {
1580 status = sscanf(buf, "%d%n", &val, &tmp);
1581 if (status < 0 || status == 0) {
1582 size = -EINVAL;
1583 goto out;
1584 }
1585 if (val < -32768 || val > 32767) {
1586 size = -EINVAL;
1587 goto out;
1588 }
1589 st_data->taps[i++] = val;
1590 buf += tmp;
1591 if (*buf != ',')
1592 break;
1593 buf++;
1594 } while (1);
1595
1596 st_data->nr_taps = i;
1597
1598out:
1599 spin_unlock_irq(&mcbsp->lock);
1600
1601 return size;
1602}
1603
1604static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1605
4c8200ae 1606static const struct attribute *additional_attrs[] = {
a1a56f5f
EV		 1607 &dev_attr_max_tx_thres.attr,
1608 &dev_attr_max_rx_thres.attr,
98cb20e8 1609 &dev_attr_dma_op_mode.attr,
a1a56f5f
EV		 1610 NULL,
1611};
1612
4c8200ae
EV		 1613static const struct attribute_group additional_attr_group = {
1614 .attrs = (struct attribute **)additional_attrs,
a1a56f5f
EV		 1615};
1616
4c8200ae 1617static inline int __devinit omap_additional_add(struct device *dev)
a1a56f5f 1618{
4c8200ae 1619 return sysfs_create_group(&dev->kobj, &additional_attr_group);
a1a56f5f
EV		 1620}
1621
4c8200ae 1622static inline void __devexit omap_additional_remove(struct device *dev)
a1a56f5f 1623{
4c8200ae 1624 sysfs_remove_group(&dev->kobj, &additional_attr_group);
a1a56f5f
EV		 1625}
1626
d912fa92
EN		 1627static const struct attribute *sidetone_attrs[] = {
1628 &dev_attr_st_taps.attr,
1629 NULL,
1630};
1631
1632static const struct attribute_group sidetone_attr_group = {
1633 .attrs = (struct attribute **)sidetone_attrs,
1634};
1635
1636int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1637{
1638 struct omap_mcbsp_platform_data *pdata = mcbsp->pdata;
1639 struct omap_mcbsp_st_data *st_data;
1640 int err;
1641
1642 st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1643 if (!st_data) {
1644 err = -ENOMEM;
1645 goto err1;
1646 }
1647
1648 st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K);
1649 if (!st_data->io_base_st) {
1650 err = -ENOMEM;
1651 goto err2;
1652 }
1653
1654 err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1655 if (err)
1656 goto err3;
1657
1658 mcbsp->st_data = st_data;
1659 return 0;
1660
1661err3:
1662 iounmap(st_data->io_base_st);
1663err2:
1664 kfree(st_data);
1665err1:
1666 return err;
1667
1668}
1669
1670static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1671{
1672 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1673
1674 if (st_data) {
1675 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1676 iounmap(st_data->io_base_st);
1677 kfree(st_data);
1678 }
1679}
1680
a1a56f5f
EV		 1681static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1682{
98cb20e8 1683 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
a1a56f5f
EV		 1684 if (cpu_is_omap34xx()) {
1685 mcbsp->max_tx_thres = max_thres(mcbsp);
1686 mcbsp->max_rx_thres = max_thres(mcbsp);
98cb20e8
PU		 1687 /*
1688 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1689 * for mcbsp2 instances.
1690 */
4c8200ae 1691 if (omap_additional_add(mcbsp->dev))
a1a56f5f 1692 dev_warn(mcbsp->dev,
4c8200ae 1693 "Unable to create additional controls\n");
d912fa92
EN		 1694
1695 if (mcbsp->id == 2 || mcbsp->id == 3)
1696 if (omap_st_add(mcbsp))
1697 dev_warn(mcbsp->dev,
1698 "Unable to create sidetone controls\n");
1699
a1a56f5f
EV		 1700 } else {
1701 mcbsp->max_tx_thres = -EINVAL;
1702 mcbsp->max_rx_thres = -EINVAL;
1703 }
1704}
1705
1706static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1707{
d912fa92 1708 if (cpu_is_omap34xx()) {
4c8200ae 1709 omap_additional_remove(mcbsp->dev);
d912fa92
EN		 1710
1711 if (mcbsp->id == 2 || mcbsp->id == 3)
1712 omap_st_remove(mcbsp);
1713 }
a1a56f5f
EV		 1714}
1715#else
1716static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1717static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
a8eb7ca0 1718#endif /* CONFIG_ARCH_OMAP3 */
a1a56f5f 1719
5e1c5ff4
TL		 1720/*
1721 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1722 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1723 */
25cef225 1724static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
bc5d0c89
EV		 1725{
1726 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
b4b58f58 1727 struct omap_mcbsp *mcbsp;
bc5d0c89
EV		 1728 int id = pdev->id - 1;
1729 int ret = 0;
5e1c5ff4 1730
bc5d0c89
EV		 1731 if (!pdata) {
1732 dev_err(&pdev->dev, "McBSP device initialized without"
1733 "platform data\n");
1734 ret = -EINVAL;
1735 goto exit;
1736 }
1737
1738 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1739
b4b58f58 1740 if (id >= omap_mcbsp_count) {
bc5d0c89
EV		 1741 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1742 ret = -EINVAL;
1743 goto exit;
1744 }
1745
b4b58f58
CS		 1746 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1747 if (!mcbsp) {
1748 ret = -ENOMEM;
1749 goto exit;
1750 }
b4b58f58
CS		 1751
1752 spin_lock_init(&mcbsp->lock);
1753 mcbsp->id = id + 1;
1754 mcbsp->free = 1;
1755 mcbsp->dma_tx_lch = -1;
1756 mcbsp->dma_rx_lch = -1;
bc5d0c89 1757
b4b58f58
CS		 1758 mcbsp->phys_base = pdata->phys_base;
1759 mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
1760 if (!mcbsp->io_base) {
d592dd1a
RK		 1761 ret = -ENOMEM;
1762 goto err_ioremap;
1763 }
1764
bc5d0c89 1765 /* Default I/O is IRQ based */
b4b58f58
CS		 1766 mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1767 mcbsp->tx_irq = pdata->tx_irq;
1768 mcbsp->rx_irq = pdata->rx_irq;
1769 mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1770 mcbsp->dma_tx_sync = pdata->dma_tx_sync;
bc5d0c89 1771
b820ce4e
RK		 1772 mcbsp->iclk = clk_get(&pdev->dev, "ick");
1773 if (IS_ERR(mcbsp->iclk)) {
1774 ret = PTR_ERR(mcbsp->iclk);
1775 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1776 goto err_iclk;
1777 }
06151158 1778
b820ce4e
RK		 1779 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1780 if (IS_ERR(mcbsp->fclk)) {
1781 ret = PTR_ERR(mcbsp->fclk);
1782 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1783 goto err_fclk;
bc5d0c89
EV		 1784 }
1785
b4b58f58
CS		 1786 mcbsp->pdata = pdata;
1787 mcbsp->dev = &pdev->dev;
b820ce4e 1788 mcbsp_ptr[id] = mcbsp;
b4b58f58 1789 platform_set_drvdata(pdev, mcbsp);
a1a56f5f
EV		 1790
1791 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1792 omap34xx_device_init(mcbsp);
1793
d592dd1a 1794 return 0;
bc5d0c89 1795
b820ce4e
RK		 1796err_fclk:
1797 clk_put(mcbsp->iclk);
1798err_iclk:
b4b58f58 1799 iounmap(mcbsp->io_base);
d592dd1a 1800err_ioremap:
b820ce4e 1801 kfree(mcbsp);
bc5d0c89
EV		 1802exit:
1803 return ret;
1804}
120db2cb 1805
25cef225 1806static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
5e1c5ff4 1807{
bc5d0c89 1808 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
5e1c5ff4 1809
bc5d0c89
EV		 1810 platform_set_drvdata(pdev, NULL);
1811 if (mcbsp) {
5e1c5ff4 1812
bc5d0c89
EV		 1813 if (mcbsp->pdata && mcbsp->pdata->ops &&
1814 mcbsp->pdata->ops->free)
1815 mcbsp->pdata->ops->free(mcbsp->id);
5e1c5ff4 1816
a1a56f5f
EV		 1817 omap34xx_device_exit(mcbsp);
1818
b820ce4e
RK		 1819 clk_disable(mcbsp->fclk);
1820 clk_disable(mcbsp->iclk);
1821 clk_put(mcbsp->fclk);
1822 clk_put(mcbsp->iclk);
bc5d0c89 1823
d592dd1a
RK		 1824 iounmap(mcbsp->io_base);
1825
b820ce4e
RK		 1826 mcbsp->fclk = NULL;
1827 mcbsp->iclk = NULL;
bc5d0c89
EV		 1828 mcbsp->free = 0;
1829 mcbsp->dev = NULL;
5e1c5ff4
TL		 1830 }
1831
1832 return 0;
1833}
1834
bc5d0c89
EV		 1835static struct platform_driver omap_mcbsp_driver = {
1836 .probe = omap_mcbsp_probe,
25cef225 1837 .remove = __devexit_p(omap_mcbsp_remove),
bc5d0c89
EV		 1838 .driver = {
1839 .name = "omap-mcbsp",
1840 },
1841};
1842
1843int __init omap_mcbsp_init(void)
1844{
1845 /* Register the McBSP driver */
1846 return platform_driver_register(&omap_mcbsp_driver);
1847}
Linux kernel - Deliverables
This page took 1.156537 seconds and 5 git commands to generate.