projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[ARM] Move AMBA bus code to drivers/amba/
[deliverable/linux.git] / arch / arm / plat-omap / mcbsp.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/mcbsp.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Multichannel mode not supported.
13 */
14
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/device.h>
18#include <linux/wait.h>
19#include <linux/completion.h>
20#include <linux/interrupt.h>
21#include <linux/err.h>
22
23#include <asm/delay.h>
24#include <asm/io.h>
25#include <asm/irq.h>
26
27#include <asm/arch/dma.h>
28#include <asm/arch/mux.h>
29#include <asm/arch/irqs.h>
92105bb7 30#include <asm/arch/dsp_common.h>
5e1c5ff4
TL		 31#include <asm/arch/mcbsp.h>
32
33#include <asm/hardware/clock.h>
34
35#ifdef CONFIG_MCBSP_DEBUG
36#define DBG(x...) printk(x)
37#else
38#define DBG(x...) do { } while (0)
39#endif
40
41struct omap_mcbsp {
42 u32 io_base;
43 u8 id;
44 u8 free;
45 omap_mcbsp_word_length rx_word_length;
46 omap_mcbsp_word_length tx_word_length;
47
48 /* IRQ based TX/RX */
49 int rx_irq;
50 int tx_irq;
51
52 /* DMA stuff */
53 u8 dma_rx_sync;
54 short dma_rx_lch;
55 u8 dma_tx_sync;
56 short dma_tx_lch;
57
58 /* Completion queues */
59 struct completion tx_irq_completion;
60 struct completion rx_irq_completion;
61 struct completion tx_dma_completion;
62 struct completion rx_dma_completion;
63
64 spinlock_t lock;
65};
66
67static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];
68static struct clk *mcbsp_dsp_ck = 0;
69static struct clk *mcbsp_api_ck = 0;
bb13b5fd 70static struct clk *mcbsp_dspxor_ck = 0;
5e1c5ff4
TL		 71
72
73static void omap_mcbsp_dump_reg(u8 id)
74{
75 DBG("**** MCBSP%d regs ****\n", mcbsp[id].id);
76 DBG("DRR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
77 DBG("DRR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
78 DBG("DXR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
79 DBG("DXR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
80 DBG("SPCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
81 DBG("SPCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
82 DBG("RCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
83 DBG("RCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
84 DBG("XCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
85 DBG("XCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
86 DBG("SRGR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
87 DBG("SRGR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
88 DBG("PCR0: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
89 DBG("***********************\n");
90}
91
92
93static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
94{
95 struct omap_mcbsp * mcbsp_tx = (struct omap_mcbsp *)(dev_id);
96
97 DBG("TX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));
98
99 complete(&mcbsp_tx->tx_irq_completion);
100 return IRQ_HANDLED;
101}
102
103static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
104{
105 struct omap_mcbsp * mcbsp_rx = (struct omap_mcbsp *)(dev_id);
106
107 DBG("RX IRQ callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));
108
109 complete(&mcbsp_rx->rx_irq_completion);
110 return IRQ_HANDLED;
111}
112
113
114static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
115{
116 struct omap_mcbsp * mcbsp_dma_tx = (struct omap_mcbsp *)(data);
117
118 DBG("TX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
119
120 /* We can free the channels */
121 omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
122 mcbsp_dma_tx->dma_tx_lch = -1;
123
124 complete(&mcbsp_dma_tx->tx_dma_completion);
125}
126
127static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
128{
129 struct omap_mcbsp * mcbsp_dma_rx = (struct omap_mcbsp *)(data);
130
131 DBG("RX DMA callback : 0x%x\n", OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
132
133 /* We can free the channels */
134 omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
135 mcbsp_dma_rx->dma_rx_lch = -1;
136
137 complete(&mcbsp_dma_rx->rx_dma_completion);
138}
139
140
141/*
142 * omap_mcbsp_config simply write a config to the
143 * appropriate McBSP.
144 * You either call this function or set the McBSP registers
145 * by yourself before calling omap_mcbsp_start().
146 */
147
148void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config)
149{
150 u32 io_base = mcbsp[id].io_base;
151
152 DBG("OMAP-McBSP: McBSP%d io_base: 0x%8x\n", id+1, io_base);
153
154 /* We write the given config */
155 OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
156 OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
157 OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
158 OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
159 OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
160 OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
161 OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
162 OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
163 OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
164 OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
165 OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
166}
167
168
169
170static int omap_mcbsp_check(unsigned int id)
171{
172 if (cpu_is_omap730()) {
173 if (id > OMAP_MAX_MCBSP_COUNT - 1) {
174 printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
175 return -1;
176 }
177 return 0;
178 }
179
bb13b5fd 180 if (cpu_is_omap1510() || cpu_is_omap16xx()) {
5e1c5ff4
TL		 181 if (id > OMAP_MAX_MCBSP_COUNT) {
182 printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
183 return -1;
184 }
185 return 0;
186 }
187
188 return -1;
189}
190
5e1c5ff4
TL		 191static void omap_mcbsp_dsp_request(void)
192{
bb13b5fd
TL		 193 if (cpu_is_omap1510() || cpu_is_omap16xx()) {
194 clk_use(mcbsp_dsp_ck);
195 clk_use(mcbsp_api_ck);
5e1c5ff4
TL		 196
197 /* enable 12MHz clock to mcbsp 1 & 3 */
bb13b5fd 198 clk_use(mcbsp_dspxor_ck);
92105bb7
TL		 199
200 /*
201 * DSP external peripheral reset
202 * FIXME: This should be moved to dsp code
203 */
5e1c5ff4
TL		 204 __raw_writew(__raw_readw(DSP_RSTCT2) | 1 | 1 << 1,
205 DSP_RSTCT2);
206 }
207}
208
209static void omap_mcbsp_dsp_free(void)
210{
bb13b5fd
TL		 211 if (cpu_is_omap1510() || cpu_is_omap16xx()) {
212 clk_unuse(mcbsp_dspxor_ck);
213 clk_unuse(mcbsp_dsp_ck);
214 clk_unuse(mcbsp_api_ck);
215 }
5e1c5ff4
TL		 216}
217
5e1c5ff4
TL		 218int omap_mcbsp_request(unsigned int id)
219{
220 int err;
221
222 if (omap_mcbsp_check(id) < 0)
223 return -EINVAL;
224
225 /*
226 * On 1510, 1610 and 1710, McBSP1 and McBSP3
227 * are DSP public peripherals.
228 */
229 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
230 omap_mcbsp_dsp_request();
231
232 spin_lock(&mcbsp[id].lock);
233 if (!mcbsp[id].free) {
234 printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1);
235 spin_unlock(&mcbsp[id].lock);
236 return -1;
237 }
238
239 mcbsp[id].free = 0;
240 spin_unlock(&mcbsp[id].lock);
241
242 /* We need to get IRQs here */
243 err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler, 0,
244 "McBSP",
245 (void *) (&mcbsp[id]));
246 if (err != 0) {
247 printk(KERN_ERR "OMAP-McBSP: Unable to request TX IRQ %d for McBSP%d\n",
248 mcbsp[id].tx_irq, mcbsp[id].id);
249 return err;
250 }
251
252 init_completion(&(mcbsp[id].tx_irq_completion));
253
254
255 err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler, 0,
256 "McBSP",
257 (void *) (&mcbsp[id]));
258 if (err != 0) {
259 printk(KERN_ERR "OMAP-McBSP: Unable to request RX IRQ %d for McBSP%d\n",
260 mcbsp[id].rx_irq, mcbsp[id].id);
261 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
262 return err;
263 }
264
265 init_completion(&(mcbsp[id].rx_irq_completion));
266 return 0;
267
268}
269
270void omap_mcbsp_free(unsigned int id)
271{
272 if (omap_mcbsp_check(id) < 0)
273 return;
274
275 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
276 omap_mcbsp_dsp_free();
277
278 spin_lock(&mcbsp[id].lock);
279 if (mcbsp[id].free) {
280 printk (KERN_ERR "OMAP-McBSP: McBSP%d was not reserved\n", id + 1);
281 spin_unlock(&mcbsp[id].lock);
282 return;
283 }
284
285 mcbsp[id].free = 1;
286 spin_unlock(&mcbsp[id].lock);
287
288 /* Free IRQs */
289 free_irq(mcbsp[id].rx_irq, (void *) (&mcbsp[id]));
290 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
291}
292
293/*
294 * Here we start the McBSP, by enabling the sample
295 * generator, both transmitter and receivers,
296 * and the frame sync.
297 */
298void omap_mcbsp_start(unsigned int id)
299{
300 u32 io_base;
301 u16 w;
302
303 if (omap_mcbsp_check(id) < 0)
304 return;
305
306 io_base = mcbsp[id].io_base;
307
308 mcbsp[id].rx_word_length = ((OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7);
309 mcbsp[id].tx_word_length = ((OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7);
310
311 /* Start the sample generator */
312 w = OMAP_MCBSP_READ(io_base, SPCR2);
313 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
314
315 /* Enable transmitter and receiver */
316 w = OMAP_MCBSP_READ(io_base, SPCR2);
317 OMAP_MCBSP_WRITE(io_base, SPCR2, w | 1);
318
319 w = OMAP_MCBSP_READ(io_base, SPCR1);
320 OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1);
321
322 udelay(100);
323
324 /* Start frame sync */
325 w = OMAP_MCBSP_READ(io_base, SPCR2);
326 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
327
328 /* Dump McBSP Regs */
329 omap_mcbsp_dump_reg(id);
330
331}
332
333void omap_mcbsp_stop(unsigned int id)
334{
335 u32 io_base;
336 u16 w;
337
338 if (omap_mcbsp_check(id) < 0)
339 return;
340
341 io_base = mcbsp[id].io_base;
342
343 /* Reset transmitter */
344 w = OMAP_MCBSP_READ(io_base, SPCR2);
345 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1));
346
347 /* Reset receiver */
348 w = OMAP_MCBSP_READ(io_base, SPCR1);
349 OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(1));
350
351 /* Reset the sample rate generator */
352 w = OMAP_MCBSP_READ(io_base, SPCR2);
353 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
354}
355
356
bb13b5fd
TL		 357/* polled mcbsp i/o operations */
358int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
359{
360 u32 base = mcbsp[id].io_base;
361 writew(buf, base + OMAP_MCBSP_REG_DXR1);
362 /* if frame sync error - clear the error */
363 if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
364 /* clear error */
365 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
366 base + OMAP_MCBSP_REG_SPCR2);
367 /* resend */
368 return -1;
369 } else {
370 /* wait for transmit confirmation */
371 int attemps = 0;
372 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
373 if (attemps++ > 1000) {
374 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
375 (~XRST),
376 base + OMAP_MCBSP_REG_SPCR2);
377 udelay(10);
378 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
379 (XRST),
380 base + OMAP_MCBSP_REG_SPCR2);
381 udelay(10);
382 printk(KERN_ERR
383 " Could not write to McBSP Register\n");
384 return -2;
385 }
386 }
387 }
388 return 0;
389}
390
391int omap_mcbsp_pollread(unsigned int id, u16 * buf)
392{
393 u32 base = mcbsp[id].io_base;
394 /* if frame sync error - clear the error */
395 if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
396 /* clear error */
397 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
398 base + OMAP_MCBSP_REG_SPCR1);
399 /* resend */
400 return -1;
401 } else {
402 /* wait for recieve confirmation */
403 int attemps = 0;
404 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
405 if (attemps++ > 1000) {
406 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
407 (~RRST),
408 base + OMAP_MCBSP_REG_SPCR1);
409 udelay(10);
410 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
411 (RRST),
412 base + OMAP_MCBSP_REG_SPCR1);
413 udelay(10);
414 printk(KERN_ERR
415 " Could not read from McBSP Register\n");
416 return -2;
417 }
418 }
419 }
420 *buf = readw(base + OMAP_MCBSP_REG_DRR1);
421 return 0;
422}
423
5e1c5ff4
TL		 424/*
425 * IRQ based word transmission.
426 */
427void omap_mcbsp_xmit_word(unsigned int id, u32 word)
428{
429 u32 io_base;
430 omap_mcbsp_word_length word_length = mcbsp[id].tx_word_length;
431
432 if (omap_mcbsp_check(id) < 0)
433 return;
434
435 io_base = mcbsp[id].io_base;
436
437 wait_for_completion(&(mcbsp[id].tx_irq_completion));
438
439 if (word_length > OMAP_MCBSP_WORD_16)
440 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
441 OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
442}
443
444u32 omap_mcbsp_recv_word(unsigned int id)
445{
446 u32 io_base;
447 u16 word_lsb, word_msb = 0;
448 omap_mcbsp_word_length word_length = mcbsp[id].rx_word_length;
449
450 if (omap_mcbsp_check(id) < 0)
451 return -EINVAL;
452
453 io_base = mcbsp[id].io_base;
454
455 wait_for_completion(&(mcbsp[id].rx_irq_completion));
456
457 if (word_length > OMAP_MCBSP_WORD_16)
458 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
459 word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
460
461 return (word_lsb | (word_msb << 16));
462}
463
464
465/*
466 * Simple DMA based buffer rx/tx routines.
467 * Nothing fancy, just a single buffer tx/rx through DMA.
468 * The DMA resources are released once the transfer is done.
469 * For anything fancier, you should use your own customized DMA
470 * routines and callbacks.
471 */
472int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
473{
474 int dma_tx_ch;
475
476 if (omap_mcbsp_check(id) < 0)
477 return -EINVAL;
478
479 if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX", omap_mcbsp_tx_dma_callback,
480 &mcbsp[id],
481 &dma_tx_ch)) {
482 printk("OMAP-McBSP: Unable to request DMA channel for McBSP%d TX. Trying IRQ based TX\n", id+1);
483 return -EAGAIN;
484 }
485 mcbsp[id].dma_tx_lch = dma_tx_ch;
486
487 DBG("TX DMA on channel %d\n", dma_tx_ch);
488
489 init_completion(&(mcbsp[id].tx_dma_completion));
490
491 omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
492 OMAP_DMA_DATA_TYPE_S16,
493 length >> 1, 1,
1a8bfa1e
TL		 494 OMAP_DMA_SYNC_ELEMENT,
495 0, 0);
5e1c5ff4
TL		 496
497 omap_set_dma_dest_params(mcbsp[id].dma_tx_lch,
498 OMAP_DMA_PORT_TIPB,
499 OMAP_DMA_AMODE_CONSTANT,
1a8bfa1e
TL		 500 mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1,
501 0, 0);
5e1c5ff4
TL		 502
503 omap_set_dma_src_params(mcbsp[id].dma_tx_lch,
504 OMAP_DMA_PORT_EMIFF,
505 OMAP_DMA_AMODE_POST_INC,
1a8bfa1e
TL		 506 buffer,
507 0, 0);
5e1c5ff4
TL		 508
509 omap_start_dma(mcbsp[id].dma_tx_lch);
510 wait_for_completion(&(mcbsp[id].tx_dma_completion));
511 return 0;
512}
513
514
515int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
516{
517 int dma_rx_ch;
518
519 if (omap_mcbsp_check(id) < 0)
520 return -EINVAL;
521
522 if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX", omap_mcbsp_rx_dma_callback,
523 &mcbsp[id],
524 &dma_rx_ch)) {
525 printk("Unable to request DMA channel for McBSP%d RX. Trying IRQ based RX\n", id+1);
526 return -EAGAIN;
527 }
528 mcbsp[id].dma_rx_lch = dma_rx_ch;
529
530 DBG("RX DMA on channel %d\n", dma_rx_ch);
531
532 init_completion(&(mcbsp[id].rx_dma_completion));
533
534 omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
535 OMAP_DMA_DATA_TYPE_S16,
536 length >> 1, 1,
1a8bfa1e
TL		 537 OMAP_DMA_SYNC_ELEMENT,
538 0, 0);
5e1c5ff4
TL		 539
540 omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
541 OMAP_DMA_PORT_TIPB,
542 OMAP_DMA_AMODE_CONSTANT,
1a8bfa1e
TL		 543 mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1,
544 0, 0);
5e1c5ff4
TL		 545
546 omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
547 OMAP_DMA_PORT_EMIFF,
548 OMAP_DMA_AMODE_POST_INC,
1a8bfa1e
TL		 549 buffer,
550 0, 0);
5e1c5ff4
TL		 551
552 omap_start_dma(mcbsp[id].dma_rx_lch);
553 wait_for_completion(&(mcbsp[id].rx_dma_completion));
554 return 0;
555}
556
557
558/*
559 * SPI wrapper.
560 * Since SPI setup is much simpler than the generic McBSP one,
561 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
562 * Once this is done, you can call omap_mcbsp_start().
563 */
564void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg)
565{
566 struct omap_mcbsp_reg_cfg mcbsp_cfg;
567
568 if (omap_mcbsp_check(id) < 0)
569 return;
570
571 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
572
573 /* SPI has only one frame */
574 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
575 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
576
577 /* Clock stop mode */
578 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
579 mcbsp_cfg.spcr1 |= (1 << 12);
580 else
581 mcbsp_cfg.spcr1 |= (3 << 11);
582
583 /* Set clock parities */
584 if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
585 mcbsp_cfg.pcr0 |= CLKRP;
586 else
587 mcbsp_cfg.pcr0 &= ~CLKRP;
588
589 if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
590 mcbsp_cfg.pcr0 &= ~CLKXP;
591 else
592 mcbsp_cfg.pcr0 |= CLKXP;
593
594 /* Set SCLKME to 0 and CLKSM to 1 */
595 mcbsp_cfg.pcr0 &= ~SCLKME;
596 mcbsp_cfg.srgr2 |= CLKSM;
597
598 /* Set FSXP */
599 if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
600 mcbsp_cfg.pcr0 &= ~FSXP;
601 else
602 mcbsp_cfg.pcr0 |= FSXP;
603
604 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
605 mcbsp_cfg.pcr0 |= CLKXM;
606 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div -1);
607 mcbsp_cfg.pcr0 |= FSXM;
608 mcbsp_cfg.srgr2 &= ~FSGM;
609 mcbsp_cfg.xcr2 |= XDATDLY(1);
610 mcbsp_cfg.rcr2 |= RDATDLY(1);
611 }
612 else {
613 mcbsp_cfg.pcr0 &= ~CLKXM;
614 mcbsp_cfg.srgr1 |= CLKGDV(1);
615 mcbsp_cfg.pcr0 &= ~FSXM;
616 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
617 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
618 }
619
620 mcbsp_cfg.xcr2 &= ~XPHASE;
621 mcbsp_cfg.rcr2 &= ~RPHASE;
622
623 omap_mcbsp_config(id, &mcbsp_cfg);
624}
625
626
627/*
628 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
629 * 730 has only 2 McBSP, and both of them are MPU peripherals.
630 */
631struct omap_mcbsp_info {
632 u32 virt_base;
633 u8 dma_rx_sync, dma_tx_sync;
634 u16 rx_irq, tx_irq;
635};
636
637#ifdef CONFIG_ARCH_OMAP730
638static const struct omap_mcbsp_info mcbsp_730[] = {
639 [0] = { .virt_base = io_p2v(OMAP730_MCBSP1_BASE),
640 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
641 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
642 .rx_irq = INT_730_McBSP1RX,
643 .tx_irq = INT_730_McBSP1TX },
644 [1] = { .virt_base = io_p2v(OMAP730_MCBSP2_BASE),
645 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
646 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
647 .rx_irq = INT_730_McBSP2RX,
648 .tx_irq = INT_730_McBSP2TX },
649};
650#endif
651
1a8bfa1e 652#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 653static const struct omap_mcbsp_info mcbsp_1510[] = {
654 [0] = { .virt_base = OMAP1510_MCBSP1_BASE,
655 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
656 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
657 .rx_irq = INT_McBSP1RX,
658 .tx_irq = INT_McBSP1TX },
659 [1] = { .virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
660 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
661 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
662 .rx_irq = INT_1510_SPI_RX,
663 .tx_irq = INT_1510_SPI_TX },
664 [2] = { .virt_base = OMAP1510_MCBSP3_BASE,
665 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
666 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
667 .rx_irq = INT_McBSP3RX,
668 .tx_irq = INT_McBSP3TX },
669};
670#endif
671
672#if defined(CONFIG_ARCH_OMAP16XX)
673static const struct omap_mcbsp_info mcbsp_1610[] = {
674 [0] = { .virt_base = OMAP1610_MCBSP1_BASE,
675 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
676 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
677 .rx_irq = INT_McBSP1RX,
678 .tx_irq = INT_McBSP1TX },
679 [1] = { .virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
680 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
681 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
682 .rx_irq = INT_1610_McBSP2_RX,
683 .tx_irq = INT_1610_McBSP2_TX },
684 [2] = { .virt_base = OMAP1610_MCBSP3_BASE,
685 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
686 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
687 .rx_irq = INT_McBSP3RX,
688 .tx_irq = INT_McBSP3TX },
689};
690#endif
691
692static int __init omap_mcbsp_init(void)
693{
694 int mcbsp_count = 0, i;
695 static const struct omap_mcbsp_info *mcbsp_info;
696
697 printk("Initializing OMAP McBSP system\n");
698
699 mcbsp_dsp_ck = clk_get(0, "dsp_ck");
700 if (IS_ERR(mcbsp_dsp_ck)) {
701 printk(KERN_ERR "mcbsp: could not acquire dsp_ck handle.\n");
702 return PTR_ERR(mcbsp_dsp_ck);
703 }
704 mcbsp_api_ck = clk_get(0, "api_ck");
bb13b5fd 705 if (IS_ERR(mcbsp_api_ck)) {
5e1c5ff4
TL		 706 printk(KERN_ERR "mcbsp: could not acquire api_ck handle.\n");
707 return PTR_ERR(mcbsp_api_ck);
708 }
bb13b5fd
TL		 709 mcbsp_dspxor_ck = clk_get(0, "dspxor_ck");
710 if (IS_ERR(mcbsp_dspxor_ck)) {
711 printk(KERN_ERR "mcbsp: could not acquire dspxor_ck handle.\n");
712 return PTR_ERR(mcbsp_dspxor_ck);
713 }
5e1c5ff4
TL		 714
715#ifdef CONFIG_ARCH_OMAP730
716 if (cpu_is_omap730()) {
717 mcbsp_info = mcbsp_730;
718 mcbsp_count = ARRAY_SIZE(mcbsp_730);
719 }
720#endif
1a8bfa1e 721#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 722 if (cpu_is_omap1510()) {
723 mcbsp_info = mcbsp_1510;
724 mcbsp_count = ARRAY_SIZE(mcbsp_1510);
725 }
726#endif
727#if defined(CONFIG_ARCH_OMAP16XX)
bb13b5fd 728 if (cpu_is_omap16xx()) {
5e1c5ff4
TL		 729 mcbsp_info = mcbsp_1610;
730 mcbsp_count = ARRAY_SIZE(mcbsp_1610);
731 }
732#endif
733 for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) {
734 if (i >= mcbsp_count) {
735 mcbsp[i].io_base = 0;
736 mcbsp[i].free = 0;
737 continue;
738 }
739 mcbsp[i].id = i + 1;
740 mcbsp[i].free = 1;
741 mcbsp[i].dma_tx_lch = -1;
742 mcbsp[i].dma_rx_lch = -1;
743
744 mcbsp[i].io_base = mcbsp_info[i].virt_base;
745 mcbsp[i].tx_irq = mcbsp_info[i].tx_irq;
746 mcbsp[i].rx_irq = mcbsp_info[i].rx_irq;
747 mcbsp[i].dma_rx_sync = mcbsp_info[i].dma_rx_sync;
748 mcbsp[i].dma_tx_sync = mcbsp_info[i].dma_tx_sync;
749 spin_lock_init(&mcbsp[i].lock);
750 }
751
752 return 0;
753}
754
755
756arch_initcall(omap_mcbsp_init);
757
758EXPORT_SYMBOL(omap_mcbsp_config);
759EXPORT_SYMBOL(omap_mcbsp_request);
760EXPORT_SYMBOL(omap_mcbsp_free);
761EXPORT_SYMBOL(omap_mcbsp_start);
762EXPORT_SYMBOL(omap_mcbsp_stop);
763EXPORT_SYMBOL(omap_mcbsp_xmit_word);
764EXPORT_SYMBOL(omap_mcbsp_recv_word);
765EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
766EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
767EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
Linux kernel - Deliverables
This page took 0.088919 seconds and 5 git commands to generate.