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omap: mcbsp: Drop SPI mode support
[deliverable/linux.git] / arch / arm / plat-omap / mcbsp.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/mcbsp.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Multichannel mode not supported.
13 */
14
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/device.h>
bc5d0c89 18#include <linux/platform_device.h>
5e1c5ff4
TL		 19#include <linux/wait.h>
20#include <linux/completion.h>
21#include <linux/interrupt.h>
22#include <linux/err.h>
f8ce2547 23#include <linux/clk.h>
04fbf6a2 24#include <linux/delay.h>
fb78d808 25#include <linux/io.h>
5a0e3ad6 26#include <linux/slab.h>
5e1c5ff4 27
ce491cf8
TL		 28#include <plat/dma.h>
29#include <plat/mcbsp.h>
f36d01d6 30#include <plat/omap_device.h>
e95496d4 31#include <linux/pm_runtime.h>
5e1c5ff4 32
59fb659b
PW		 33/* XXX These "sideways" includes are a sign that something is wrong */
34#include "../mach-omap2/cm2xxx_3xxx.h"
d912fa92
EN		 35#include "../mach-omap2/cm-regbits-34xx.h"
36
b4b58f58 37struct omap_mcbsp **mcbsp_ptr;
c8c99699 38int omap_mcbsp_count, omap_mcbsp_cache_size;
bc5d0c89 39
b0a330dc 40static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
b4b58f58 41{
c8c99699
JK		 42 if (cpu_class_is_omap1()) {
43 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
8ea3200f 44 __raw_writew((u16)val, mcbsp->io_base + reg);
c8c99699
JK		 45 } else if (cpu_is_omap2420()) {
46 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
47 __raw_writew((u16)val, mcbsp->io_base + reg);
48 } else {
49 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
8ea3200f 50 __raw_writel(val, mcbsp->io_base + reg);
c8c99699 51 }
b4b58f58
CS		 52}
53
b0a330dc 54static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
b4b58f58 55{
c8c99699
JK		 56 if (cpu_class_is_omap1()) {
57 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
58 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
59 } else if (cpu_is_omap2420()) {
60 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
61 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
62 } else {
63 return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
64 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
65 }
b4b58f58
CS		 66}
67
d912fa92 68#ifdef CONFIG_ARCH_OMAP3
b0a330dc 69static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
d912fa92
EN		 70{
71 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
72}
73
b0a330dc 74static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
d912fa92
EN		 75{
76 return __raw_readl(mcbsp->st_data->io_base_st + reg);
77}
78#endif
79
8ea3200f 80#define MCBSP_READ(mcbsp, reg) \
c8c99699 81 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
8ea3200f
JK		 82#define MCBSP_WRITE(mcbsp, reg, val) \
83 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
c8c99699
JK		 84#define MCBSP_READ_CACHE(mcbsp, reg) \
85 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
b4b58f58 86
d912fa92
EN		 87#define MCBSP_ST_READ(mcbsp, reg) \
88 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
89#define MCBSP_ST_WRITE(mcbsp, reg, val) \
90 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
91
5e1c5ff4
TL		 92static void omap_mcbsp_dump_reg(u8 id)
93{
b4b58f58
CS		 94 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
95
96 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
97 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
8ea3200f 98 MCBSP_READ(mcbsp, DRR2));
b4b58f58 99 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
8ea3200f 100 MCBSP_READ(mcbsp, DRR1));
b4b58f58 101 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
8ea3200f 102 MCBSP_READ(mcbsp, DXR2));
b4b58f58 103 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
8ea3200f 104 MCBSP_READ(mcbsp, DXR1));
b4b58f58 105 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
8ea3200f 106 MCBSP_READ(mcbsp, SPCR2));
b4b58f58 107 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
8ea3200f 108 MCBSP_READ(mcbsp, SPCR1));
b4b58f58 109 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
8ea3200f 110 MCBSP_READ(mcbsp, RCR2));
b4b58f58 111 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
8ea3200f 112 MCBSP_READ(mcbsp, RCR1));
b4b58f58 113 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
8ea3200f 114 MCBSP_READ(mcbsp, XCR2));
b4b58f58 115 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
8ea3200f 116 MCBSP_READ(mcbsp, XCR1));
b4b58f58 117 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
8ea3200f 118 MCBSP_READ(mcbsp, SRGR2));
b4b58f58 119 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
8ea3200f 120 MCBSP_READ(mcbsp, SRGR1));
b4b58f58 121 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
8ea3200f 122 MCBSP_READ(mcbsp, PCR0));
b4b58f58 123 dev_dbg(mcbsp->dev, "***********************\n");
5e1c5ff4
TL		 124}
125
0cd61b68 126static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
5e1c5ff4 127{
e8f2af17 128 struct omap_mcbsp *mcbsp_tx = dev_id;
d6d834b0 129 u16 irqst_spcr2;
5e1c5ff4 130
8ea3200f 131 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
d6d834b0 132 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
5e1c5ff4 133
d6d834b0
EN		 134 if (irqst_spcr2 & XSYNC_ERR) {
135 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
136 irqst_spcr2);
137 /* Writing zero to XSYNC_ERR clears the IRQ */
0841cb82 138 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
d6d834b0
EN		 139 } else {
140 complete(&mcbsp_tx->tx_irq_completion);
141 }
fb78d808 142
5e1c5ff4
TL		 143 return IRQ_HANDLED;
144}
145
0cd61b68 146static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
5e1c5ff4 147{
e8f2af17 148 struct omap_mcbsp *mcbsp_rx = dev_id;
d6d834b0
EN		 149 u16 irqst_spcr1;
150
8ea3200f 151 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
d6d834b0
EN		 152 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
153
154 if (irqst_spcr1 & RSYNC_ERR) {
155 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
156 irqst_spcr1);
157 /* Writing zero to RSYNC_ERR clears the IRQ */
0841cb82 158 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
d6d834b0 159 } else {
cb922d25 160 complete(&mcbsp_rx->rx_irq_completion);
d6d834b0 161 }
fb78d808 162
5e1c5ff4
TL		 163 return IRQ_HANDLED;
164}
165
5e1c5ff4
TL		 166static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
167{
e8f2af17 168 struct omap_mcbsp *mcbsp_dma_tx = data;
5e1c5ff4 169
bc5d0c89 170 dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
8ea3200f 171 MCBSP_READ(mcbsp_dma_tx, SPCR2));
5e1c5ff4
TL		 172
173 /* We can free the channels */
174 omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
175 mcbsp_dma_tx->dma_tx_lch = -1;
176
177 complete(&mcbsp_dma_tx->tx_dma_completion);
178}
179
180static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
181{
e8f2af17 182 struct omap_mcbsp *mcbsp_dma_rx = data;
5e1c5ff4 183
bc5d0c89 184 dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
8ea3200f 185 MCBSP_READ(mcbsp_dma_rx, SPCR2));
5e1c5ff4
TL		 186
187 /* We can free the channels */
188 omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
189 mcbsp_dma_rx->dma_rx_lch = -1;
190
191 complete(&mcbsp_dma_rx->rx_dma_completion);
192}
193
5e1c5ff4
TL		 194/*
195 * omap_mcbsp_config simply write a config to the
196 * appropriate McBSP.
197 * You either call this function or set the McBSP registers
198 * by yourself before calling omap_mcbsp_start().
199 */
fb78d808 200void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
5e1c5ff4 201{
b4b58f58 202 struct omap_mcbsp *mcbsp;
5e1c5ff4 203
bc5d0c89
EV		 204 if (!omap_mcbsp_check_valid_id(id)) {
205 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
206 return;
207 }
b4b58f58 208 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 209
b4b58f58
CS		 210 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
211 mcbsp->id, mcbsp->phys_base);
5e1c5ff4
TL		 212
213 /* We write the given config */
8ea3200f
JK		 214 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
215 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
216 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
217 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
218 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
219 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
220 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
221 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
222 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
223 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
224 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
a5b92cc3 225 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
8ea3200f
JK		 226 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
227 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
3127f8f8 228 }
5e1c5ff4 229}
fb78d808 230EXPORT_SYMBOL(omap_mcbsp_config);
5e1c5ff4 231
9504ba64
KVA		 232/**
233 * omap_mcbsp_dma_params - returns the dma channel number
234 * @id - mcbsp id
235 * @stream - indicates the direction of data flow (rx or tx)
236 *
237 * Returns the dma channel number for the rx channel or tx channel
238 * based on the value of @stream for the requested mcbsp given by @id
239 */
240int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream)
241{
242 struct omap_mcbsp *mcbsp;
243
244 if (!omap_mcbsp_check_valid_id(id)) {
245 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
246 return -ENODEV;
247 }
248 mcbsp = id_to_mcbsp_ptr(id);
249
250 if (stream)
251 return mcbsp->dma_rx_sync;
252 else
253 return mcbsp->dma_tx_sync;
254}
255EXPORT_SYMBOL(omap_mcbsp_dma_ch_params);
256
257/**
258 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
259 * @id - mcbsp id
260 * @stream - indicates the direction of data flow (rx or tx)
261 *
262 * Returns the address of mcbsp data transmit register or data receive register
263 * to be used by DMA for transferring/receiving data based on the value of
264 * @stream for the requested mcbsp given by @id
265 */
266int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
267{
268 struct omap_mcbsp *mcbsp;
269 int data_reg;
270
271 if (!omap_mcbsp_check_valid_id(id)) {
272 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
273 return -ENODEV;
274 }
275 mcbsp = id_to_mcbsp_ptr(id);
276
277 data_reg = mcbsp->phys_dma_base;
278
279 if (mcbsp->mcbsp_config_type < MCBSP_CONFIG_TYPE2) {
280 if (stream)
281 data_reg += OMAP_MCBSP_REG_DRR1;
282 else
283 data_reg += OMAP_MCBSP_REG_DXR1;
284 } else {
285 if (stream)
286 data_reg += OMAP_MCBSP_REG_DRR;
287 else
288 data_reg += OMAP_MCBSP_REG_DXR;
289 }
290
291 return data_reg;
292}
293EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
294
a8eb7ca0 295#ifdef CONFIG_ARCH_OMAP3
f36d01d6
KVA		 296static struct omap_device *find_omap_device_by_dev(struct device *dev)
297{
298 struct platform_device *pdev = container_of(dev,
299 struct platform_device, dev);
300 return container_of(pdev, struct omap_device, pdev);
301}
302
d912fa92
EN		 303static void omap_st_on(struct omap_mcbsp *mcbsp)
304{
305 unsigned int w;
f36d01d6
KVA		 306 struct omap_device *od;
307
308 od = find_omap_device_by_dev(mcbsp->dev);
d912fa92
EN		 309
310 /*
311 * Sidetone uses McBSP ICLK - which must not idle when sidetones
312 * are enabled or sidetones start sounding ugly.
313 */
c4d7e58f 314 w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
d912fa92 315 w &= ~(1 << (mcbsp->id - 2));
c4d7e58f 316 omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
d912fa92
EN		 317
318 /* Enable McBSP Sidetone */
319 w = MCBSP_READ(mcbsp, SSELCR);
320 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
321
d912fa92
EN		 322 /* Enable Sidetone from Sidetone Core */
323 w = MCBSP_ST_READ(mcbsp, SSELCR);
324 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
325}
326
327static void omap_st_off(struct omap_mcbsp *mcbsp)
328{
329 unsigned int w;
f36d01d6
KVA		 330 struct omap_device *od;
331
332 od = find_omap_device_by_dev(mcbsp->dev);
d912fa92
EN		 333
334 w = MCBSP_ST_READ(mcbsp, SSELCR);
335 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
336
d912fa92
EN		 337 w = MCBSP_READ(mcbsp, SSELCR);
338 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
339
c4d7e58f 340 w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
d912fa92 341 w |= 1 << (mcbsp->id - 2);
c4d7e58f 342 omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
d912fa92
EN		 343}
344
345static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
346{
347 u16 val, i;
f36d01d6 348 struct omap_device *od;
d912fa92 349
f36d01d6 350 od = find_omap_device_by_dev(mcbsp->dev);
d912fa92
EN		 351
352 val = MCBSP_ST_READ(mcbsp, SSELCR);
353
354 if (val & ST_COEFFWREN)
355 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
356
357 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
358
359 for (i = 0; i < 128; i++)
360 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
361
362 i = 0;
363
364 val = MCBSP_ST_READ(mcbsp, SSELCR);
365 while (!(val & ST_COEFFWRDONE) && (++i < 1000))
366 val = MCBSP_ST_READ(mcbsp, SSELCR);
367
368 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
369
370 if (i == 1000)
371 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
372}
373
374static void omap_st_chgain(struct omap_mcbsp *mcbsp)
375{
376 u16 w;
377 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
f36d01d6 378 struct omap_device *od;
d912fa92 379
f36d01d6 380 od = find_omap_device_by_dev(mcbsp->dev);
d912fa92
EN		 381
382 w = MCBSP_ST_READ(mcbsp, SSELCR);
383
384 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
385 ST_CH1GAIN(st_data->ch1gain));
386}
387
388int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
389{
390 struct omap_mcbsp *mcbsp;
391 struct omap_mcbsp_st_data *st_data;
392 int ret = 0;
393
394 if (!omap_mcbsp_check_valid_id(id)) {
395 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
396 return -ENODEV;
397 }
398
399 mcbsp = id_to_mcbsp_ptr(id);
400 st_data = mcbsp->st_data;
401
402 if (!st_data)
403 return -ENOENT;
404
405 spin_lock_irq(&mcbsp->lock);
406 if (channel == 0)
407 st_data->ch0gain = chgain;
408 else if (channel == 1)
409 st_data->ch1gain = chgain;
410 else
411 ret = -EINVAL;
412
413 if (st_data->enabled)
414 omap_st_chgain(mcbsp);
415 spin_unlock_irq(&mcbsp->lock);
416
417 return ret;
418}
419EXPORT_SYMBOL(omap_st_set_chgain);
420
421int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
422{
423 struct omap_mcbsp *mcbsp;
424 struct omap_mcbsp_st_data *st_data;
425 int ret = 0;
426
427 if (!omap_mcbsp_check_valid_id(id)) {
428 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
429 return -ENODEV;
430 }
431
432 mcbsp = id_to_mcbsp_ptr(id);
433 st_data = mcbsp->st_data;
434
435 if (!st_data)
436 return -ENOENT;
437
438 spin_lock_irq(&mcbsp->lock);
439 if (channel == 0)
440 *chgain = st_data->ch0gain;
441 else if (channel == 1)
442 *chgain = st_data->ch1gain;
443 else
444 ret = -EINVAL;
445 spin_unlock_irq(&mcbsp->lock);
446
447 return ret;
448}
449EXPORT_SYMBOL(omap_st_get_chgain);
450
451static int omap_st_start(struct omap_mcbsp *mcbsp)
452{
453 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
454
455 if (st_data && st_data->enabled && !st_data->running) {
456 omap_st_fir_write(mcbsp, st_data->taps);
457 omap_st_chgain(mcbsp);
458
459 if (!mcbsp->free) {
460 omap_st_on(mcbsp);
461 st_data->running = 1;
462 }
463 }
464
465 return 0;
466}
467
468int omap_st_enable(unsigned int id)
469{
470 struct omap_mcbsp *mcbsp;
471 struct omap_mcbsp_st_data *st_data;
472
473 if (!omap_mcbsp_check_valid_id(id)) {
474 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
475 return -ENODEV;
476 }
477
478 mcbsp = id_to_mcbsp_ptr(id);
479 st_data = mcbsp->st_data;
480
481 if (!st_data)
482 return -ENODEV;
483
484 spin_lock_irq(&mcbsp->lock);
485 st_data->enabled = 1;
486 omap_st_start(mcbsp);
487 spin_unlock_irq(&mcbsp->lock);
488
489 return 0;
490}
491EXPORT_SYMBOL(omap_st_enable);
492
493static int omap_st_stop(struct omap_mcbsp *mcbsp)
494{
495 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
496
497 if (st_data && st_data->running) {
498 if (!mcbsp->free) {
499 omap_st_off(mcbsp);
500 st_data->running = 0;
501 }
502 }
503
504 return 0;
505}
506
507int omap_st_disable(unsigned int id)
508{
509 struct omap_mcbsp *mcbsp;
510 struct omap_mcbsp_st_data *st_data;
511 int ret = 0;
512
513 if (!omap_mcbsp_check_valid_id(id)) {
514 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
515 return -ENODEV;
516 }
517
518 mcbsp = id_to_mcbsp_ptr(id);
519 st_data = mcbsp->st_data;
520
521 if (!st_data)
522 return -ENODEV;
523
524 spin_lock_irq(&mcbsp->lock);
525 omap_st_stop(mcbsp);
526 st_data->enabled = 0;
527 spin_unlock_irq(&mcbsp->lock);
528
529 return ret;
530}
531EXPORT_SYMBOL(omap_st_disable);
532
533int omap_st_is_enabled(unsigned int id)
534{
535 struct omap_mcbsp *mcbsp;
536 struct omap_mcbsp_st_data *st_data;
537
538 if (!omap_mcbsp_check_valid_id(id)) {
539 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
540 return -ENODEV;
541 }
542
543 mcbsp = id_to_mcbsp_ptr(id);
544 st_data = mcbsp->st_data;
545
546 if (!st_data)
547 return -ENODEV;
548
549
550 return st_data->enabled;
551}
552EXPORT_SYMBOL(omap_st_is_enabled);
553
7aa9ff56 554/*
451fd82d
PU		 555 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
556 * The threshold parameter is 1 based, and it is converted (threshold - 1)
557 * for the THRSH2 register.
7aa9ff56
EV		 558 */
559void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
560{
561 struct omap_mcbsp *mcbsp;
7aa9ff56 562
752ec2f2 563 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
7aa9ff56
EV		 564 return;
565
566 if (!omap_mcbsp_check_valid_id(id)) {
567 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
568 return;
569 }
570 mcbsp = id_to_mcbsp_ptr(id);
7aa9ff56 571
451fd82d
PU		 572 if (threshold && threshold <= mcbsp->max_tx_thres)
573 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
7aa9ff56
EV		 574}
575EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
576
577/*
451fd82d
PU		 578 * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
579 * The threshold parameter is 1 based, and it is converted (threshold - 1)
580 * for the THRSH1 register.
7aa9ff56
EV		 581 */
582void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
583{
584 struct omap_mcbsp *mcbsp;
7aa9ff56 585
752ec2f2 586 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
7aa9ff56
EV		 587 return;
588
589 if (!omap_mcbsp_check_valid_id(id)) {
590 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
591 return;
592 }
593 mcbsp = id_to_mcbsp_ptr(id);
7aa9ff56 594
451fd82d
PU		 595 if (threshold && threshold <= mcbsp->max_rx_thres)
596 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
7aa9ff56
EV		 597}
598EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
a1a56f5f
EV		 599
600/*
601 * omap_mcbsp_get_max_tx_thres just return the current configured
602 * maximum threshold for transmission
603 */
604u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
605{
606 struct omap_mcbsp *mcbsp;
607
608 if (!omap_mcbsp_check_valid_id(id)) {
609 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
610 return -ENODEV;
611 }
612 mcbsp = id_to_mcbsp_ptr(id);
613
614 return mcbsp->max_tx_thres;
615}
616EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
617
618/*
619 * omap_mcbsp_get_max_rx_thres just return the current configured
620 * maximum threshold for reception
621 */
622u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
623{
624 struct omap_mcbsp *mcbsp;
625
626 if (!omap_mcbsp_check_valid_id(id)) {
627 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
628 return -ENODEV;
629 }
630 mcbsp = id_to_mcbsp_ptr(id);
631
632 return mcbsp->max_rx_thres;
633}
634EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
98cb20e8 635
0acce82b
PU		 636u16 omap_mcbsp_get_fifo_size(unsigned int id)
637{
638 struct omap_mcbsp *mcbsp;
639
640 if (!omap_mcbsp_check_valid_id(id)) {
641 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
642 return -ENODEV;
643 }
644 mcbsp = id_to_mcbsp_ptr(id);
645
646 return mcbsp->pdata->buffer_size;
647}
648EXPORT_SYMBOL(omap_mcbsp_get_fifo_size);
649
7dc976ed
PU		 650/*
651 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
652 */
653u16 omap_mcbsp_get_tx_delay(unsigned int id)
654{
655 struct omap_mcbsp *mcbsp;
656 u16 buffstat;
657
658 if (!omap_mcbsp_check_valid_id(id)) {
659 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
660 return -ENODEV;
661 }
662 mcbsp = id_to_mcbsp_ptr(id);
663
664 /* Returns the number of free locations in the buffer */
665 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
666
667 /* Number of slots are different in McBSP ports */
f10b8ad1 668 return mcbsp->pdata->buffer_size - buffstat;
7dc976ed
PU		 669}
670EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
671
672/*
673 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
674 * to reach the threshold value (when the DMA will be triggered to read it)
675 */
676u16 omap_mcbsp_get_rx_delay(unsigned int id)
677{
678 struct omap_mcbsp *mcbsp;
679 u16 buffstat, threshold;
680
681 if (!omap_mcbsp_check_valid_id(id)) {
682 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
683 return -ENODEV;
684 }
685 mcbsp = id_to_mcbsp_ptr(id);
686
687 /* Returns the number of used locations in the buffer */
688 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
689 /* RX threshold */
690 threshold = MCBSP_READ(mcbsp, THRSH1);
691
692 /* Return the number of location till we reach the threshold limit */
693 if (threshold <= buffstat)
694 return 0;
695 else
696 return threshold - buffstat;
697}
698EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
699
98cb20e8
PU		 700/*
701 * omap_mcbsp_get_dma_op_mode just return the current configured
702 * operating mode for the mcbsp channel
703 */
704int omap_mcbsp_get_dma_op_mode(unsigned int id)
705{
706 struct omap_mcbsp *mcbsp;
707 int dma_op_mode;
708
709 if (!omap_mcbsp_check_valid_id(id)) {
710 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
711 return -ENODEV;
712 }
713 mcbsp = id_to_mcbsp_ptr(id);
714
98cb20e8 715 dma_op_mode = mcbsp->dma_op_mode;
98cb20e8
PU		 716
717 return dma_op_mode;
718}
719EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
2122fdc6
EN		 720
721static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
722{
f36d01d6
KVA		 723 struct omap_device *od;
724
725 od = find_omap_device_by_dev(mcbsp->dev);
2122fdc6
EN		 726 /*
727 * Enable wakup behavior, smart idle and all wakeups
728 * REVISIT: some wakeups may be unnecessary
729 */
752ec2f2 730 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
f36d01d6 731 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
2122fdc6
EN		 732 }
733}
734
735static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
736{
f36d01d6
KVA		 737 struct omap_device *od;
738
739 od = find_omap_device_by_dev(mcbsp->dev);
740
2122fdc6
EN		 741 /*
742 * Disable wakup behavior, smart idle and all wakeups
743 */
752ec2f2 744 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
72cc6d71
EN		 745 /*
746 * HW bug workaround - If no_idle mode is taken, we need to
747 * go to smart_idle before going to always_idle, or the
748 * device will not hit retention anymore.
749 */
2122fdc6 750
8ea3200f 751 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
2122fdc6
EN		 752 }
753}
754#else
755static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
756static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
d912fa92
EN		 757static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
758static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
7aa9ff56
EV		 759#endif
760
120db2cb
TL		 761/*
762 * We can choose between IRQ based or polled IO.
763 * This needs to be called before omap_mcbsp_request().
764 */
765int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
766{
b4b58f58
CS		 767 struct omap_mcbsp *mcbsp;
768
bc5d0c89
EV		 769 if (!omap_mcbsp_check_valid_id(id)) {
770 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
771 return -ENODEV;
772 }
b4b58f58 773 mcbsp = id_to_mcbsp_ptr(id);
120db2cb 774
b4b58f58 775 spin_lock(&mcbsp->lock);
120db2cb 776
b4b58f58
CS		 777 if (!mcbsp->free) {
778 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
779 mcbsp->id);
780 spin_unlock(&mcbsp->lock);
120db2cb
TL		 781 return -EINVAL;
782 }
783
b4b58f58 784 mcbsp->io_type = io_type;
120db2cb 785
b4b58f58 786 spin_unlock(&mcbsp->lock);
120db2cb
TL		 787
788 return 0;
789}
fb78d808 790EXPORT_SYMBOL(omap_mcbsp_set_io_type);
5e1c5ff4 791
5e1c5ff4
TL		 792int omap_mcbsp_request(unsigned int id)
793{
b4b58f58 794 struct omap_mcbsp *mcbsp;
c8c99699 795 void *reg_cache;
5e1c5ff4
TL		 796 int err;
797
bc5d0c89
EV		 798 if (!omap_mcbsp_check_valid_id(id)) {
799 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
800 return -ENODEV;
120db2cb 801 }
b4b58f58 802 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 803
c8c99699
JK		 804 reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
805 if (!reg_cache) {
806 return -ENOMEM;
807 }
808
b4b58f58
CS		 809 spin_lock(&mcbsp->lock);
810 if (!mcbsp->free) {
811 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
812 mcbsp->id);
c8c99699
JK		 813 err = -EBUSY;
814 goto err_kfree;
5e1c5ff4
TL		 815 }
816
6722a723 817 mcbsp->free = false;
c8c99699 818 mcbsp->reg_cache = reg_cache;
b4b58f58 819 spin_unlock(&mcbsp->lock);
5e1c5ff4 820
b820ce4e
RK		 821 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
822 mcbsp->pdata->ops->request(id);
823
e95496d4 824 pm_runtime_get_sync(mcbsp->dev);
b820ce4e 825
2122fdc6
EN		 826 /* Do procedure specific to omap34xx arch, if applicable */
827 omap34xx_mcbsp_request(mcbsp);
828
5a07055a
JN		 829 /*
830 * Make sure that transmitter, receiver and sample-rate generator are
831 * not running before activating IRQs.
832 */
8ea3200f
JK		 833 MCBSP_WRITE(mcbsp, SPCR1, 0);
834 MCBSP_WRITE(mcbsp, SPCR2, 0);
5a07055a 835
b4b58f58 836 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
120db2cb 837 /* We need to get IRQs here */
5a07055a 838 init_completion(&mcbsp->tx_irq_completion);
b4b58f58
CS		 839 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
840 0, "McBSP", (void *)mcbsp);
120db2cb 841 if (err != 0) {
b4b58f58
CS		 842 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
843 "for McBSP%d\n", mcbsp->tx_irq,
844 mcbsp->id);
c8c99699 845 goto err_clk_disable;
120db2cb 846 }
5e1c5ff4 847
9319b9da
JEC		 848 if (mcbsp->rx_irq) {
849 init_completion(&mcbsp->rx_irq_completion);
850 err = request_irq(mcbsp->rx_irq,
851 omap_mcbsp_rx_irq_handler,
b4b58f58 852 0, "McBSP", (void *)mcbsp);
9319b9da
JEC		 853 if (err != 0) {
854 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
855 "for McBSP%d\n", mcbsp->rx_irq,
856 mcbsp->id);
857 goto err_free_irq;
858 }
120db2cb 859 }
5e1c5ff4
TL		 860 }
861
5e1c5ff4 862 return 0;
c8c99699 863err_free_irq:
1866b545 864 free_irq(mcbsp->tx_irq, (void *)mcbsp);
c8c99699 865err_clk_disable:
1866b545 866 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
c8c99699 867 mcbsp->pdata->ops->free(id);
1866b545
JK		 868
869 /* Do procedure specific to omap34xx arch, if applicable */
870 omap34xx_mcbsp_free(mcbsp);
871
e95496d4 872 pm_runtime_put_sync(mcbsp->dev);
1866b545 873
c8c99699 874 spin_lock(&mcbsp->lock);
6722a723 875 mcbsp->free = true;
c8c99699
JK		 876 mcbsp->reg_cache = NULL;
877err_kfree:
878 spin_unlock(&mcbsp->lock);
879 kfree(reg_cache);
1866b545
JK		 880
881 return err;
5e1c5ff4 882}
fb78d808 883EXPORT_SYMBOL(omap_mcbsp_request);
5e1c5ff4
TL		 884
885void omap_mcbsp_free(unsigned int id)
886{
b4b58f58 887 struct omap_mcbsp *mcbsp;
c8c99699 888 void *reg_cache;
b4b58f58 889
bc5d0c89
EV		 890 if (!omap_mcbsp_check_valid_id(id)) {
891 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 892 return;
120db2cb 893 }
b4b58f58 894 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 895
b4b58f58
CS		 896 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
897 mcbsp->pdata->ops->free(id);
bc5d0c89 898
2122fdc6
EN		 899 /* Do procedure specific to omap34xx arch, if applicable */
900 omap34xx_mcbsp_free(mcbsp);
901
e95496d4 902 pm_runtime_put_sync(mcbsp->dev);
b820ce4e
RK		 903
904 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
905 /* Free IRQs */
9319b9da
JEC		 906 if (mcbsp->rx_irq)
907 free_irq(mcbsp->rx_irq, (void *)mcbsp);
b820ce4e
RK		 908 free_irq(mcbsp->tx_irq, (void *)mcbsp);
909 }
5e1c5ff4 910
c8c99699 911 reg_cache = mcbsp->reg_cache;
5e1c5ff4 912
c8c99699
JK		 913 spin_lock(&mcbsp->lock);
914 if (mcbsp->free)
915 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
916 else
6722a723 917 mcbsp->free = true;
c8c99699 918 mcbsp->reg_cache = NULL;
b4b58f58 919 spin_unlock(&mcbsp->lock);
c8c99699
JK		 920
921 if (reg_cache)
922 kfree(reg_cache);
5e1c5ff4 923}
fb78d808 924EXPORT_SYMBOL(omap_mcbsp_free);
5e1c5ff4
TL		 925
926/*
c12abc01
JN		 927 * Here we start the McBSP, by enabling transmitter, receiver or both.
928 * If no transmitter or receiver is active prior calling, then sample-rate
929 * generator and frame sync are started.
5e1c5ff4 930 */
c12abc01 931void omap_mcbsp_start(unsigned int id, int tx, int rx)
5e1c5ff4 932{
b4b58f58 933 struct omap_mcbsp *mcbsp;
ce3f054b 934 int enable_srg = 0;
5e1c5ff4
TL		 935 u16 w;
936
bc5d0c89
EV		 937 if (!omap_mcbsp_check_valid_id(id)) {
938 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 939 return;
bc5d0c89 940 }
b4b58f58 941 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 942
d912fa92
EN		 943 if (cpu_is_omap34xx())
944 omap_st_start(mcbsp);
945
96fbd745
JK		 946 mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
947 mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
5e1c5ff4 948
ce3f054b
PU		 949 /* Only enable SRG, if McBSP is master */
950 w = MCBSP_READ_CACHE(mcbsp, PCR0);
951 if (w & (FSXM | FSRM | CLKXM | CLKRM))
952 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
953 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
c12abc01 954
ce3f054b 955 if (enable_srg) {
c12abc01 956 /* Start the sample generator */
96fbd745 957 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 958 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
c12abc01 959 }
5e1c5ff4
TL		 960
961 /* Enable transmitter and receiver */
d09a2afc 962 tx &= 1;
96fbd745 963 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 964 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
5e1c5ff4 965
d09a2afc 966 rx &= 1;
96fbd745 967 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
8ea3200f 968 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
5e1c5ff4 969
44a6311c
EV		 970 /*
971 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
972 * REVISIT: 100us may give enough time for two CLKSRG, however
973 * due to some unknown PM related, clock gating etc. reason it
974 * is now at 500us.
975 */
976 udelay(500);
5e1c5ff4 977
ce3f054b 978 if (enable_srg) {
c12abc01 979 /* Start frame sync */
96fbd745 980 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 981 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
c12abc01 982 }
5e1c5ff4 983
752ec2f2 984 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
d09a2afc 985 /* Release the transmitter and receiver */
96fbd745 986 w = MCBSP_READ_CACHE(mcbsp, XCCR);
d09a2afc 987 w &= ~(tx ? XDISABLE : 0);
8ea3200f 988 MCBSP_WRITE(mcbsp, XCCR, w);
96fbd745 989 w = MCBSP_READ_CACHE(mcbsp, RCCR);
d09a2afc 990 w &= ~(rx ? RDISABLE : 0);
8ea3200f 991 MCBSP_WRITE(mcbsp, RCCR, w);
d09a2afc
JN		 992 }
993
5e1c5ff4
TL		 994 /* Dump McBSP Regs */
995 omap_mcbsp_dump_reg(id);
5e1c5ff4 996}
fb78d808 997EXPORT_SYMBOL(omap_mcbsp_start);
5e1c5ff4 998
c12abc01 999void omap_mcbsp_stop(unsigned int id, int tx, int rx)
5e1c5ff4 1000{
b4b58f58 1001 struct omap_mcbsp *mcbsp;
c12abc01 1002 int idle;
5e1c5ff4
TL		 1003 u16 w;
1004
bc5d0c89
EV		 1005 if (!omap_mcbsp_check_valid_id(id)) {
1006 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 1007 return;
bc5d0c89 1008 }
5e1c5ff4 1009
b4b58f58 1010 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 1011
fb78d808 1012 /* Reset transmitter */
d09a2afc 1013 tx &= 1;
752ec2f2 1014 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
96fbd745 1015 w = MCBSP_READ_CACHE(mcbsp, XCCR);
d09a2afc 1016 w |= (tx ? XDISABLE : 0);
8ea3200f 1017 MCBSP_WRITE(mcbsp, XCCR, w);
d09a2afc 1018 }
96fbd745 1019 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 1020 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
5e1c5ff4
TL		 1021
1022 /* Reset receiver */
d09a2afc 1023 rx &= 1;
752ec2f2 1024 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
96fbd745 1025 w = MCBSP_READ_CACHE(mcbsp, RCCR);
a93d4ed2 1026 w |= (rx ? RDISABLE : 0);
8ea3200f 1027 MCBSP_WRITE(mcbsp, RCCR, w);
d09a2afc 1028 }
96fbd745 1029 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
8ea3200f 1030 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
5e1c5ff4 1031
96fbd745
JK		 1032 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
1033 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
c12abc01
JN		 1034
1035 if (idle) {
1036 /* Reset the sample rate generator */
96fbd745 1037 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
8ea3200f 1038 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
c12abc01 1039 }
d912fa92
EN		 1040
1041 if (cpu_is_omap34xx())
1042 omap_st_stop(mcbsp);
5e1c5ff4 1043}
fb78d808 1044EXPORT_SYMBOL(omap_mcbsp_stop);
5e1c5ff4 1045
bb13b5fd
TL		 1046/* polled mcbsp i/o operations */
1047int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
1048{
b4b58f58 1049 struct omap_mcbsp *mcbsp;
bc5d0c89
EV		 1050
1051 if (!omap_mcbsp_check_valid_id(id)) {
1052 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1053 return -ENODEV;
1054 }
1055
b4b58f58 1056 mcbsp = id_to_mcbsp_ptr(id);
b4b58f58 1057
8ea3200f 1058 MCBSP_WRITE(mcbsp, DXR1, buf);
bb13b5fd 1059 /* if frame sync error - clear the error */
8ea3200f 1060 if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
bb13b5fd 1061 /* clear error */
0841cb82 1062 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
bb13b5fd
TL		 1063 /* resend */
1064 return -1;
1065 } else {
1066 /* wait for transmit confirmation */
1067 int attemps = 0;
8ea3200f 1068 while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
bb13b5fd 1069 if (attemps++ > 1000) {
8ea3200f 1070 MCBSP_WRITE(mcbsp, SPCR2,
96fbd745
JK		 1071 MCBSP_READ_CACHE(mcbsp, SPCR2) &
1072 (~XRST));
bb13b5fd 1073 udelay(10);
8ea3200f 1074 MCBSP_WRITE(mcbsp, SPCR2,
96fbd745
JK		 1075 MCBSP_READ_CACHE(mcbsp, SPCR2) |
1076 (XRST));
bb13b5fd 1077 udelay(10);
b4b58f58
CS		 1078 dev_err(mcbsp->dev, "Could not write to"
1079 " McBSP%d Register\n", mcbsp->id);
bb13b5fd
TL		 1080 return -2;
1081 }
1082 }
1083 }
fb78d808 1084
bb13b5fd
TL		 1085 return 0;
1086}
fb78d808 1087EXPORT_SYMBOL(omap_mcbsp_pollwrite);
bb13b5fd 1088
fb78d808 1089int omap_mcbsp_pollread(unsigned int id, u16 *buf)
bb13b5fd 1090{
b4b58f58 1091 struct omap_mcbsp *mcbsp;
bc5d0c89
EV		 1092
1093 if (!omap_mcbsp_check_valid_id(id)) {
1094 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1095 return -ENODEV;
1096 }
b4b58f58 1097 mcbsp = id_to_mcbsp_ptr(id);
bc5d0c89 1098
bb13b5fd 1099 /* if frame sync error - clear the error */
8ea3200f 1100 if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
bb13b5fd 1101 /* clear error */
0841cb82 1102 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
bb13b5fd
TL		 1103 /* resend */
1104 return -1;
1105 } else {
25985edc 1106 /* wait for receive confirmation */
bb13b5fd 1107 int attemps = 0;
8ea3200f 1108 while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
bb13b5fd 1109 if (attemps++ > 1000) {
8ea3200f 1110 MCBSP_WRITE(mcbsp, SPCR1,
96fbd745
JK		 1111 MCBSP_READ_CACHE(mcbsp, SPCR1) &
1112 (~RRST));
bb13b5fd 1113 udelay(10);
8ea3200f 1114 MCBSP_WRITE(mcbsp, SPCR1,
96fbd745
JK		 1115 MCBSP_READ_CACHE(mcbsp, SPCR1) |
1116 (RRST));
bb13b5fd 1117 udelay(10);
b4b58f58
CS		 1118 dev_err(mcbsp->dev, "Could not read from"
1119 " McBSP%d Register\n", mcbsp->id);
bb13b5fd
TL		 1120 return -2;
1121 }
1122 }
1123 }
8ea3200f 1124 *buf = MCBSP_READ(mcbsp, DRR1);
fb78d808 1125
bb13b5fd
TL		 1126 return 0;
1127}
fb78d808 1128EXPORT_SYMBOL(omap_mcbsp_pollread);
bb13b5fd 1129
5e1c5ff4
TL		 1130/*
1131 * IRQ based word transmission.
1132 */
1133void omap_mcbsp_xmit_word(unsigned int id, u32 word)
1134{
b4b58f58 1135 struct omap_mcbsp *mcbsp;
bc5d0c89 1136 omap_mcbsp_word_length word_length;
5e1c5ff4 1137
bc5d0c89
EV		 1138 if (!omap_mcbsp_check_valid_id(id)) {
1139 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
5e1c5ff4 1140 return;
bc5d0c89 1141 }
5e1c5ff4 1142
b4b58f58 1143 mcbsp = id_to_mcbsp_ptr(id);
b4b58f58 1144 word_length = mcbsp->tx_word_length;
5e1c5ff4 1145
b4b58f58 1146 wait_for_completion(&mcbsp->tx_irq_completion);
5e1c5ff4
TL		 1147
1148 if (word_length > OMAP_MCBSP_WORD_16)
8ea3200f
JK		 1149 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1150 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
5e1c5ff4 1151}
fb78d808 1152EXPORT_SYMBOL(omap_mcbsp_xmit_word);
5e1c5ff4
TL		 1153
1154u32 omap_mcbsp_recv_word(unsigned int id)
1155{
b4b58f58 1156 struct omap_mcbsp *mcbsp;
5e1c5ff4 1157 u16 word_lsb, word_msb = 0;
bc5d0c89 1158 omap_mcbsp_word_length word_length;
5e1c5ff4 1159
bc5d0c89
EV		 1160 if (!omap_mcbsp_check_valid_id(id)) {
1161 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1162 return -ENODEV;
1163 }
b4b58f58 1164 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 1165
b4b58f58 1166 word_length = mcbsp->rx_word_length;
5e1c5ff4 1167
b4b58f58 1168 wait_for_completion(&mcbsp->rx_irq_completion);
5e1c5ff4
TL		 1169
1170 if (word_length > OMAP_MCBSP_WORD_16)
8ea3200f
JK		 1171 word_msb = MCBSP_READ(mcbsp, DRR2);
1172 word_lsb = MCBSP_READ(mcbsp, DRR1);
5e1c5ff4
TL		 1173
1174 return (word_lsb | (word_msb << 16));
1175}
fb78d808 1176EXPORT_SYMBOL(omap_mcbsp_recv_word);
5e1c5ff4
TL		 1177
1178/*
1179 * Simple DMA based buffer rx/tx routines.
1180 * Nothing fancy, just a single buffer tx/rx through DMA.
1181 * The DMA resources are released once the transfer is done.
1182 * For anything fancier, you should use your own customized DMA
1183 * routines and callbacks.
1184 */
fb78d808
EV		 1185int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
1186 unsigned int length)
5e1c5ff4 1187{
b4b58f58 1188 struct omap_mcbsp *mcbsp;
5e1c5ff4 1189 int dma_tx_ch;
120db2cb
TL		 1190 int src_port = 0;
1191 int dest_port = 0;
1192 int sync_dev = 0;
5e1c5ff4 1193
bc5d0c89
EV		 1194 if (!omap_mcbsp_check_valid_id(id)) {
1195 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1196 return -ENODEV;
1197 }
b4b58f58 1198 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 1199
b4b58f58 1200 if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
fb78d808 1201 omap_mcbsp_tx_dma_callback,
b4b58f58 1202 mcbsp,
fb78d808 1203 &dma_tx_ch)) {
b4b58f58 1204 dev_err(mcbsp->dev, " Unable to request DMA channel for "
bc5d0c89 1205 "McBSP%d TX. Trying IRQ based TX\n",
b4b58f58 1206 mcbsp->id);
5e1c5ff4
TL		 1207 return -EAGAIN;
1208 }
b4b58f58 1209 mcbsp->dma_tx_lch = dma_tx_ch;
5e1c5ff4 1210
b4b58f58 1211 dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
bc5d0c89 1212 dma_tx_ch);
5e1c5ff4 1213
b4b58f58 1214 init_completion(&mcbsp->tx_dma_completion);
5e1c5ff4 1215
120db2cb
TL		 1216 if (cpu_class_is_omap1()) {
1217 src_port = OMAP_DMA_PORT_TIPB;
1218 dest_port = OMAP_DMA_PORT_EMIFF;
1219 }
bc5d0c89 1220 if (cpu_class_is_omap2())
b4b58f58 1221 sync_dev = mcbsp->dma_tx_sync;
120db2cb 1222
b4b58f58 1223 omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
5e1c5ff4
TL		 1224 OMAP_DMA_DATA_TYPE_S16,
1225 length >> 1, 1,
1a8bfa1e 1226 OMAP_DMA_SYNC_ELEMENT,
120db2cb 1227 sync_dev, 0);
5e1c5ff4 1228
b4b58f58 1229 omap_set_dma_dest_params(mcbsp->dma_tx_lch,
120db2cb 1230 src_port,
5e1c5ff4 1231 OMAP_DMA_AMODE_CONSTANT,
b4b58f58 1232 mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
1a8bfa1e 1233 0, 0);
5e1c5ff4 1234
b4b58f58 1235 omap_set_dma_src_params(mcbsp->dma_tx_lch,
120db2cb 1236 dest_port,
5e1c5ff4 1237 OMAP_DMA_AMODE_POST_INC,
1a8bfa1e
TL		 1238 buffer,
1239 0, 0);
5e1c5ff4 1240
b4b58f58
CS		 1241 omap_start_dma(mcbsp->dma_tx_lch);
1242 wait_for_completion(&mcbsp->tx_dma_completion);
fb78d808 1243
5e1c5ff4
TL		 1244 return 0;
1245}
fb78d808 1246EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
5e1c5ff4 1247
fb78d808
EV		 1248int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
1249 unsigned int length)
5e1c5ff4 1250{
b4b58f58 1251 struct omap_mcbsp *mcbsp;
5e1c5ff4 1252 int dma_rx_ch;
120db2cb
TL		 1253 int src_port = 0;
1254 int dest_port = 0;
1255 int sync_dev = 0;
5e1c5ff4 1256
bc5d0c89
EV		 1257 if (!omap_mcbsp_check_valid_id(id)) {
1258 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1259 return -ENODEV;
1260 }
b4b58f58 1261 mcbsp = id_to_mcbsp_ptr(id);
5e1c5ff4 1262
b4b58f58 1263 if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
fb78d808 1264 omap_mcbsp_rx_dma_callback,
b4b58f58 1265 mcbsp,
fb78d808 1266 &dma_rx_ch)) {
b4b58f58 1267 dev_err(mcbsp->dev, "Unable to request DMA channel for "
bc5d0c89 1268 "McBSP%d RX. Trying IRQ based RX\n",
b4b58f58 1269 mcbsp->id);
5e1c5ff4
TL		 1270 return -EAGAIN;
1271 }
b4b58f58 1272 mcbsp->dma_rx_lch = dma_rx_ch;
5e1c5ff4 1273
b4b58f58 1274 dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
bc5d0c89 1275 dma_rx_ch);
5e1c5ff4 1276
b4b58f58 1277 init_completion(&mcbsp->rx_dma_completion);
5e1c5ff4 1278
120db2cb
TL		 1279 if (cpu_class_is_omap1()) {
1280 src_port = OMAP_DMA_PORT_TIPB;
1281 dest_port = OMAP_DMA_PORT_EMIFF;
1282 }
bc5d0c89 1283 if (cpu_class_is_omap2())
b4b58f58 1284 sync_dev = mcbsp->dma_rx_sync;
120db2cb 1285
b4b58f58 1286 omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
fb78d808
EV		 1287 OMAP_DMA_DATA_TYPE_S16,
1288 length >> 1, 1,
1289 OMAP_DMA_SYNC_ELEMENT,
1290 sync_dev, 0);
5e1c5ff4 1291
b4b58f58 1292 omap_set_dma_src_params(mcbsp->dma_rx_lch,
120db2cb 1293 src_port,
5e1c5ff4 1294 OMAP_DMA_AMODE_CONSTANT,
b4b58f58 1295 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1a8bfa1e 1296 0, 0);
5e1c5ff4 1297
b4b58f58 1298 omap_set_dma_dest_params(mcbsp->dma_rx_lch,
fb78d808
EV		 1299 dest_port,
1300 OMAP_DMA_AMODE_POST_INC,
1301 buffer,
1302 0, 0);
5e1c5ff4 1303
b4b58f58
CS		 1304 omap_start_dma(mcbsp->dma_rx_lch);
1305 wait_for_completion(&mcbsp->rx_dma_completion);
fb78d808 1306
5e1c5ff4
TL		 1307 return 0;
1308}
fb78d808 1309EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
5e1c5ff4 1310
a8eb7ca0 1311#ifdef CONFIG_ARCH_OMAP3
a1a56f5f
EV		 1312#define max_thres(m) (mcbsp->pdata->buffer_size)
1313#define valid_threshold(m, val) ((val) <= max_thres(m))
1314#define THRESHOLD_PROP_BUILDER(prop) \
1315static ssize_t prop##_show(struct device *dev, \
1316 struct device_attribute *attr, char *buf) \
1317{ \
1318 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1319 \
1320 return sprintf(buf, "%u\n", mcbsp->prop); \
1321} \
1322 \
1323static ssize_t prop##_store(struct device *dev, \
1324 struct device_attribute *attr, \
1325 const char *buf, size_t size) \
1326{ \
1327 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1328 unsigned long val; \
1329 int status; \
1330 \
1331 status = strict_strtoul(buf, 0, &val); \
1332 if (status) \
1333 return status; \
1334 \
1335 if (!valid_threshold(mcbsp, val)) \
1336 return -EDOM; \
1337 \
1338 mcbsp->prop = val; \
1339 return size; \
1340} \
1341 \
1342static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1343
1344THRESHOLD_PROP_BUILDER(max_tx_thres);
1345THRESHOLD_PROP_BUILDER(max_rx_thres);
1346
9b300509
JN		 1347static const char *dma_op_modes[] = {
1348 "element", "threshold", "frame",
1349};
1350
98cb20e8
PU		 1351static ssize_t dma_op_mode_show(struct device *dev,
1352 struct device_attribute *attr, char *buf)
1353{
1354 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
9b300509
JN		 1355 int dma_op_mode, i = 0;
1356 ssize_t len = 0;
1357 const char * const *s;
98cb20e8 1358
98cb20e8 1359 dma_op_mode = mcbsp->dma_op_mode;
98cb20e8 1360
9b300509
JN		 1361 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1362 if (dma_op_mode == i)
1363 len += sprintf(buf + len, "[%s] ", *s);
1364 else
1365 len += sprintf(buf + len, "%s ", *s);
1366 }
1367 len += sprintf(buf + len, "\n");
1368
1369 return len;
98cb20e8
PU		 1370}
1371
1372static ssize_t dma_op_mode_store(struct device *dev,
1373 struct device_attribute *attr,
1374 const char *buf, size_t size)
1375{
1376 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
9b300509
JN		 1377 const char * const *s;
1378 int i = 0;
98cb20e8 1379
9b300509
JN		 1380 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1381 if (sysfs_streq(buf, *s))
1382 break;
98cb20e8 1383
9b300509
JN		 1384 if (i == ARRAY_SIZE(dma_op_modes))
1385 return -EINVAL;
98cb20e8 1386
9b300509 1387 spin_lock_irq(&mcbsp->lock);
98cb20e8
PU		 1388 if (!mcbsp->free) {
1389 size = -EBUSY;
1390 goto unlock;
1391 }
9b300509 1392 mcbsp->dma_op_mode = i;
98cb20e8
PU		 1393
1394unlock:
1395 spin_unlock_irq(&mcbsp->lock);
1396
1397 return size;
1398}
1399
1400static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1401
d912fa92
EN		 1402static ssize_t st_taps_show(struct device *dev,
1403 struct device_attribute *attr, char *buf)
1404{
1405 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1406 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1407 ssize_t status = 0;
1408 int i;
1409
1410 spin_lock_irq(&mcbsp->lock);
1411 for (i = 0; i < st_data->nr_taps; i++)
1412 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1413 st_data->taps[i]);
1414 if (i)
1415 status += sprintf(&buf[status], "\n");
1416 spin_unlock_irq(&mcbsp->lock);
1417
1418 return status;
1419}
1420
1421static ssize_t st_taps_store(struct device *dev,
1422 struct device_attribute *attr,
1423 const char *buf, size_t size)
1424{
1425 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1426 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1427 int val, tmp, status, i = 0;
1428
1429 spin_lock_irq(&mcbsp->lock);
1430 memset(st_data->taps, 0, sizeof(st_data->taps));
1431 st_data->nr_taps = 0;
1432
1433 do {
1434 status = sscanf(buf, "%d%n", &val, &tmp);
1435 if (status < 0 || status == 0) {
1436 size = -EINVAL;
1437 goto out;
1438 }
1439 if (val < -32768 || val > 32767) {
1440 size = -EINVAL;
1441 goto out;
1442 }
1443 st_data->taps[i++] = val;
1444 buf += tmp;
1445 if (*buf != ',')
1446 break;
1447 buf++;
1448 } while (1);
1449
1450 st_data->nr_taps = i;
1451
1452out:
1453 spin_unlock_irq(&mcbsp->lock);
1454
1455 return size;
1456}
1457
1458static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1459
4c8200ae 1460static const struct attribute *additional_attrs[] = {
a1a56f5f
EV		 1461 &dev_attr_max_tx_thres.attr,
1462 &dev_attr_max_rx_thres.attr,
98cb20e8 1463 &dev_attr_dma_op_mode.attr,
a1a56f5f
EV		 1464 NULL,
1465};
1466
4c8200ae
EV		 1467static const struct attribute_group additional_attr_group = {
1468 .attrs = (struct attribute **)additional_attrs,
a1a56f5f
EV		 1469};
1470
4c8200ae 1471static inline int __devinit omap_additional_add(struct device *dev)
a1a56f5f 1472{
4c8200ae 1473 return sysfs_create_group(&dev->kobj, &additional_attr_group);
a1a56f5f
EV		 1474}
1475
4c8200ae 1476static inline void __devexit omap_additional_remove(struct device *dev)
a1a56f5f 1477{
4c8200ae 1478 sysfs_remove_group(&dev->kobj, &additional_attr_group);
a1a56f5f
EV		 1479}
1480
d912fa92
EN		 1481static const struct attribute *sidetone_attrs[] = {
1482 &dev_attr_st_taps.attr,
1483 NULL,
1484};
1485
1486static const struct attribute_group sidetone_attr_group = {
1487 .attrs = (struct attribute **)sidetone_attrs,
1488};
1489
b0a330dc 1490static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
d912fa92 1491{
3cf32bba
KVA		 1492 struct platform_device *pdev;
1493 struct resource *res;
d912fa92
EN		 1494 struct omap_mcbsp_st_data *st_data;
1495 int err;
1496
1497 st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1498 if (!st_data) {
1499 err = -ENOMEM;
1500 goto err1;
1501 }
1502
3cf32bba
KVA		 1503 pdev = container_of(mcbsp->dev, struct platform_device, dev);
1504
1505 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1506 st_data->io_base_st = ioremap(res->start, resource_size(res));
d912fa92
EN		 1507 if (!st_data->io_base_st) {
1508 err = -ENOMEM;
1509 goto err2;
1510 }
1511
1512 err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1513 if (err)
1514 goto err3;
1515
1516 mcbsp->st_data = st_data;
1517 return 0;
1518
1519err3:
1520 iounmap(st_data->io_base_st);
1521err2:
1522 kfree(st_data);
1523err1:
1524 return err;
1525
1526}
1527
1528static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1529{
1530 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1531
1532 if (st_data) {
1533 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1534 iounmap(st_data->io_base_st);
1535 kfree(st_data);
1536 }
1537}
1538
a1a56f5f
EV		 1539static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1540{
98cb20e8 1541 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
a1a56f5f 1542 if (cpu_is_omap34xx()) {
451fd82d
PU		 1543 /*
1544 * Initially configure the maximum thresholds to a safe value.
1545 * The McBSP FIFO usage with these values should not go under
1546 * 16 locations.
1547 * If the whole FIFO without safety buffer is used, than there
1548 * is a possibility that the DMA will be not able to push the
1549 * new data on time, causing channel shifts in runtime.
1550 */
1551 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1552 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
98cb20e8
PU		 1553 /*
1554 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1555 * for mcbsp2 instances.
1556 */
4c8200ae 1557 if (omap_additional_add(mcbsp->dev))
a1a56f5f 1558 dev_warn(mcbsp->dev,
4c8200ae 1559 "Unable to create additional controls\n");
d912fa92
EN		 1560
1561 if (mcbsp->id == 2 || mcbsp->id == 3)
1562 if (omap_st_add(mcbsp))
1563 dev_warn(mcbsp->dev,
1564 "Unable to create sidetone controls\n");
1565
a1a56f5f
EV		 1566 } else {
1567 mcbsp->max_tx_thres = -EINVAL;
1568 mcbsp->max_rx_thres = -EINVAL;
1569 }
1570}
1571
1572static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1573{
d912fa92 1574 if (cpu_is_omap34xx()) {
4c8200ae 1575 omap_additional_remove(mcbsp->dev);
d912fa92
EN		 1576
1577 if (mcbsp->id == 2 || mcbsp->id == 3)
1578 omap_st_remove(mcbsp);
1579 }
a1a56f5f
EV		 1580}
1581#else
1582static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1583static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
a8eb7ca0 1584#endif /* CONFIG_ARCH_OMAP3 */
a1a56f5f 1585
5e1c5ff4
TL		 1586/*
1587 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1588 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1589 */
25cef225 1590static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
bc5d0c89
EV		 1591{
1592 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
b4b58f58 1593 struct omap_mcbsp *mcbsp;
bc5d0c89 1594 int id = pdev->id - 1;
3cf32bba 1595 struct resource *res;
bc5d0c89 1596 int ret = 0;
5e1c5ff4 1597
bc5d0c89
EV		 1598 if (!pdata) {
1599 dev_err(&pdev->dev, "McBSP device initialized without"
1600 "platform data\n");
1601 ret = -EINVAL;
1602 goto exit;
1603 }
1604
1605 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1606
b4b58f58 1607 if (id >= omap_mcbsp_count) {
bc5d0c89
EV		 1608 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1609 ret = -EINVAL;
1610 goto exit;
1611 }
1612
b4b58f58
CS		 1613 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1614 if (!mcbsp) {
1615 ret = -ENOMEM;
1616 goto exit;
1617 }
b4b58f58
CS		 1618
1619 spin_lock_init(&mcbsp->lock);
1620 mcbsp->id = id + 1;
6722a723 1621 mcbsp->free = true;
b4b58f58
CS		 1622 mcbsp->dma_tx_lch = -1;
1623 mcbsp->dma_rx_lch = -1;
bc5d0c89 1624
3cf32bba
KVA		 1625 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1626 if (!res) {
1627 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1628 if (!res) {
1629 dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory"
1630 "resource\n", __func__, pdev->id);
1631 ret = -ENOMEM;
1632 goto exit;
1633 }
1634 }
1635 mcbsp->phys_base = res->start;
1636 omap_mcbsp_cache_size = resource_size(res);
1637 mcbsp->io_base = ioremap(res->start, resource_size(res));
b4b58f58 1638 if (!mcbsp->io_base) {
d592dd1a
RK		 1639 ret = -ENOMEM;
1640 goto err_ioremap;
1641 }
1642
3cf32bba
KVA		 1643 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
1644 if (!res)
1645 mcbsp->phys_dma_base = mcbsp->phys_base;
1646 else
1647 mcbsp->phys_dma_base = res->start;
1648
bc5d0c89 1649 /* Default I/O is IRQ based */
b4b58f58 1650 mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
3cf32bba
KVA		 1651
1652 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1653 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1654
cb7e9ded
KVA		 1655 /* From OMAP4 there will be a single irq line */
1656 if (mcbsp->tx_irq == -ENXIO)
1657 mcbsp->tx_irq = platform_get_irq(pdev, 0);
1658
3cf32bba
KVA		 1659 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1660 if (!res) {
1661 dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
1662 __func__, pdev->id);
1663 ret = -ENODEV;
1664 goto err_res;
1665 }
1666 mcbsp->dma_rx_sync = res->start;
1667
1668 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1669 if (!res) {
1670 dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n",
1671 __func__, pdev->id);
1672 ret = -ENODEV;
1673 goto err_res;
1674 }
1675 mcbsp->dma_tx_sync = res->start;
bc5d0c89 1676
b820ce4e
RK		 1677 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1678 if (IS_ERR(mcbsp->fclk)) {
1679 ret = PTR_ERR(mcbsp->fclk);
1680 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
e95496d4 1681 goto err_res;
bc5d0c89
EV		 1682 }
1683
b4b58f58
CS		 1684 mcbsp->pdata = pdata;
1685 mcbsp->dev = &pdev->dev;
b820ce4e 1686 mcbsp_ptr[id] = mcbsp;
9504ba64 1687 mcbsp->mcbsp_config_type = pdata->mcbsp_config_type;
b4b58f58 1688 platform_set_drvdata(pdev, mcbsp);
e95496d4 1689 pm_runtime_enable(mcbsp->dev);
a1a56f5f
EV		 1690
1691 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1692 omap34xx_device_init(mcbsp);
1693
d592dd1a 1694 return 0;
bc5d0c89 1695
3cf32bba 1696err_res:
b4b58f58 1697 iounmap(mcbsp->io_base);
d592dd1a 1698err_ioremap:
b820ce4e 1699 kfree(mcbsp);
bc5d0c89
EV		 1700exit:
1701 return ret;
1702}
120db2cb 1703
25cef225 1704static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
5e1c5ff4 1705{
bc5d0c89 1706 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
5e1c5ff4 1707
bc5d0c89
EV		 1708 platform_set_drvdata(pdev, NULL);
1709 if (mcbsp) {
5e1c5ff4 1710
bc5d0c89
EV		 1711 if (mcbsp->pdata && mcbsp->pdata->ops &&
1712 mcbsp->pdata->ops->free)
1713 mcbsp->pdata->ops->free(mcbsp->id);
5e1c5ff4 1714
a1a56f5f
EV		 1715 omap34xx_device_exit(mcbsp);
1716
b820ce4e 1717 clk_put(mcbsp->fclk);
bc5d0c89 1718
d592dd1a 1719 iounmap(mcbsp->io_base);
5f3b7284 1720 kfree(mcbsp);
5e1c5ff4
TL		 1721 }
1722
1723 return 0;
1724}
1725
bc5d0c89
EV		 1726static struct platform_driver omap_mcbsp_driver = {
1727 .probe = omap_mcbsp_probe,
25cef225 1728 .remove = __devexit_p(omap_mcbsp_remove),
bc5d0c89
EV		 1729 .driver = {
1730 .name = "omap-mcbsp",
1731 },
1732};
1733
1734int __init omap_mcbsp_init(void)
1735{
1736 /* Register the McBSP driver */
1737 return platform_driver_register(&omap_mcbsp_driver);
1738}
Linux kernel - Deliverables
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