[deliverable/linux.git] / arch / arm / plat-omap / sram.c

/*
 * linux/arch/arm/plat-omap/sram.c
 *
 * OMAP SRAM detection and management
 *
 * Copyright (C) 2005 Nokia Corporation
 * Written by Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2009-2012 Texas Instruments
 * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#undef DEBUG

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>

#include <asm/tlb.h>
#include <asm/cacheflush.h>

#include <asm/mach/map.h>

#include <plat/sram.h>
#include <plat/board.h>
#include <plat/cpu.h>

#include "sram.h"

/* XXX These "sideways" includes will disappear when sram.c becomes a driver */
#include "../mach-omap2/iomap.h"
#include "../mach-omap2/prm2xxx_3xxx.h"
#include "../mach-omap2/sdrc.h"

#define OMAP1_SRAM_PA		0x20000000
#define OMAP2_SRAM_PUB_PA	(OMAP2_SRAM_PA + 0xf800)
#define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
#ifdef CONFIG_OMAP4_ERRATA_I688
#define OMAP4_SRAM_PUB_PA	OMAP4_SRAM_PA
#else
#define OMAP4_SRAM_PUB_PA	(OMAP4_SRAM_PA + 0x4000)
#endif
#define OMAP5_SRAM_PA		0x40300000

#if defined(CONFIG_ARCH_OMAP2PLUS)
#define SRAM_BOOTLOADER_SZ	0x00
#else
#define SRAM_BOOTLOADER_SZ	0x80
#endif

#define OMAP24XX_VA_REQINFOPERM0	OMAP2_L3_IO_ADDRESS(0x68005048)
#define OMAP24XX_VA_READPERM0		OMAP2_L3_IO_ADDRESS(0x68005050)
#define OMAP24XX_VA_WRITEPERM0		OMAP2_L3_IO_ADDRESS(0x68005058)

#define OMAP34XX_VA_REQINFOPERM0	OMAP2_L3_IO_ADDRESS(0x68012848)
#define OMAP34XX_VA_READPERM0		OMAP2_L3_IO_ADDRESS(0x68012850)
#define OMAP34XX_VA_WRITEPERM0		OMAP2_L3_IO_ADDRESS(0x68012858)
#define OMAP34XX_VA_ADDR_MATCH2		OMAP2_L3_IO_ADDRESS(0x68012880)
#define OMAP34XX_VA_SMS_RG_ATT0		OMAP2_L3_IO_ADDRESS(0x6C000048)

#define GP_DEVICE		0x300

#define ROUND_DOWN(value,boundary)	((value) & (~((boundary)-1)))

static unsigned long omap_sram_start;
static void __iomem *omap_sram_base;
static unsigned long omap_sram_skip;
static unsigned long omap_sram_size;
static void __iomem *omap_sram_ceil;

/*
 * Depending on the target RAMFS firewall setup, the public usable amount of
 * SRAM varies.  The default accessible size for all device types is 2k. A GP
 * device allows ARM11 but not other initiators for full size. This
 * functionality seems ok until some nice security API happens.
 */
static int is_sram_locked(void)
{
	if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
		/* RAMFW: R/W access to all initiators for all qualifier sets */
		if (cpu_is_omap242x()) {
			__raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
			__raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
			__raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
		}
		if (cpu_is_omap34xx()) {
			__raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
			__raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
			__raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
			__raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
			__raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
		}
		return 0;
	} else
		return 1; /* assume locked with no PPA or security driver */
}

/*
 * The amount of SRAM depends on the core type.
 * Note that we cannot try to test for SRAM here because writes
 * to secure SRAM will hang the system. Also the SRAM is not
 * yet mapped at this point.
 */
static void __init omap_detect_sram(void)
{
	omap_sram_skip = SRAM_BOOTLOADER_SZ;
	if (cpu_class_is_omap2()) {
		if (is_sram_locked()) {
			if (cpu_is_omap34xx()) {
				omap_sram_start = OMAP3_SRAM_PUB_PA;
				if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
				    (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
					omap_sram_size = 0x7000; /* 28K */
					omap_sram_skip += SZ_16K;
				} else {
					omap_sram_size = 0x8000; /* 32K */
				}
			} else if (cpu_is_omap44xx()) {
				omap_sram_start = OMAP4_SRAM_PUB_PA;
				omap_sram_size = 0xa000; /* 40K */
			} else if (soc_is_omap54xx()) {
				omap_sram_start = OMAP5_SRAM_PA;
				omap_sram_size = SZ_128K; /* 128KB */
			} else {
				omap_sram_start = OMAP2_SRAM_PUB_PA;
				omap_sram_size = 0x800; /* 2K */
			}
		} else {
			if (soc_is_am33xx()) {
				omap_sram_start = AM33XX_SRAM_PA;
				omap_sram_size = 0x10000; /* 64K */
			} else if (cpu_is_omap34xx()) {
				omap_sram_start = OMAP3_SRAM_PA;
				omap_sram_size = 0x10000; /* 64K */
			} else if (cpu_is_omap44xx()) {
				omap_sram_start = OMAP4_SRAM_PA;
				omap_sram_size = 0xe000; /* 56K */
			} else if (soc_is_omap54xx()) {
				omap_sram_start = OMAP5_SRAM_PA;
				omap_sram_size = SZ_128K; /* 128KB */
			} else {
				omap_sram_start = OMAP2_SRAM_PA;
				if (cpu_is_omap242x())
					omap_sram_size = 0xa0000; /* 640K */
				else if (cpu_is_omap243x())
					omap_sram_size = 0x10000; /* 64K */
			}
		}
	} else {
		omap_sram_start = OMAP1_SRAM_PA;

		if (cpu_is_omap7xx())
			omap_sram_size = 0x32000;	/* 200K */
		else if (cpu_is_omap15xx())
			omap_sram_size = 0x30000;	/* 192K */
		else if (cpu_is_omap1610() || cpu_is_omap1611() ||
				cpu_is_omap1621() || cpu_is_omap1710())
			omap_sram_size = 0x4000;	/* 16K */
		else {
			pr_err("Could not detect SRAM size\n");
			omap_sram_size = 0x4000;
		}
	}
}

/*
 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
 */
static void __init omap_map_sram(void)
{
	int cached = 1;

	if (omap_sram_size == 0)
		return;

#ifdef CONFIG_OMAP4_ERRATA_I688
	if (cpu_is_omap44xx()) {
		omap_sram_start += PAGE_SIZE;
		omap_sram_size -= SZ_16K;
	}
#endif
	if (cpu_is_omap34xx()) {
		/*
		 * SRAM must be marked as non-cached on OMAP3 since the
		 * CORE DPLL M2 divider change code (in SRAM) runs with the
		 * SDRAM controller disabled, and if it is marked cached,
		 * the ARM may attempt to write cache lines back to SDRAM
		 * which will cause the system to hang.
		 */
		cached = 0;
	}

	omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
	omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size,
						cached);
	if (!omap_sram_base) {
		pr_err("SRAM: Could not map\n");
		return;
	}

	omap_sram_ceil = omap_sram_base + omap_sram_size;

	/*
	 * Looks like we need to preserve some bootloader code at the
	 * beginning of SRAM for jumping to flash for reboot to work...
	 */
	memset_io(omap_sram_base + omap_sram_skip, 0,
		  omap_sram_size - omap_sram_skip);
}

/*
 * Memory allocator for SRAM: calculates the new ceiling address
 * for pushing a function using the fncpy API.
 *
 * Note that fncpy requires the returned address to be aligned
 * to an 8-byte boundary.
 */
void *omap_sram_push_address(unsigned long size)
{
	unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;

	available = omap_sram_ceil - (omap_sram_base + omap_sram_skip);

	if (size > available) {
		pr_err("Not enough space in SRAM\n");
		return NULL;
	}

	new_ceil -= size;
	new_ceil = ROUND_DOWN(new_ceil, FNCPY_ALIGN);
	omap_sram_ceil = IOMEM(new_ceil);

	return (void *)omap_sram_ceil;
}

#ifdef CONFIG_ARCH_OMAP1

static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);

void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
{
	BUG_ON(!_omap_sram_reprogram_clock);
	/* On 730, bit 13 must always be 1 */
	if (cpu_is_omap7xx())
		ckctl |= 0x2000;
	_omap_sram_reprogram_clock(dpllctl, ckctl);
}

static int __init omap1_sram_init(void)
{
	_omap_sram_reprogram_clock =
			omap_sram_push(omap1_sram_reprogram_clock,
					omap1_sram_reprogram_clock_sz);

	return 0;
}

#else
#define omap1_sram_init()	do {} while (0)
#endif

#if defined(CONFIG_ARCH_OMAP2)

static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
			      u32 base_cs, u32 force_unlock);

void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
		   u32 base_cs, u32 force_unlock)
{
	BUG_ON(!_omap2_sram_ddr_init);
	_omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
			     base_cs, force_unlock);
}

static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
					  u32 mem_type);

void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
{
	BUG_ON(!_omap2_sram_reprogram_sdrc);
	_omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
}

static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);

u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
{
	BUG_ON(!_omap2_set_prcm);
	return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
}
#endif

#ifdef CONFIG_SOC_OMAP2420
static int __init omap242x_sram_init(void)
{
	_omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
					omap242x_sram_ddr_init_sz);

	_omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
					    omap242x_sram_reprogram_sdrc_sz);

	_omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
					 omap242x_sram_set_prcm_sz);

	return 0;
}
#else
static inline int omap242x_sram_init(void)
{
	return 0;
}
#endif

#ifdef CONFIG_SOC_OMAP2430
static int __init omap243x_sram_init(void)
{
	_omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
					omap243x_sram_ddr_init_sz);

	_omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
					    omap243x_sram_reprogram_sdrc_sz);

	_omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
					 omap243x_sram_set_prcm_sz);

	return 0;
}
#else
static inline int omap243x_sram_init(void)
{
	return 0;
}
#endif

#ifdef CONFIG_ARCH_OMAP3

static u32 (*_omap3_sram_configure_core_dpll)(
			u32 m2, u32 unlock_dll, u32 f, u32 inc,
			u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);

u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
			u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
			u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
			u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
			u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
{
	BUG_ON(!_omap3_sram_configure_core_dpll);
	return _omap3_sram_configure_core_dpll(
			m2, unlock_dll, f, inc,
			sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
			sdrc_actim_ctrl_b_0, sdrc_mr_0,
			sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
			sdrc_actim_ctrl_b_1, sdrc_mr_1);
}

void omap3_sram_restore_context(void)
{
	omap_sram_ceil = omap_sram_base + omap_sram_size;

	_omap3_sram_configure_core_dpll =
		omap_sram_push(omap3_sram_configure_core_dpll,
			       omap3_sram_configure_core_dpll_sz);
	omap_push_sram_idle();
}

static inline int omap34xx_sram_init(void)
{
	omap3_sram_restore_context();
	return 0;
}
#else
static inline int omap34xx_sram_init(void)
{
	return 0;
}
#endif /* CONFIG_ARCH_OMAP3 */

static inline int am33xx_sram_init(void)
{
	return 0;
}

int __init omap_sram_init(void)
{
	omap_detect_sram();
	omap_map_sram();

	if (!(cpu_class_is_omap2()))
		omap1_sram_init();
	else if (cpu_is_omap242x())
		omap242x_sram_init();
	else if (cpu_is_omap2430())
		omap243x_sram_init();
	else if (soc_is_am33xx())
		am33xx_sram_init();
	else if (cpu_is_omap34xx())
		omap34xx_sram_init();

	return 0;
}
Commit	Line	Data
92105bb7 TL	1	/*
	2	* linux/arch/arm/plat-omap/sram.c
	3	*
	4	* OMAP SRAM detection and management
	5	*
	6	* Copyright (C) 2005 Nokia Corporation
	7	* Written by Tony Lindgren <tony@atomide.com>
	8	*
05e152c7 S	9	* Copyright (C) 2009-2012 Texas Instruments
05e152c7 S	10	* Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
44169075	11	*
92105bb7 TL	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*/
c2d43e39	16	#undef DEBUG
92105bb7	17
92105bb7 TL	18	#include <linux/module.h>
	19	#include <linux/kernel.h>
	20	#include <linux/init.h>
fced80c7	21	#include <linux/io.h>
92105bb7	22
53d9cc73	23	#include <asm/tlb.h>
92105bb7 TL	24	#include <asm/cacheflush.h>
92105bb7 TL	25
670c104a TL	26	#include <asm/mach/map.h>
670c104a TL	27
ce491cf8 TL	28	#include <plat/sram.h>
	29	#include <plat/board.h>
	30	#include <plat/cpu.h>
1a8bfa1e	31
b0a330dc	32	#include "sram.h"
59fb659b	33
ee0839c2 TL	34	/* XXX These "sideways" includes will disappear when sram.c becomes a driver */
	35	#include "../mach-omap2/iomap.h"
	36	#include "../mach-omap2/prm2xxx_3xxx.h"
	37	#include "../mach-omap2/sdrc.h"
c2d43e39	38
1a8bfa1e	39	#define OMAP1_SRAM_PA 0x20000000
b4b36fd9	40	#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
b4b36fd9	41	#define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
137d105d SS	42	#ifdef CONFIG_OMAP4_ERRATA_I688
	43	#define OMAP4_SRAM_PUB_PA OMAP4_SRAM_PA
	44	#else
a7c3ae2c	45	#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
137d105d	46	#endif
05e152c7	47	#define OMAP5_SRAM_PA 0x40300000
c2d43e39	48
f47d8c69	49	#if defined(CONFIG_ARCH_OMAP2PLUS)
670c104a TL	50	#define SRAM_BOOTLOADER_SZ 0x00
670c104a TL	51	#else
92105bb7	52	#define SRAM_BOOTLOADER_SZ 0x80
670c104a TL	53	#endif
670c104a TL	54
233fd64e SS	55	#define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048)
	56	#define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050)
	57	#define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058)
c2d43e39	58
233fd64e SS	59	#define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848)
	60	#define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850)
	61	#define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
	62	#define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880)
	63	#define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048)
c2d43e39	64
670c104a	65	#define GP_DEVICE 0x300
670c104a TL	66
670c104a TL	67	#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
92105bb7	68
c40fae95	69	static unsigned long omap_sram_start;
a66cb345	70	static void __iomem *omap_sram_base;
b2856734	71	static unsigned long omap_sram_skip;
92105bb7	72	static unsigned long omap_sram_size;
a66cb345	73	static void __iomem *omap_sram_ceil;
92105bb7	74
b7cc6d46 ID	75	/*
b7cc6d46 ID	76	* Depending on the target RAMFS firewall setup, the public usable amount of
6cbdc8c5 SA	77	* SRAM varies. The default accessible size for all device types is 2k. A GP
6cbdc8c5 SA	78	* device allows ARM11 but not other initiators for full size. This
670c104a TL	79	* functionality seems ok until some nice security API happens.
	80	*/
	81	static int is_sram_locked(void)
	82	{
2a27753f	83	if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
6cbdc8c5	84	/* RAMFW: R/W access to all initiators for all qualifier sets */
670c104a	85	if (cpu_is_omap242x()) {
c2d43e39 TL	86	__raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
	87	__raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
	88	__raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
	89	}
1c213ba1	90	if (cpu_is_omap34xx()) {
c2d43e39 TL	91	__raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
	92	__raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
	93	__raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
	94	__raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
	95	__raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
670c104a TL	96	}
	97	return 0;
	98	} else
	99	return 1; /* assume locked with no PPA or security driver */
	100	}
	101
92105bb7	102	/*
1a8bfa1e	103	* The amount of SRAM depends on the core type.
92105bb7 TL	104	* Note that we cannot try to test for SRAM here because writes
	105	* to secure SRAM will hang the system. Also the SRAM is not
	106	* yet mapped at this point.
	107	*/
b0a330dc	108	static void __init omap_detect_sram(void)
92105bb7	109	{
b2856734	110	omap_sram_skip = SRAM_BOOTLOADER_SZ;
c2d43e39	111	if (cpu_class_is_omap2()) {
670c104a	112	if (is_sram_locked()) {
c2d43e39	113	if (cpu_is_omap34xx()) {
c2d43e39	114	omap_sram_start = OMAP3_SRAM_PUB_PA;
5b0acc59 TK	115	if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) \|\|
	116	(omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
	117	omap_sram_size = 0x7000; /* 28K */
b2856734	118	omap_sram_skip += SZ_16K;
5b0acc59 TK	119	} else {
	120	omap_sram_size = 0x8000; /* 32K */
	121	}
a7c3ae2c	122	} else if (cpu_is_omap44xx()) {
a7c3ae2c SS	123	omap_sram_start = OMAP4_SRAM_PUB_PA;
a7c3ae2c SS	124	omap_sram_size = 0xa000; /* 40K */
05e152c7 S	125	} else if (soc_is_omap54xx()) {
	126	omap_sram_start = OMAP5_SRAM_PA;
	127	omap_sram_size = SZ_128K; /* 128KB */
c2d43e39	128	} else {
c2d43e39 TL	129	omap_sram_start = OMAP2_SRAM_PUB_PA;
	130	omap_sram_size = 0x800; /* 2K */
	131	}
670c104a	132	} else {
971b8a9c	133	if (soc_is_am33xx()) {
b4c0a8a7 VB	134	omap_sram_start = AM33XX_SRAM_PA;
	135	omap_sram_size = 0x10000; /* 64K */
	136	} else if (cpu_is_omap34xx()) {
c2d43e39	137	omap_sram_start = OMAP3_SRAM_PA;
670c104a	138	omap_sram_size = 0x10000; /* 64K */
44169075	139	} else if (cpu_is_omap44xx()) {
44169075	140	omap_sram_start = OMAP4_SRAM_PA;
a7c3ae2c	141	omap_sram_size = 0xe000; /* 56K */
05e152c7 S	142	} else if (soc_is_omap54xx()) {
	143	omap_sram_start = OMAP5_SRAM_PA;
	144	omap_sram_size = SZ_128K; /* 128KB */
c2d43e39	145	} else {
c2d43e39 TL	146	omap_sram_start = OMAP2_SRAM_PA;
	147	if (cpu_is_omap242x())
	148	omap_sram_size = 0xa0000; /* 640K */
	149	else if (cpu_is_omap243x())
	150	omap_sram_size = 0x10000; /* 64K */
	151	}
670c104a TL	152	}
670c104a TL	153	} else {
c40fae95	154	omap_sram_start = OMAP1_SRAM_PA;
670c104a	155
557096fe	156	if (cpu_is_omap7xx())
670c104a TL	157	omap_sram_size = 0x32000; /* 200K */
	158	else if (cpu_is_omap15xx())
	159	omap_sram_size = 0x30000; /* 192K */
ee62e93a TL	160	else if (cpu_is_omap1610() \|\| cpu_is_omap1611() \|\|
ee62e93a TL	161	cpu_is_omap1621() \|\| cpu_is_omap1710())
670c104a	162	omap_sram_size = 0x4000; /* 16K */
670c104a	163	else {
26a510ba	164	pr_err("Could not detect SRAM size\n");
670c104a TL	165	omap_sram_size = 0x4000;
670c104a TL	166	}
92105bb7	167	}
92105bb7 TL	168	}
92105bb7 TL	169
92105bb7	170	/*
ce2deca2	171	* Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
92105bb7	172	*/
b0a330dc	173	static void __init omap_map_sram(void)
92105bb7	174	{
a66cb345	175	int cached = 1;
670c104a	176
92105bb7 TL	177	if (omap_sram_size == 0)
	178	return;
	179
137d105d	180	#ifdef CONFIG_OMAP4_ERRATA_I688
528c28f5	181	if (cpu_is_omap44xx()) {
137d105d SS	182	omap_sram_start += PAGE_SIZE;
137d105d SS	183	omap_sram_size -= SZ_16K;
528c28f5	184	}
137d105d	185	#endif
c2d43e39	186	if (cpu_is_omap34xx()) {
d9295746 PW	187	/*
	188	* SRAM must be marked as non-cached on OMAP3 since the
	189	* CORE DPLL M2 divider change code (in SRAM) runs with the
	190	* SDRAM controller disabled, and if it is marked cached,
	191	* the ARM may attempt to write cache lines back to SDRAM
	192	* which will cause the system to hang.
	193	*/
a66cb345	194	cached = 0;
c2d43e39 TL	195	}
c2d43e39 TL	196
a66cb345 TL	197	omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
	198	omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size,
	199	cached);
	200	if (!omap_sram_base) {
	201	pr_err("SRAM: Could not map\n");
	202	return;
	203	}
1a8bfa1e	204
a66cb345	205	omap_sram_ceil = omap_sram_base + omap_sram_size;
53d9cc73	206
92105bb7 TL	207	/*
	208	* Looks like we need to preserve some bootloader code at the
	209	* beginning of SRAM for jumping to flash for reboot to work...
	210	*/
b2856734 AK	211	memset_io(omap_sram_base + omap_sram_skip, 0,
b2856734 AK	212	omap_sram_size - omap_sram_skip);
92105bb7 TL	213	}
92105bb7 TL	214
b6338bdc JP	215	/*
	216	* Memory allocator for SRAM: calculates the new ceiling address
	217	* for pushing a function using the fncpy API.
	218	*
	219	* Note that fncpy requires the returned address to be aligned
	220	* to an 8-byte boundary.
	221	*/
	222	void *omap_sram_push_address(unsigned long size)
92105bb7	223	{
a66cb345 TL	224	unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;
a66cb345 TL	225
b2856734	226	available = omap_sram_ceil - (omap_sram_base + omap_sram_skip);
a66cb345 TL	227
a66cb345 TL	228	if (size > available) {
26a510ba	229	pr_err("Not enough space in SRAM\n");
92105bb7 TL	230	return NULL;
92105bb7 TL	231	}
670c104a	232
a66cb345 TL	233	new_ceil -= size;
	234	new_ceil = ROUND_DOWN(new_ceil, FNCPY_ALIGN);
	235	omap_sram_ceil = IOMEM(new_ceil);
92105bb7 TL	236
	237	return (void *)omap_sram_ceil;
	238	}
	239
1a8bfa1e TL	240	#ifdef CONFIG_ARCH_OMAP1
	241
	242	static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
	243
	244	void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
	245	{
da7a0649	246	BUG_ON(!_omap_sram_reprogram_clock);
f9e5908f JK	247	/* On 730, bit 13 must always be 1 */
	248	if (cpu_is_omap7xx())
	249	ckctl \|= 0x2000;
020f9706	250	_omap_sram_reprogram_clock(dpllctl, ckctl);
1a8bfa1e TL	251	}
1a8bfa1e TL	252
e6f16821	253	static int __init omap1_sram_init(void)
92105bb7	254	{
c2d43e39 TL	255	_omap_sram_reprogram_clock =
	256	omap_sram_push(omap1_sram_reprogram_clock,
	257	omap1_sram_reprogram_clock_sz);
1a8bfa1e TL	258
	259	return 0;
	260	}
	261
	262	#else
	263	#define omap1_sram_init() do {} while (0)
	264	#endif
	265
cc26b3b0	266	#if defined(CONFIG_ARCH_OMAP2)
1a8bfa1e TL	267
	268	static void (_omap2_sram_ddr_init)(u32 slow_dll_ctrl, u32 fast_dll_ctrl,
	269	u32 base_cs, u32 force_unlock);
	270
	271	void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
	272	u32 base_cs, u32 force_unlock)
	273	{
da7a0649	274	BUG_ON(!_omap2_sram_ddr_init);
020f9706 RK	275	_omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
020f9706 RK	276	base_cs, force_unlock);
1a8bfa1e TL	277	}
	278
	279	static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
	280	u32 mem_type);
	281
	282	void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
	283	{
da7a0649	284	BUG_ON(!_omap2_sram_reprogram_sdrc);
020f9706	285	_omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
1a8bfa1e TL	286	}
	287
	288	static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
	289
	290	u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
	291	{
da7a0649	292	BUG_ON(!_omap2_set_prcm);
1a8bfa1e TL	293	return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
1a8bfa1e TL	294	}
c2d43e39 TL	295	#endif
c2d43e39 TL	296
59b479e0	297	#ifdef CONFIG_SOC_OMAP2420
b0a330dc	298	static int __init omap242x_sram_init(void)
c2d43e39 TL	299	{
	300	_omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
	301	omap242x_sram_ddr_init_sz);
	302
	303	_omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
	304	omap242x_sram_reprogram_sdrc_sz);
	305
	306	_omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
	307	omap242x_sram_set_prcm_sz);
	308
	309	return 0;
	310	}
	311	#else
	312	static inline int omap242x_sram_init(void)
	313	{
	314	return 0;
	315	}
	316	#endif
	317
59b479e0	318	#ifdef CONFIG_SOC_OMAP2430
b0a330dc	319	static int __init omap243x_sram_init(void)
c2d43e39 TL	320	{
	321	_omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
	322	omap243x_sram_ddr_init_sz);
	323
	324	_omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
	325	omap243x_sram_reprogram_sdrc_sz);
	326
	327	_omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
	328	omap243x_sram_set_prcm_sz);
	329
	330	return 0;
	331	}
	332	#else
	333	static inline int omap243x_sram_init(void)
	334	{
	335	return 0;
	336	}
	337	#endif
	338
	339	#ifdef CONFIG_ARCH_OMAP3
	340
58cda884 JP	341	static u32 (*_omap3_sram_configure_core_dpll)(
	342	u32 m2, u32 unlock_dll, u32 f, u32 inc,
	343	u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
	344	u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
	345	u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
	346	u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
	347
	348	u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
	349	u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
	350	u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
	351	u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
	352	u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
c2d43e39	353	{
da7a0649	354	BUG_ON(!_omap3_sram_configure_core_dpll);
58cda884 JP	355	return _omap3_sram_configure_core_dpll(
	356	m2, unlock_dll, f, inc,
	357	sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
	358	sdrc_actim_ctrl_b_0, sdrc_mr_0,
	359	sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
	360	sdrc_actim_ctrl_b_1, sdrc_mr_1);
c2d43e39	361	}
1a8bfa1e	362
3231fc88	363	void omap3_sram_restore_context(void)
1a8bfa1e	364	{
c2d43e39	365	omap_sram_ceil = omap_sram_base + omap_sram_size;
1a8bfa1e	366
cc26b3b0 SMK	367	_omap3_sram_configure_core_dpll =
	368	omap_sram_push(omap3_sram_configure_core_dpll,
	369	omap3_sram_configure_core_dpll_sz);
3231fc88	370	omap_push_sram_idle();
c2d43e39	371	}
46e130d2	372
c2d43e39 TL	373	static inline int omap34xx_sram_init(void)
c2d43e39 TL	374	{
46e130d2	375	omap3_sram_restore_context();
c2d43e39 TL	376	return 0;
c2d43e39 TL	377	}
63878acf GI	378	#else
	379	static inline int omap34xx_sram_init(void)
	380	{
	381	return 0;
	382	}
	383	#endif /* CONFIG_ARCH_OMAP3 */
1a8bfa1e	384
b4c0a8a7 VB	385	static inline int am33xx_sram_init(void)
	386	{
	387	return 0;
	388	}
	389
1a8bfa1e TL	390	int __init omap_sram_init(void)
	391	{
	392	omap_detect_sram();
	393	omap_map_sram();
	394
c2d43e39	395	if (!(cpu_class_is_omap2()))
1a8bfa1e	396	omap1_sram_init();
c2d43e39 TL	397	else if (cpu_is_omap242x())
	398	omap242x_sram_init();
	399	else if (cpu_is_omap2430())
	400	omap243x_sram_init();
971b8a9c	401	else if (soc_is_am33xx())
b4c0a8a7	402	am33xx_sram_init();
c2d43e39 TL	403	else if (cpu_is_omap34xx())
c2d43e39 TL	404	omap34xx_sram_init();
1a8bfa1e TL	405
1a8bfa1e TL	406	return 0;
92105bb7	407	}