Commit | Line | Data |
---|---|---|
b6d1c33a AL |
1 | /* |
2 | * arch/arm/plat-orion/addr-map.c | |
3 | * | |
4 | * Address map functions for Marvell Orion based SoCs | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public | |
7 | * License version 2. This program is licensed "as is" without any | |
8 | * warranty of any kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/mbus.h> | |
14 | #include <linux/io.h> | |
15 | #include <plat/addr-map.h> | |
16 | ||
17 | /* | |
18 | * DDR target is the same on all Orion platforms. | |
19 | */ | |
20 | #define TARGET_DDR 0 | |
21 | ||
22 | /* | |
23 | * Helpers to get DDR bank info | |
24 | */ | |
25 | #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) | |
26 | #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) | |
27 | ||
28 | /* | |
29 | * CPU Address Decode Windows registers | |
30 | */ | |
31 | #define WIN_CTRL_OFF 0x0000 | |
32 | #define WIN_BASE_OFF 0x0004 | |
33 | #define WIN_REMAP_LO_OFF 0x0008 | |
34 | #define WIN_REMAP_HI_OFF 0x000c | |
35 | ||
36 | /* | |
37 | * Default implementation | |
38 | */ | |
39 | static void __init __iomem * | |
40 | orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win) | |
41 | { | |
42 | return (void __iomem *)(cfg->bridge_virt_base + (win << 4)); | |
43 | } | |
44 | ||
45 | /* | |
46 | * Default implementation | |
47 | */ | |
48 | static int __init orion_cpu_win_can_remap(const struct orion_addr_map_cfg *cfg, | |
49 | const int win) | |
50 | { | |
51 | if (win < cfg->remappable_wins) | |
52 | return 1; | |
53 | ||
54 | return 0; | |
55 | } | |
56 | ||
57 | void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg, | |
58 | const int win, const u32 base, | |
59 | const u32 size, const u8 target, | |
60 | const u8 attr, const int remap) | |
61 | { | |
62 | void __iomem *addr = cfg->win_cfg_base(cfg, win); | |
63 | u32 ctrl, base_high, remap_addr; | |
64 | ||
65 | if (win >= cfg->num_wins) { | |
66 | printk(KERN_ERR "setup_cpu_win: trying to allocate window " | |
67 | "%d when only %d allowed\n", win, cfg->num_wins); | |
68 | } | |
69 | ||
70 | base_high = base & 0xffff0000; | |
71 | ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; | |
72 | ||
73 | writel(base_high, addr + WIN_BASE_OFF); | |
74 | writel(ctrl, addr + WIN_CTRL_OFF); | |
75 | if (cfg->cpu_win_can_remap(cfg, win)) { | |
76 | if (remap < 0) | |
77 | remap_addr = base; | |
78 | else | |
79 | remap_addr = remap; | |
80 | writel(remap_addr & 0xffff0000, addr + WIN_REMAP_LO_OFF); | |
81 | writel(0, addr + WIN_REMAP_HI_OFF); | |
82 | } | |
83 | } | |
84 | ||
85 | /* | |
86 | * Configure a number of windows. | |
87 | */ | |
88 | static void __init orion_setup_cpu_wins(const struct orion_addr_map_cfg * cfg, | |
89 | const struct orion_addr_map_info *info) | |
90 | { | |
91 | while (info->win != -1) { | |
92 | orion_setup_cpu_win(cfg, info->win, info->base, info->size, | |
93 | info->target, info->attr, info->remap); | |
94 | info++; | |
95 | } | |
96 | } | |
97 | ||
98 | static void __init orion_disable_wins(const struct orion_addr_map_cfg * cfg) | |
99 | { | |
100 | void __iomem *addr; | |
101 | int i; | |
102 | ||
103 | for (i = 0; i < cfg->num_wins; i++) { | |
104 | addr = cfg->win_cfg_base(cfg, i); | |
105 | ||
106 | writel(0, addr + WIN_BASE_OFF); | |
107 | writel(0, addr + WIN_CTRL_OFF); | |
108 | if (cfg->cpu_win_can_remap(cfg, i)) { | |
109 | writel(0, addr + WIN_REMAP_LO_OFF); | |
110 | writel(0, addr + WIN_REMAP_HI_OFF); | |
111 | } | |
112 | } | |
113 | } | |
114 | ||
115 | /* | |
116 | * Disable, clear and configure windows. | |
117 | */ | |
118 | void __init orion_config_wins(struct orion_addr_map_cfg * cfg, | |
119 | const struct orion_addr_map_info *info) | |
120 | { | |
121 | if (!cfg->cpu_win_can_remap) | |
122 | cfg->cpu_win_can_remap = orion_cpu_win_can_remap; | |
123 | ||
124 | if (!cfg->win_cfg_base) | |
125 | cfg->win_cfg_base = orion_win_cfg_base; | |
126 | ||
127 | orion_disable_wins(cfg); | |
128 | ||
129 | if (info) | |
130 | orion_setup_cpu_wins(cfg, info); | |
131 | } | |
132 | ||
133 | /* | |
134 | * Setup MBUS dram target info. | |
135 | */ | |
136 | void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, | |
137 | struct mbus_dram_target_info *info, | |
138 | const u32 ddr_window_cpu_base) | |
139 | { | |
140 | void __iomem *addr; | |
141 | int i; | |
142 | int cs; | |
143 | ||
144 | info->mbus_dram_target_id = TARGET_DDR; | |
145 | ||
146 | addr = (void __iomem *)ddr_window_cpu_base; | |
147 | ||
148 | for (i = 0, cs = 0; i < 4; i++) { | |
149 | u32 base = readl(addr + DDR_BASE_CS_OFF(i)); | |
150 | u32 size = readl(addr + DDR_SIZE_CS_OFF(i)); | |
151 | ||
152 | /* | |
153 | * Chip select enabled? | |
154 | */ | |
155 | if (size & 1) { | |
156 | struct mbus_dram_window *w; | |
157 | ||
158 | w = &info->cs[cs++]; | |
159 | w->cs_index = i; | |
160 | w->mbus_attr = 0xf & ~(1 << i); | |
161 | w->base = base & 0xffff0000; | |
162 | w->size = (size | 0x0000ffff) + 1; | |
163 | } | |
164 | } | |
165 | info->num_cs = cs; | |
166 | } |