Commit | Line | Data |
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9569dae7 LB |
1 | /* |
2 | * arch/arm/plat-orion/gpio.c | |
3 | * | |
4 | * Marvell Orion SoC GPIO handling. | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public | |
7 | * License version 2. This program is licensed "as is" without any | |
8 | * warranty of any kind, whether express or implied. | |
9 | */ | |
10 | ||
278b45b0 AL |
11 | #define DEBUG |
12 | ||
9569dae7 LB |
13 | #include <linux/kernel.h> |
14 | #include <linux/init.h> | |
07332318 | 15 | #include <linux/irq.h> |
278b45b0 | 16 | #include <linux/irqdomain.h> |
9569dae7 LB |
17 | #include <linux/module.h> |
18 | #include <linux/spinlock.h> | |
19 | #include <linux/bitops.h> | |
20 | #include <linux/io.h> | |
a8865655 | 21 | #include <linux/gpio.h> |
ff3e660b | 22 | #include <linux/leds.h> |
278b45b0 AL |
23 | #include <linux/of.h> |
24 | #include <linux/of_irq.h> | |
25 | #include <linux/of_address.h> | |
26 | #include <plat/gpio.h> | |
9569dae7 | 27 | |
9eac6d0a LB |
28 | /* |
29 | * GPIO unit register offsets. | |
30 | */ | |
31 | #define GPIO_OUT_OFF 0x0000 | |
32 | #define GPIO_IO_CONF_OFF 0x0004 | |
33 | #define GPIO_BLINK_EN_OFF 0x0008 | |
34 | #define GPIO_IN_POL_OFF 0x000c | |
35 | #define GPIO_DATA_IN_OFF 0x0010 | |
36 | #define GPIO_EDGE_CAUSE_OFF 0x0014 | |
37 | #define GPIO_EDGE_MASK_OFF 0x0018 | |
38 | #define GPIO_LEVEL_MASK_OFF 0x001c | |
39 | ||
40 | struct orion_gpio_chip { | |
41 | struct gpio_chip chip; | |
42 | spinlock_t lock; | |
43 | void __iomem *base; | |
44 | unsigned long valid_input; | |
45 | unsigned long valid_output; | |
46 | int mask_offset; | |
47 | int secondary_irq_base; | |
278b45b0 | 48 | struct irq_domain *domain; |
9eac6d0a LB |
49 | }; |
50 | ||
51 | static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip) | |
52 | { | |
53 | return ochip->base + GPIO_OUT_OFF; | |
54 | } | |
55 | ||
56 | static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip) | |
57 | { | |
58 | return ochip->base + GPIO_IO_CONF_OFF; | |
59 | } | |
60 | ||
61 | static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip) | |
62 | { | |
63 | return ochip->base + GPIO_BLINK_EN_OFF; | |
64 | } | |
65 | ||
66 | static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip) | |
67 | { | |
68 | return ochip->base + GPIO_IN_POL_OFF; | |
69 | } | |
70 | ||
71 | static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip) | |
72 | { | |
73 | return ochip->base + GPIO_DATA_IN_OFF; | |
74 | } | |
75 | ||
76 | static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip) | |
77 | { | |
78 | return ochip->base + GPIO_EDGE_CAUSE_OFF; | |
79 | } | |
80 | ||
81 | static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip) | |
82 | { | |
83 | return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF; | |
84 | } | |
85 | ||
86 | static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip) | |
87 | { | |
88 | return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF; | |
89 | } | |
90 | ||
9569dae7 | 91 | |
9eac6d0a LB |
92 | static struct orion_gpio_chip orion_gpio_chips[2]; |
93 | static int orion_gpio_chip_count; | |
94 | ||
95 | static inline void | |
96 | __set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input) | |
9569dae7 LB |
97 | { |
98 | u32 u; | |
99 | ||
9eac6d0a | 100 | u = readl(GPIO_IO_CONF(ochip)); |
9569dae7 | 101 | if (input) |
9eac6d0a | 102 | u |= 1 << pin; |
9569dae7 | 103 | else |
9eac6d0a LB |
104 | u &= ~(1 << pin); |
105 | writel(u, GPIO_IO_CONF(ochip)); | |
9569dae7 LB |
106 | } |
107 | ||
9eac6d0a | 108 | static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high) |
9569dae7 LB |
109 | { |
110 | u32 u; | |
111 | ||
9eac6d0a | 112 | u = readl(GPIO_OUT(ochip)); |
9569dae7 | 113 | if (high) |
9eac6d0a | 114 | u |= 1 << pin; |
9569dae7 | 115 | else |
9eac6d0a LB |
116 | u &= ~(1 << pin); |
117 | writel(u, GPIO_OUT(ochip)); | |
9569dae7 LB |
118 | } |
119 | ||
9eac6d0a LB |
120 | static inline void |
121 | __set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink) | |
9569dae7 | 122 | { |
a8865655 | 123 | u32 u; |
9569dae7 | 124 | |
9eac6d0a | 125 | u = readl(GPIO_BLINK_EN(ochip)); |
a8865655 | 126 | if (blink) |
9eac6d0a | 127 | u |= 1 << pin; |
a8865655 | 128 | else |
9eac6d0a LB |
129 | u &= ~(1 << pin); |
130 | writel(u, GPIO_BLINK_EN(ochip)); | |
a8865655 | 131 | } |
9569dae7 | 132 | |
9eac6d0a LB |
133 | static inline int |
134 | orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode) | |
a8865655 | 135 | { |
9eac6d0a LB |
136 | if (pin >= ochip->chip.ngpio) |
137 | goto err_out; | |
138 | ||
139 | if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input)) | |
140 | goto err_out; | |
141 | ||
142 | if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output)) | |
143 | goto err_out; | |
144 | ||
145 | return 1; | |
9569dae7 | 146 | |
a8865655 EB |
147 | err_out: |
148 | pr_debug("%s: invalid GPIO %d\n", __func__, pin); | |
149 | return false; | |
9569dae7 | 150 | } |
9569dae7 | 151 | |
a8865655 EB |
152 | /* |
153 | * GENERIC_GPIO primitives. | |
154 | */ | |
9eac6d0a LB |
155 | static int orion_gpio_request(struct gpio_chip *chip, unsigned pin) |
156 | { | |
157 | struct orion_gpio_chip *ochip = | |
158 | container_of(chip, struct orion_gpio_chip, chip); | |
159 | ||
160 | if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) || | |
161 | orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK)) | |
162 | return 0; | |
163 | ||
164 | return -EINVAL; | |
165 | } | |
166 | ||
a8865655 | 167 | static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin) |
9569dae7 | 168 | { |
9eac6d0a LB |
169 | struct orion_gpio_chip *ochip = |
170 | container_of(chip, struct orion_gpio_chip, chip); | |
9569dae7 | 171 | unsigned long flags; |
9569dae7 | 172 | |
9eac6d0a | 173 | if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK)) |
9569dae7 | 174 | return -EINVAL; |
9569dae7 | 175 | |
9eac6d0a LB |
176 | spin_lock_irqsave(&ochip->lock, flags); |
177 | __set_direction(ochip, pin, 1); | |
178 | spin_unlock_irqrestore(&ochip->lock, flags); | |
9569dae7 LB |
179 | |
180 | return 0; | |
181 | } | |
9569dae7 | 182 | |
9eac6d0a | 183 | static int orion_gpio_get(struct gpio_chip *chip, unsigned pin) |
9569dae7 | 184 | { |
9eac6d0a LB |
185 | struct orion_gpio_chip *ochip = |
186 | container_of(chip, struct orion_gpio_chip, chip); | |
9569dae7 LB |
187 | int val; |
188 | ||
9eac6d0a LB |
189 | if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) { |
190 | val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip)); | |
191 | } else { | |
192 | val = readl(GPIO_OUT(ochip)); | |
193 | } | |
9569dae7 | 194 | |
9eac6d0a | 195 | return (val >> pin) & 1; |
9569dae7 | 196 | } |
9569dae7 | 197 | |
9eac6d0a LB |
198 | static int |
199 | orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value) | |
9569dae7 | 200 | { |
9eac6d0a LB |
201 | struct orion_gpio_chip *ochip = |
202 | container_of(chip, struct orion_gpio_chip, chip); | |
9569dae7 | 203 | unsigned long flags; |
a8865655 | 204 | |
9eac6d0a | 205 | if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK)) |
a8865655 | 206 | return -EINVAL; |
9569dae7 | 207 | |
9eac6d0a LB |
208 | spin_lock_irqsave(&ochip->lock, flags); |
209 | __set_blinking(ochip, pin, 0); | |
210 | __set_level(ochip, pin, value); | |
211 | __set_direction(ochip, pin, 0); | |
212 | spin_unlock_irqrestore(&ochip->lock, flags); | |
a8865655 EB |
213 | |
214 | return 0; | |
9569dae7 | 215 | } |
9569dae7 | 216 | |
9eac6d0a | 217 | static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value) |
9569dae7 | 218 | { |
9eac6d0a LB |
219 | struct orion_gpio_chip *ochip = |
220 | container_of(chip, struct orion_gpio_chip, chip); | |
9569dae7 | 221 | unsigned long flags; |
9569dae7 | 222 | |
9eac6d0a LB |
223 | spin_lock_irqsave(&ochip->lock, flags); |
224 | __set_level(ochip, pin, value); | |
225 | spin_unlock_irqrestore(&ochip->lock, flags); | |
9569dae7 | 226 | } |
9569dae7 | 227 | |
9eac6d0a | 228 | static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin) |
9569dae7 | 229 | { |
9eac6d0a LB |
230 | struct orion_gpio_chip *ochip = |
231 | container_of(chip, struct orion_gpio_chip, chip); | |
9569dae7 | 232 | |
278b45b0 AL |
233 | return irq_create_mapping(ochip->domain, |
234 | ochip->secondary_irq_base + pin); | |
a8865655 | 235 | } |
9569dae7 LB |
236 | |
237 | /* | |
238 | * Orion-specific GPIO API extensions. | |
239 | */ | |
9eac6d0a LB |
240 | static struct orion_gpio_chip *orion_gpio_chip_find(int pin) |
241 | { | |
242 | int i; | |
243 | ||
244 | for (i = 0; i < orion_gpio_chip_count; i++) { | |
245 | struct orion_gpio_chip *ochip = orion_gpio_chips + i; | |
246 | struct gpio_chip *chip = &ochip->chip; | |
247 | ||
248 | if (pin >= chip->base && pin < chip->base + chip->ngpio) | |
249 | return ochip; | |
250 | } | |
251 | ||
252 | return NULL; | |
253 | } | |
254 | ||
9569dae7 LB |
255 | void __init orion_gpio_set_unused(unsigned pin) |
256 | { | |
9eac6d0a LB |
257 | struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin); |
258 | ||
259 | if (ochip == NULL) | |
260 | return; | |
261 | ||
262 | pin -= ochip->chip.base; | |
263 | ||
a8865655 | 264 | /* Configure as output, drive low. */ |
9eac6d0a LB |
265 | __set_level(ochip, pin, 0); |
266 | __set_direction(ochip, pin, 0); | |
9569dae7 LB |
267 | } |
268 | ||
28d27cf4 | 269 | void __init orion_gpio_set_valid(unsigned pin, int mode) |
9569dae7 | 270 | { |
9eac6d0a LB |
271 | struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin); |
272 | ||
273 | if (ochip == NULL) | |
274 | return; | |
275 | ||
276 | pin -= ochip->chip.base; | |
277 | ||
28d27cf4 NP |
278 | if (mode == 1) |
279 | mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK; | |
9eac6d0a | 280 | |
28d27cf4 | 281 | if (mode & GPIO_INPUT_OK) |
9eac6d0a | 282 | __set_bit(pin, &ochip->valid_input); |
9569dae7 | 283 | else |
9eac6d0a LB |
284 | __clear_bit(pin, &ochip->valid_input); |
285 | ||
28d27cf4 | 286 | if (mode & GPIO_OUTPUT_OK) |
9eac6d0a | 287 | __set_bit(pin, &ochip->valid_output); |
28d27cf4 | 288 | else |
9eac6d0a | 289 | __clear_bit(pin, &ochip->valid_output); |
9569dae7 LB |
290 | } |
291 | ||
292 | void orion_gpio_set_blink(unsigned pin, int blink) | |
293 | { | |
9eac6d0a | 294 | struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin); |
9569dae7 | 295 | unsigned long flags; |
9569dae7 | 296 | |
9eac6d0a LB |
297 | if (ochip == NULL) |
298 | return; | |
9569dae7 | 299 | |
9eac6d0a | 300 | spin_lock_irqsave(&ochip->lock, flags); |
92a486ea APR |
301 | __set_level(ochip, pin & 31, 0); |
302 | __set_blinking(ochip, pin & 31, blink); | |
9eac6d0a | 303 | spin_unlock_irqrestore(&ochip->lock, flags); |
9569dae7 LB |
304 | } |
305 | EXPORT_SYMBOL(orion_gpio_set_blink); | |
07332318 | 306 | |
ff3e660b APR |
307 | #define ORION_BLINK_HALF_PERIOD 100 /* ms */ |
308 | ||
309 | int orion_gpio_led_blink_set(unsigned gpio, int state, | |
310 | unsigned long *delay_on, unsigned long *delay_off) | |
311 | { | |
312 | ||
313 | if (delay_on && delay_off && !*delay_on && !*delay_off) | |
314 | *delay_on = *delay_off = ORION_BLINK_HALF_PERIOD; | |
315 | ||
316 | switch (state) { | |
317 | case GPIO_LED_NO_BLINK_LOW: | |
318 | case GPIO_LED_NO_BLINK_HIGH: | |
319 | orion_gpio_set_blink(gpio, 0); | |
320 | gpio_set_value(gpio, state); | |
321 | break; | |
322 | case GPIO_LED_BLINK: | |
323 | orion_gpio_set_blink(gpio, 1); | |
324 | } | |
325 | return 0; | |
326 | } | |
327 | EXPORT_SYMBOL_GPL(orion_gpio_led_blink_set); | |
328 | ||
07332318 LB |
329 | |
330 | /***************************************************************************** | |
331 | * Orion GPIO IRQ | |
332 | * | |
333 | * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same | |
334 | * value of the line or the opposite value. | |
335 | * | |
336 | * Level IRQ handlers: DATA_IN is used directly as cause register. | |
337 | * Interrupt are masked by LEVEL_MASK registers. | |
338 | * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. | |
339 | * Interrupt are masked by EDGE_MASK registers. | |
340 | * Both-edge handlers: Similar to regular Edge handlers, but also swaps | |
341 | * the polarity to catch the next line transaction. | |
342 | * This is a race condition that might not perfectly | |
343 | * work on some use cases. | |
344 | * | |
345 | * Every eight GPIO lines are grouped (OR'ed) before going up to main | |
346 | * cause register. | |
347 | * | |
348 | * EDGE cause mask | |
349 | * data-in /--------| |-----| |----\ | |
350 | * -----| |----- ---- to main cause reg | |
351 | * X \----------------| |----/ | |
352 | * polarity LEVEL mask | |
353 | * | |
354 | ****************************************************************************/ | |
07332318 | 355 | |
3b0c8d40 | 356 | static int gpio_irq_set_type(struct irq_data *d, u32 type) |
07332318 | 357 | { |
e59347a1 TG |
358 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
359 | struct irq_chip_type *ct = irq_data_get_chip_type(d); | |
360 | struct orion_gpio_chip *ochip = gc->private; | |
9eac6d0a | 361 | int pin; |
07332318 LB |
362 | u32 u; |
363 | ||
278b45b0 | 364 | pin = d->hwirq - ochip->secondary_irq_base; |
9eac6d0a LB |
365 | |
366 | u = readl(GPIO_IO_CONF(ochip)) & (1 << pin); | |
07332318 | 367 | if (!u) { |
07332318 LB |
368 | return -EINVAL; |
369 | } | |
370 | ||
e59347a1 TG |
371 | type &= IRQ_TYPE_SENSE_MASK; |
372 | if (type == IRQ_TYPE_NONE) | |
07332318 | 373 | return -EINVAL; |
e59347a1 TG |
374 | |
375 | /* Check if we need to change chip and handler */ | |
376 | if (!(ct->type & type)) | |
377 | if (irq_setup_alt_chip(d, type)) | |
378 | return -EINVAL; | |
07332318 LB |
379 | |
380 | /* | |
381 | * Configure interrupt polarity. | |
382 | */ | |
383 | if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) { | |
9eac6d0a LB |
384 | u = readl(GPIO_IN_POL(ochip)); |
385 | u &= ~(1 << pin); | |
386 | writel(u, GPIO_IN_POL(ochip)); | |
07332318 | 387 | } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) { |
9eac6d0a LB |
388 | u = readl(GPIO_IN_POL(ochip)); |
389 | u |= 1 << pin; | |
390 | writel(u, GPIO_IN_POL(ochip)); | |
07332318 LB |
391 | } else if (type == IRQ_TYPE_EDGE_BOTH) { |
392 | u32 v; | |
393 | ||
9eac6d0a | 394 | v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip)); |
07332318 LB |
395 | |
396 | /* | |
397 | * set initial polarity based on current input level | |
398 | */ | |
9eac6d0a LB |
399 | u = readl(GPIO_IN_POL(ochip)); |
400 | if (v & (1 << pin)) | |
401 | u |= 1 << pin; /* falling */ | |
07332318 | 402 | else |
9eac6d0a LB |
403 | u &= ~(1 << pin); /* rising */ |
404 | writel(u, GPIO_IN_POL(ochip)); | |
07332318 | 405 | } |
07332318 LB |
406 | return 0; |
407 | } | |
408 | ||
278b45b0 AL |
409 | static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) |
410 | { | |
411 | struct orion_gpio_chip *ochip = irq_get_handler_data(irq); | |
412 | u32 cause, type; | |
413 | int i; | |
414 | ||
415 | if (ochip == NULL) | |
416 | return; | |
417 | ||
418 | cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip)); | |
419 | cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip)); | |
420 | ||
421 | for (i = 0; i < ochip->chip.ngpio; i++) { | |
422 | int irq; | |
423 | ||
424 | irq = ochip->secondary_irq_base + i; | |
425 | ||
426 | if (!(cause & (1 << i))) | |
427 | continue; | |
428 | ||
429 | type = irqd_get_trigger_type(irq_get_irq_data(irq)); | |
430 | if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { | |
431 | /* Swap polarity (race with GPIO line) */ | |
432 | u32 polarity; | |
433 | ||
434 | polarity = readl(GPIO_IN_POL(ochip)); | |
435 | polarity ^= 1 << i; | |
436 | writel(polarity, GPIO_IN_POL(ochip)); | |
437 | } | |
438 | generic_handle_irq(irq); | |
439 | } | |
440 | } | |
441 | ||
442 | void __init orion_gpio_init(struct device_node *np, | |
443 | int gpio_base, int ngpio, | |
444 | void __iomem *base, int mask_offset, | |
445 | int secondary_irq_base, | |
446 | int irqs[4]) | |
9eac6d0a LB |
447 | { |
448 | struct orion_gpio_chip *ochip; | |
e59347a1 TG |
449 | struct irq_chip_generic *gc; |
450 | struct irq_chip_type *ct; | |
0b35a45b | 451 | char gc_label[16]; |
278b45b0 | 452 | int i; |
9eac6d0a LB |
453 | |
454 | if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips)) | |
455 | return; | |
456 | ||
0b35a45b HB |
457 | snprintf(gc_label, sizeof(gc_label), "orion_gpio%d", |
458 | orion_gpio_chip_count); | |
459 | ||
9eac6d0a | 460 | ochip = orion_gpio_chips + orion_gpio_chip_count; |
0b35a45b | 461 | ochip->chip.label = kstrdup(gc_label, GFP_KERNEL); |
9eac6d0a LB |
462 | ochip->chip.request = orion_gpio_request; |
463 | ochip->chip.direction_input = orion_gpio_direction_input; | |
464 | ochip->chip.get = orion_gpio_get; | |
465 | ochip->chip.direction_output = orion_gpio_direction_output; | |
466 | ochip->chip.set = orion_gpio_set; | |
467 | ochip->chip.to_irq = orion_gpio_to_irq; | |
468 | ochip->chip.base = gpio_base; | |
469 | ochip->chip.ngpio = ngpio; | |
470 | ochip->chip.can_sleep = 0; | |
278b45b0 AL |
471 | #ifdef CONFIG_OF |
472 | ochip->chip.of_node = np; | |
473 | #endif | |
474 | ||
9eac6d0a LB |
475 | spin_lock_init(&ochip->lock); |
476 | ochip->base = (void __iomem *)base; | |
477 | ochip->valid_input = 0; | |
478 | ochip->valid_output = 0; | |
479 | ochip->mask_offset = mask_offset; | |
480 | ochip->secondary_irq_base = secondary_irq_base; | |
481 | ||
482 | gpiochip_add(&ochip->chip); | |
483 | ||
9eac6d0a LB |
484 | /* |
485 | * Mask and clear GPIO interrupts. | |
486 | */ | |
487 | writel(0, GPIO_EDGE_CAUSE(ochip)); | |
488 | writel(0, GPIO_EDGE_MASK(ochip)); | |
489 | writel(0, GPIO_LEVEL_MASK(ochip)); | |
490 | ||
278b45b0 AL |
491 | /* Setup the interrupt handlers. Each chip can have up to 4 |
492 | * interrupt handlers, with each handler dealing with 8 GPIO | |
493 | * pins. */ | |
494 | ||
495 | for (i = 0; i < 4; i++) { | |
496 | if (irqs[i]) { | |
497 | irq_set_handler_data(irqs[i], ochip); | |
498 | irq_set_chained_handler(irqs[i], gpio_irq_handler); | |
499 | } | |
500 | } | |
501 | ||
502 | gc = irq_alloc_generic_chip("orion_gpio_irq", 2, | |
503 | secondary_irq_base, | |
e59347a1 TG |
504 | ochip->base, handle_level_irq); |
505 | gc->private = ochip; | |
e59347a1 TG |
506 | ct = gc->chip_types; |
507 | ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF; | |
508 | ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; | |
509 | ct->chip.irq_mask = irq_gc_mask_clr_bit; | |
510 | ct->chip.irq_unmask = irq_gc_mask_set_bit; | |
511 | ct->chip.irq_set_type = gpio_irq_set_type; | |
278b45b0 | 512 | ct->chip.name = ochip->chip.label; |
e59347a1 TG |
513 | |
514 | ct++; | |
515 | ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF; | |
516 | ct->regs.ack = GPIO_EDGE_CAUSE_OFF; | |
517 | ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | |
659fb32d | 518 | ct->chip.irq_ack = irq_gc_ack_clr_bit; |
e59347a1 TG |
519 | ct->chip.irq_mask = irq_gc_mask_clr_bit; |
520 | ct->chip.irq_unmask = irq_gc_mask_set_bit; | |
521 | ct->chip.irq_set_type = gpio_irq_set_type; | |
522 | ct->handler = handle_edge_irq; | |
278b45b0 | 523 | ct->chip.name = ochip->chip.label; |
e59347a1 TG |
524 | |
525 | irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE, | |
526 | IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); | |
9eac6d0a | 527 | |
278b45b0 AL |
528 | /* Setup irq domain on top of the generic chip. */ |
529 | ochip->domain = irq_domain_add_legacy(np, | |
530 | ochip->chip.ngpio, | |
531 | ochip->secondary_irq_base, | |
532 | ochip->secondary_irq_base, | |
533 | &irq_domain_simple_ops, | |
534 | ochip); | |
535 | if (!ochip->domain) | |
536 | panic("%s: couldn't allocate irq domain (DT).\n", | |
537 | ochip->chip.label); | |
9eac6d0a | 538 | |
278b45b0 AL |
539 | orion_gpio_chip_count++; |
540 | } | |
9eac6d0a | 541 | |
278b45b0 AL |
542 | #ifdef CONFIG_OF |
543 | static void __init orion_gpio_of_init_one(struct device_node *np, | |
544 | int irq_gpio_base) | |
545 | { | |
546 | int ngpio, gpio_base, mask_offset; | |
547 | void __iomem *base; | |
548 | int ret, i; | |
549 | int irqs[4]; | |
550 | int secondary_irq_base; | |
551 | ||
552 | ret = of_property_read_u32(np, "ngpio", &ngpio); | |
553 | if (ret) | |
554 | goto out; | |
555 | ret = of_property_read_u32(np, "mask-offset", &mask_offset); | |
556 | if (ret == -EINVAL) | |
557 | mask_offset = 0; | |
558 | else | |
559 | goto out; | |
560 | base = of_iomap(np, 0); | |
561 | if (!base) | |
562 | goto out; | |
563 | ||
564 | secondary_irq_base = irq_gpio_base + (32 * orion_gpio_chip_count); | |
565 | gpio_base = 32 * orion_gpio_chip_count; | |
566 | ||
567 | /* Get the interrupt numbers. Each chip can have up to 4 | |
568 | * interrupt handlers, with each handler dealing with 8 GPIO | |
569 | * pins. */ | |
570 | ||
571 | for (i = 0; i < 4; i++) | |
572 | irqs[i] = irq_of_parse_and_map(np, i); | |
573 | ||
574 | orion_gpio_init(np, gpio_base, ngpio, base, mask_offset, | |
575 | secondary_irq_base, irqs); | |
576 | return; | |
577 | out: | |
578 | pr_err("%s: %s: missing mandatory property\n", __func__, np->name); | |
579 | } | |
07332318 | 580 | |
278b45b0 AL |
581 | void __init orion_gpio_of_init(int irq_gpio_base) |
582 | { | |
583 | struct device_node *np; | |
07332318 | 584 | |
278b45b0 AL |
585 | for_each_compatible_node(np, NULL, "marvell,orion-gpio") |
586 | orion_gpio_of_init_one(np, irq_gpio_base); | |
07332318 | 587 | } |
278b45b0 | 588 | #endif |