[deliverable/linux.git] / arch / arm / plat-orion / gpio.c

/*
 * arch/arm/plat-orion/gpio.c
 *
 * Marvell Orion SoC GPIO handling.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <asm/gpio.h>

static DEFINE_SPINLOCK(gpio_lock);
static const char *gpio_label[GPIO_MAX];  /* non null for allocated GPIOs */
static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)];

static inline void __set_direction(unsigned pin, int input)
{
	u32 u;

	u = readl(GPIO_IO_CONF(pin));
	if (input)
		u |= 1 << (pin & 31);
	else
		u &= ~(1 << (pin & 31));
	writel(u, GPIO_IO_CONF(pin));
}

static void __set_level(unsigned pin, int high)
{
	u32 u;

	u = readl(GPIO_OUT(pin));
	if (high)
		u |= 1 << (pin & 31);
	else
		u &= ~(1 << (pin & 31));
	writel(u, GPIO_OUT(pin));
}


/*
 * GENERIC_GPIO primitives.
 */
int gpio_direction_input(unsigned pin)
{
	unsigned long flags;

	if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
		pr_debug("%s: invalid GPIO %d\n", __func__, pin);
		return -EINVAL;
	}

	spin_lock_irqsave(&gpio_lock, flags);

	/*
	 * Some callers might not have used gpio_request(),
	 * so flag this pin as requested now.
	 */
	if (gpio_label[pin] == NULL)
		gpio_label[pin] = "?";

	/*
	 * Configure GPIO direction.
	 */
	__set_direction(pin, 1);

	spin_unlock_irqrestore(&gpio_lock, flags);

	return 0;
}
EXPORT_SYMBOL(gpio_direction_input);

int gpio_direction_output(unsigned pin, int value)
{
	unsigned long flags;
	u32 u;

	if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
		pr_debug("%s: invalid GPIO %d\n", __func__, pin);
		return -EINVAL;
	}

	spin_lock_irqsave(&gpio_lock, flags);

	/*
	 * Some callers might not have used gpio_request(),
	 * so flag this pin as requested now.
	 */
	if (gpio_label[pin] == NULL)
		gpio_label[pin] = "?";

	/*
	 * Disable blinking.
	 */
	u = readl(GPIO_BLINK_EN(pin));
	u &= ~(1 << (pin & 31));
	writel(u, GPIO_BLINK_EN(pin));

	/*
	 * Configure GPIO output value.
	 */
	__set_level(pin, value);

	/*
	 * Configure GPIO direction.
	 */
	__set_direction(pin, 0);

	spin_unlock_irqrestore(&gpio_lock, flags);

	return 0;
}
EXPORT_SYMBOL(gpio_direction_output);

int gpio_get_value(unsigned pin)
{
	int val;

	if (readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31)))
		val = readl(GPIO_DATA_IN(pin)) ^ readl(GPIO_IN_POL(pin));
	else
		val = readl(GPIO_OUT(pin));

	return (val >> (pin & 31)) & 1;
}
EXPORT_SYMBOL(gpio_get_value);

void gpio_set_value(unsigned pin, int value)
{
	unsigned long flags;
	u32 u;

	spin_lock_irqsave(&gpio_lock, flags);

	/*
	 * Disable blinking.
	 */
	u = readl(GPIO_BLINK_EN(pin));
	u &= ~(1 << (pin & 31));
	writel(u, GPIO_BLINK_EN(pin));

	/*
	 * Configure GPIO output value.
	 */
	__set_level(pin, value);

	spin_unlock_irqrestore(&gpio_lock, flags);
}
EXPORT_SYMBOL(gpio_set_value);

int gpio_request(unsigned pin, const char *label)
{
	unsigned long flags;
	int ret;

	if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
		pr_debug("%s: invalid GPIO %d\n", __func__, pin);
		return -EINVAL;
	}

	spin_lock_irqsave(&gpio_lock, flags);
	if (gpio_label[pin] == NULL) {
		gpio_label[pin] = label ? label : "?";
		ret = 0;
	} else {
		pr_debug("%s: GPIO %d already used as %s\n",
			 __func__, pin, gpio_label[pin]);
		ret = -EBUSY;
	}
	spin_unlock_irqrestore(&gpio_lock, flags);

	return ret;
}
EXPORT_SYMBOL(gpio_request);

void gpio_free(unsigned pin)
{
	if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) {
		pr_debug("%s: invalid GPIO %d\n", __func__, pin);
		return;
	}

	if (gpio_label[pin] == NULL)
		pr_warning("%s: GPIO %d already freed\n", __func__, pin);
	else
		gpio_label[pin] = NULL;
}
EXPORT_SYMBOL(gpio_free);


/*
 * Orion-specific GPIO API extensions.
 */
void __init orion_gpio_set_unused(unsigned pin)
{
	/*
	 * Configure as output, drive low.
	 */
	__set_level(pin, 0);
	__set_direction(pin, 0);
}

void __init orion_gpio_set_valid(unsigned pin, int valid)
{
	if (valid)
		__set_bit(pin, gpio_valid);
	else
		__clear_bit(pin, gpio_valid);
}

void orion_gpio_set_blink(unsigned pin, int blink)
{
	unsigned long flags;
	u32 u;

	spin_lock_irqsave(&gpio_lock, flags);

	/*
	 * Set output value to zero.
	 */
	__set_level(pin, 0);

	u = readl(GPIO_BLINK_EN(pin));
	if (blink)
		u |= 1 << (pin & 31);
	else
		u &= ~(1 << (pin & 31));
	writel(u, GPIO_BLINK_EN(pin));

	spin_unlock_irqrestore(&gpio_lock, flags);
}
EXPORT_SYMBOL(orion_gpio_set_blink);


/*****************************************************************************
 * Orion GPIO IRQ
 *
 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
 * value of the line or the opposite value.
 *
 * Level IRQ handlers: DATA_IN is used directly as cause register.
 *                     Interrupt are masked by LEVEL_MASK registers.
 * Edge IRQ handlers:  Change in DATA_IN are latched in EDGE_CAUSE.
 *                     Interrupt are masked by EDGE_MASK registers.
 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
 *                     the polarity to catch the next line transaction.
 *                     This is a race condition that might not perfectly
 *                     work on some use cases.
 *
 * Every eight GPIO lines are grouped (OR'ed) before going up to main
 * cause register.
 *
 *                    EDGE  cause    mask
 *        data-in   /--------| |-----| |----\
 *     -----| |-----                         ---- to main cause reg
 *           X      \----------------| |----/
 *        polarity    LEVEL          mask
 *
 ****************************************************************************/
static void gpio_irq_edge_ack(u32 irq)
{
	int pin = irq_to_gpio(irq);

	writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin));
}

static void gpio_irq_edge_mask(u32 irq)
{
	int pin = irq_to_gpio(irq);
	u32 u;

	u = readl(GPIO_EDGE_MASK(pin));
	u &= ~(1 << (pin & 31));
	writel(u, GPIO_EDGE_MASK(pin));
}

static void gpio_irq_edge_unmask(u32 irq)
{
	int pin = irq_to_gpio(irq);
	u32 u;

	u = readl(GPIO_EDGE_MASK(pin));
	u |= 1 << (pin & 31);
	writel(u, GPIO_EDGE_MASK(pin));
}

static void gpio_irq_level_mask(u32 irq)
{
	int pin = irq_to_gpio(irq);
	u32 u;

	u = readl(GPIO_LEVEL_MASK(pin));
	u &= ~(1 << (pin & 31));
	writel(u, GPIO_LEVEL_MASK(pin));
}

static void gpio_irq_level_unmask(u32 irq)
{
	int pin = irq_to_gpio(irq);
	u32 u;

	u = readl(GPIO_LEVEL_MASK(pin));
	u |= 1 << (pin & 31);
	writel(u, GPIO_LEVEL_MASK(pin));
}

static int gpio_irq_set_type(u32 irq, u32 type)
{
	int pin = irq_to_gpio(irq);
	struct irq_desc *desc;
	u32 u;

	u = readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31));
	if (!u) {
		printk(KERN_ERR "orion gpio_irq_set_type failed "
				"(irq %d, pin %d).\n", irq, pin);
		return -EINVAL;
	}

	desc = irq_desc + irq;

	/*
	 * Set edge/level type.
	 */
	if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
		desc->chip = &orion_gpio_irq_edge_chip;
	} else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
		desc->chip = &orion_gpio_irq_level_chip;
	} else {
		printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
		return -EINVAL;
	}

	/*
	 * Configure interrupt polarity.
	 */
	if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
		u = readl(GPIO_IN_POL(pin));
		u &= ~(1 << (pin & 31));
		writel(u, GPIO_IN_POL(pin));
	} else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
		u = readl(GPIO_IN_POL(pin));
		u |= 1 << (pin & 31);
		writel(u, GPIO_IN_POL(pin));
	} else if (type == IRQ_TYPE_EDGE_BOTH) {
		u32 v;

		v = readl(GPIO_IN_POL(pin)) ^ readl(GPIO_DATA_IN(pin));

		/*
		 * set initial polarity based on current input level
		 */
		u = readl(GPIO_IN_POL(pin));
		if (v & (1 << (pin & 31)))
			u |= 1 << (pin & 31);		/* falling */
		else
			u &= ~(1 << (pin & 31));	/* rising */
		writel(u, GPIO_IN_POL(pin));
	}

	desc->status = (desc->status & ~IRQ_TYPE_SENSE_MASK) | type;

	return 0;
}

struct irq_chip orion_gpio_irq_edge_chip = {
	.name		= "orion_gpio_irq_edge",
	.ack		= gpio_irq_edge_ack,
	.mask		= gpio_irq_edge_mask,
	.unmask		= gpio_irq_edge_unmask,
	.set_type	= gpio_irq_set_type,
};

struct irq_chip orion_gpio_irq_level_chip = {
	.name		= "orion_gpio_irq_level",
	.mask		= gpio_irq_level_mask,
	.mask_ack	= gpio_irq_level_mask,
	.unmask		= gpio_irq_level_unmask,
	.set_type	= gpio_irq_set_type,
};

void orion_gpio_irq_handler(int pinoff)
{
	u32 cause;
	int pin;

	cause = readl(GPIO_DATA_IN(pinoff)) & readl(GPIO_LEVEL_MASK(pinoff));
	cause |= readl(GPIO_EDGE_CAUSE(pinoff)) & readl(GPIO_EDGE_MASK(pinoff));

	for (pin = pinoff; pin < pinoff + 8; pin++) {
		int irq = gpio_to_irq(pin);
		struct irq_desc *desc = irq_desc + irq;

		if (!(cause & (1 << (pin & 31))))
			continue;

		if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
			/* Swap polarity (race with GPIO line) */
			u32 polarity;

			polarity = readl(GPIO_IN_POL(pin));
			polarity ^= 1 << (pin & 31);
			writel(polarity, GPIO_IN_POL(pin));
		}
		desc_handle_irq(irq, desc);
	}
}
Commit	Line	Data
9569dae7 LB	1	/*
	2	* arch/arm/plat-orion/gpio.c
	3	*
	4	* Marvell Orion SoC GPIO handling.
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
07332318	13	#include <linux/irq.h>
9569dae7 LB	14	#include <linux/module.h>
	15	#include <linux/spinlock.h>
	16	#include <linux/bitops.h>
	17	#include <linux/io.h>
	18	#include <asm/gpio.h>
	19
	20	static DEFINE_SPINLOCK(gpio_lock);
	21	static const char gpio_label[GPIO_MAX]; / non null for allocated GPIOs */
	22	static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)];
	23
	24	static inline void __set_direction(unsigned pin, int input)
	25	{
	26	u32 u;
	27
	28	u = readl(GPIO_IO_CONF(pin));
	29	if (input)
	30	u \|= 1 << (pin & 31);
	31	else
	32	u &= ~(1 << (pin & 31));
	33	writel(u, GPIO_IO_CONF(pin));
	34	}
	35
	36	static void __set_level(unsigned pin, int high)
	37	{
	38	u32 u;
	39
	40	u = readl(GPIO_OUT(pin));
	41	if (high)
	42	u \|= 1 << (pin & 31);
	43	else
	44	u &= ~(1 << (pin & 31));
	45	writel(u, GPIO_OUT(pin));
	46	}
	47
	48
	49	/*
	50	* GENERIC_GPIO primitives.
	51	*/
	52	int gpio_direction_input(unsigned pin)
	53	{
	54	unsigned long flags;
	55
	56	if (pin >= GPIO_MAX \|\| !test_bit(pin, gpio_valid)) {
	57	pr_debug("%s: invalid GPIO %d\n", __func__, pin);
	58	return -EINVAL;
	59	}
	60
	61	spin_lock_irqsave(&gpio_lock, flags);
	62
	63	/*
	64	* Some callers might not have used gpio_request(),
	65	* so flag this pin as requested now.
	66	*/
	67	if (gpio_label[pin] == NULL)
	68	gpio_label[pin] = "?";
	69
	70	/*
	71	* Configure GPIO direction.
	72	*/
	73	__set_direction(pin, 1);
	74
	75	spin_unlock_irqrestore(&gpio_lock, flags);
	76
	77	return 0;
78	}
79	EXPORT_SYMBOL(gpio_direction_input);
80
81	int gpio_direction_output(unsigned pin, int value)
82	{
83	unsigned long flags;
84	u32 u;
85
86	if (pin >= GPIO_MAX \|\| !test_bit(pin, gpio_valid)) {
87	pr_debug("%s: invalid GPIO %d\n", __func__, pin);
88	return -EINVAL;
89	}
90
91	spin_lock_irqsave(&gpio_lock, flags);
92
93	/*
94	* Some callers might not have used gpio_request(),
95	* so flag this pin as requested now.
96	*/
97	if (gpio_label[pin] == NULL)
98	gpio_label[pin] = "?";
99
100	/*
101	* Disable blinking.
102	*/
103	u = readl(GPIO_BLINK_EN(pin));
104	u &= ~(1 << (pin & 31));
105	writel(u, GPIO_BLINK_EN(pin));
106
107	/*
108	* Configure GPIO output value.
109	*/
110	__set_level(pin, value);
111
112	/*
113	* Configure GPIO direction.
114	*/
115	__set_direction(pin, 0);
116
117	spin_unlock_irqrestore(&gpio_lock, flags);
118
119	return 0;
120	}
121	EXPORT_SYMBOL(gpio_direction_output);
122
123	int gpio_get_value(unsigned pin)
124	{
125	int val;
126
127	if (readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31)))
128	val = readl(GPIO_DATA_IN(pin)) ^ readl(GPIO_IN_POL(pin));
129	else
130	val = readl(GPIO_OUT(pin));
131
132	return (val >> (pin & 31)) & 1;
133	}
134	EXPORT_SYMBOL(gpio_get_value);
135
136	void gpio_set_value(unsigned pin, int value)
137	{
138	unsigned long flags;
139	u32 u;
140
141	spin_lock_irqsave(&gpio_lock, flags);
142
143	/*
144	* Disable blinking.
145	*/
146	u = readl(GPIO_BLINK_EN(pin));
147	u &= ~(1 << (pin & 31));
148	writel(u, GPIO_BLINK_EN(pin));
149
150	/*
151	* Configure GPIO output value.
152	*/
153	__set_level(pin, value);
154
155	spin_unlock_irqrestore(&gpio_lock, flags);
156	}
157	EXPORT_SYMBOL(gpio_set_value);
158
159	int gpio_request(unsigned pin, const char *label)
160	{
161	unsigned long flags;
162	int ret;
163
164	if (pin >= GPIO_MAX \|\| !test_bit(pin, gpio_valid)) {
165	pr_debug("%s: invalid GPIO %d\n", __func__, pin);
166	return -EINVAL;
167	}
168
169	spin_lock_irqsave(&gpio_lock, flags);
170	if (gpio_label[pin] == NULL) {
171	gpio_label[pin] = label ? label : "?";
172	ret = 0;
173	} else {
174	pr_debug("%s: GPIO %d already used as %s\n",
175	__func__, pin, gpio_label[pin]);
176	ret = -EBUSY;
177	}
178	spin_unlock_irqrestore(&gpio_lock, flags);
179
180	return ret;
181	}
182	EXPORT_SYMBOL(gpio_request);
183
184	void gpio_free(unsigned pin)
185	{
186	if (pin >= GPIO_MAX \|\| !test_bit(pin, gpio_valid)) {
187	pr_debug("%s: invalid GPIO %d\n", __func__, pin);
188	return;
189	}
190
191	if (gpio_label[pin] == NULL)
192	pr_warning("%s: GPIO %d already freed\n", __func__, pin);
193	else
194	gpio_label[pin] = NULL;
195	}
196	EXPORT_SYMBOL(gpio_free);
197
198
199	/*
200	* Orion-specific GPIO API extensions.
201	*/
202	void __init orion_gpio_set_unused(unsigned pin)
203	{
204	/*
205	* Configure as output, drive low.
206	*/
207	__set_level(pin, 0);
208	__set_direction(pin, 0);
209	}
210
211	void __init orion_gpio_set_valid(unsigned pin, int valid)
212	{
213	if (valid)
214	__set_bit(pin, gpio_valid);
215	else
216	__clear_bit(pin, gpio_valid);
217	}
218
219	void orion_gpio_set_blink(unsigned pin, int blink)
220	{
221	unsigned long flags;
222	u32 u;
223
224	spin_lock_irqsave(&gpio_lock, flags);
225
226	/*
227	* Set output value to zero.
228	*/
229	__set_level(pin, 0);
230
231	u = readl(GPIO_BLINK_EN(pin));
232	if (blink)
233	u \|= 1 << (pin & 31);
234	else
235	u &= ~(1 << (pin & 31));
236	writel(u, GPIO_BLINK_EN(pin));
237
238	spin_unlock_irqrestore(&gpio_lock, flags);
239	}
240	EXPORT_SYMBOL(orion_gpio_set_blink);
07332318 LB	241
	242
	243	/*****************************************************************************
	244	* Orion GPIO IRQ
	245	*
	246	* GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
	247	* value of the line or the opposite value.
	248	*
	249	* Level IRQ handlers: DATA_IN is used directly as cause register.
	250	* Interrupt are masked by LEVEL_MASK registers.
	251	* Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
	252	* Interrupt are masked by EDGE_MASK registers.
	253	* Both-edge handlers: Similar to regular Edge handlers, but also swaps
	254	* the polarity to catch the next line transaction.
	255	* This is a race condition that might not perfectly
	256	* work on some use cases.
	257	*
	258	* Every eight GPIO lines are grouped (OR'ed) before going up to main
	259	* cause register.
	260	*
	261	* EDGE cause mask
	262	* data-in /--------\| \|-----\| \|----\
	263	* -----\| \|----- ---- to main cause reg
	264	* X \----------------\| \|----/
	265	* polarity LEVEL mask
	266	*
	267	****************************************************************************/
	268	static void gpio_irq_edge_ack(u32 irq)
	269	{
	270	int pin = irq_to_gpio(irq);
	271
	272	writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin));
	273	}
	274
	275	static void gpio_irq_edge_mask(u32 irq)
	276	{
	277	int pin = irq_to_gpio(irq);
	278	u32 u;
	279
	280	u = readl(GPIO_EDGE_MASK(pin));
	281	u &= ~(1 << (pin & 31));
	282	writel(u, GPIO_EDGE_MASK(pin));
	283	}
	284
	285	static void gpio_irq_edge_unmask(u32 irq)
	286	{
	287	int pin = irq_to_gpio(irq);
	288	u32 u;
	289
	290	u = readl(GPIO_EDGE_MASK(pin));
	291	u \|= 1 << (pin & 31);
	292	writel(u, GPIO_EDGE_MASK(pin));
	293	}
	294
	295	static void gpio_irq_level_mask(u32 irq)
	296	{
	297	int pin = irq_to_gpio(irq);
	298	u32 u;
	299
	300	u = readl(GPIO_LEVEL_MASK(pin));
	301	u &= ~(1 << (pin & 31));
	302	writel(u, GPIO_LEVEL_MASK(pin));
	303	}
	304
305	static void gpio_irq_level_unmask(u32 irq)
306	{
307	int pin = irq_to_gpio(irq);
308	u32 u;
309
310	u = readl(GPIO_LEVEL_MASK(pin));
311	u \|= 1 << (pin & 31);
312	writel(u, GPIO_LEVEL_MASK(pin));
313	}
314
315	static int gpio_irq_set_type(u32 irq, u32 type)
316	{
317	int pin = irq_to_gpio(irq);
318	struct irq_desc *desc;
319	u32 u;
320
321	u = readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31));
322	if (!u) {
323	printk(KERN_ERR "orion gpio_irq_set_type failed "
324	"(irq %d, pin %d).\n", irq, pin);
325	return -EINVAL;
326	}
327
328	desc = irq_desc + irq;
329
330	/*
331	* Set edge/level type.
332	*/
333	if (type & (IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING)) {
334	desc->chip = &orion_gpio_irq_edge_chip;
335	} else if (type & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW)) {
336	desc->chip = &orion_gpio_irq_level_chip;
337	} else {
338	printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
339	return -EINVAL;
340	}
341
342	/*
343	* Configure interrupt polarity.
344	*/
345	if (type == IRQ_TYPE_EDGE_RISING \|\| type == IRQ_TYPE_LEVEL_HIGH) {
346	u = readl(GPIO_IN_POL(pin));
347	u &= ~(1 << (pin & 31));
348	writel(u, GPIO_IN_POL(pin));
349	} else if (type == IRQ_TYPE_EDGE_FALLING \|\| type == IRQ_TYPE_LEVEL_LOW) {
350	u = readl(GPIO_IN_POL(pin));
351	u \|= 1 << (pin & 31);
352	writel(u, GPIO_IN_POL(pin));
353	} else if (type == IRQ_TYPE_EDGE_BOTH) {
354	u32 v;
355
356	v = readl(GPIO_IN_POL(pin)) ^ readl(GPIO_DATA_IN(pin));
357
358	/*
359	* set initial polarity based on current input level
360	*/
361	u = readl(GPIO_IN_POL(pin));
362	if (v & (1 << (pin & 31)))
363	u \|= 1 << (pin & 31); /* falling */
364	else
365	u &= ~(1 << (pin & 31)); /* rising */
366	writel(u, GPIO_IN_POL(pin));
367	}
368
369	desc->status = (desc->status & ~IRQ_TYPE_SENSE_MASK) \| type;
370
371	return 0;
372	}
373
374	struct irq_chip orion_gpio_irq_edge_chip = {
375	.name = "orion_gpio_irq_edge",
376	.ack = gpio_irq_edge_ack,
377	.mask = gpio_irq_edge_mask,
378	.unmask = gpio_irq_edge_unmask,
379	.set_type = gpio_irq_set_type,
380	};
381
382	struct irq_chip orion_gpio_irq_level_chip = {
383	.name = "orion_gpio_irq_level",
384	.mask = gpio_irq_level_mask,
385	.mask_ack = gpio_irq_level_mask,
386	.unmask = gpio_irq_level_unmask,
387	.set_type = gpio_irq_set_type,
388	};
389
390	void orion_gpio_irq_handler(int pinoff)
391	{
392	u32 cause;
393	int pin;
394
395	cause = readl(GPIO_DATA_IN(pinoff)) & readl(GPIO_LEVEL_MASK(pinoff));
396	cause \|= readl(GPIO_EDGE_CAUSE(pinoff)) & readl(GPIO_EDGE_MASK(pinoff));
397
398	for (pin = pinoff; pin < pinoff + 8; pin++) {
399	int irq = gpio_to_irq(pin);
400	struct irq_desc *desc = irq_desc + irq;
401
402	if (!(cause & (1 << (pin & 31))))
403	continue;
404
405	if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
406	/* Swap polarity (race with GPIO line) */
407	u32 polarity;
408
409	polarity = readl(GPIO_IN_POL(pin));
410	polarity ^= 1 << (pin & 31);
411	writel(polarity, GPIO_IN_POL(pin));
412	}
413	desc_handle_irq(irq, desc);
414	}
415	}