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abc0197d LB |
1 | /* |
2 | * arch/arm/plat-orion/pcie.c | |
3 | * | |
4 | * Marvell Orion SoC PCIe handling. | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public | |
7 | * License version 2. This program is licensed "as is" without any | |
8 | * warranty of any kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/mbus.h> | |
14 | #include <asm/mach/pci.h> | |
6f088f1d | 15 | #include <plat/pcie.h> |
63a9332b | 16 | #include <plat/addr-map.h> |
21f0ba90 | 17 | #include <linux/delay.h> |
abc0197d LB |
18 | |
19 | /* | |
20 | * PCIe unit register offsets. | |
21 | */ | |
22 | #define PCIE_DEV_ID_OFF 0x0000 | |
23 | #define PCIE_CMD_OFF 0x0004 | |
24 | #define PCIE_DEV_REV_OFF 0x0008 | |
25 | #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) | |
26 | #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) | |
27 | #define PCIE_HEADER_LOG_4_OFF 0x0128 | |
28 | #define PCIE_BAR_CTRL_OFF(n) (0x1804 + ((n - 1) * 4)) | |
29 | #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) | |
30 | #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4)) | |
31 | #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4)) | |
32 | #define PCIE_WIN5_CTRL_OFF 0x1880 | |
33 | #define PCIE_WIN5_BASE_OFF 0x1884 | |
34 | #define PCIE_WIN5_REMAP_OFF 0x188c | |
35 | #define PCIE_CONF_ADDR_OFF 0x18f8 | |
36 | #define PCIE_CONF_ADDR_EN 0x80000000 | |
37 | #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) | |
38 | #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) | |
39 | #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) | |
82676d76 | 40 | #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) |
abc0197d LB |
41 | #define PCIE_CONF_DATA_OFF 0x18fc |
42 | #define PCIE_MASK_OFF 0x1910 | |
43 | #define PCIE_CTRL_OFF 0x1a00 | |
a9311cfe | 44 | #define PCIE_CTRL_X1_MODE 0x0001 |
abc0197d LB |
45 | #define PCIE_STAT_OFF 0x1a04 |
46 | #define PCIE_STAT_DEV_OFFS 20 | |
47 | #define PCIE_STAT_DEV_MASK 0x1f | |
48 | #define PCIE_STAT_BUS_OFFS 8 | |
49 | #define PCIE_STAT_BUS_MASK 0xff | |
50 | #define PCIE_STAT_LINK_DOWN 1 | |
21f0ba90 OR |
51 | #define PCIE_DEBUG_CTRL 0x1a60 |
52 | #define PCIE_DEBUG_SOFT_RESET (1<<20) | |
abc0197d LB |
53 | |
54 | ||
98d9986c | 55 | u32 orion_pcie_dev_id(void __iomem *base) |
abc0197d LB |
56 | { |
57 | return readl(base + PCIE_DEV_ID_OFF) >> 16; | |
58 | } | |
59 | ||
98d9986c | 60 | u32 orion_pcie_rev(void __iomem *base) |
abc0197d LB |
61 | { |
62 | return readl(base + PCIE_DEV_REV_OFF) & 0xff; | |
63 | } | |
64 | ||
b488a5ed | 65 | int orion_pcie_link_up(void __iomem *base) |
abc0197d LB |
66 | { |
67 | return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); | |
68 | } | |
69 | ||
a9311cfe LB |
70 | int __init orion_pcie_x4_mode(void __iomem *base) |
71 | { | |
72 | return !(readl(base + PCIE_CTRL_OFF) & PCIE_CTRL_X1_MODE); | |
73 | } | |
74 | ||
b488a5ed | 75 | int orion_pcie_get_local_bus_nr(void __iomem *base) |
abc0197d LB |
76 | { |
77 | u32 stat = readl(base + PCIE_STAT_OFF); | |
78 | ||
79 | return (stat >> PCIE_STAT_BUS_OFFS) & PCIE_STAT_BUS_MASK; | |
80 | } | |
81 | ||
82 | void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr) | |
83 | { | |
84 | u32 stat; | |
85 | ||
86 | stat = readl(base + PCIE_STAT_OFF); | |
87 | stat &= ~(PCIE_STAT_BUS_MASK << PCIE_STAT_BUS_OFFS); | |
88 | stat |= nr << PCIE_STAT_BUS_OFFS; | |
89 | writel(stat, base + PCIE_STAT_OFF); | |
90 | } | |
91 | ||
21f0ba90 OR |
92 | void __init orion_pcie_reset(void __iomem *base) |
93 | { | |
94 | u32 reg; | |
95 | int i; | |
96 | ||
97 | /* | |
98 | * MV-S104860-U0, Rev. C: | |
99 | * PCI Express Unit Soft Reset | |
100 | * When set, generates an internal reset in the PCI Express unit. | |
101 | * This bit should be cleared after the link is re-established. | |
102 | */ | |
103 | reg = readl(base + PCIE_DEBUG_CTRL); | |
104 | reg |= PCIE_DEBUG_SOFT_RESET; | |
105 | writel(reg, base + PCIE_DEBUG_CTRL); | |
106 | ||
107 | for (i = 0; i < 20; i++) { | |
108 | mdelay(10); | |
109 | ||
110 | if (orion_pcie_link_up(base)) | |
111 | break; | |
112 | } | |
113 | ||
114 | reg &= ~(PCIE_DEBUG_SOFT_RESET); | |
115 | writel(reg, base + PCIE_DEBUG_CTRL); | |
116 | } | |
117 | ||
abc0197d LB |
118 | /* |
119 | * Setup PCIE BARs and Address Decode Wins: | |
120 | * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks | |
121 | * WIN[0-3] -> DRAM bank[0-3] | |
122 | */ | |
123 | static void __init orion_pcie_setup_wins(void __iomem *base, | |
124 | struct mbus_dram_target_info *dram) | |
125 | { | |
126 | u32 size; | |
127 | int i; | |
128 | ||
129 | /* | |
130 | * First, disable and clear BARs and windows. | |
131 | */ | |
132 | for (i = 1; i <= 2; i++) { | |
133 | writel(0, base + PCIE_BAR_CTRL_OFF(i)); | |
134 | writel(0, base + PCIE_BAR_LO_OFF(i)); | |
135 | writel(0, base + PCIE_BAR_HI_OFF(i)); | |
136 | } | |
137 | ||
138 | for (i = 0; i < 5; i++) { | |
139 | writel(0, base + PCIE_WIN04_CTRL_OFF(i)); | |
140 | writel(0, base + PCIE_WIN04_BASE_OFF(i)); | |
141 | writel(0, base + PCIE_WIN04_REMAP_OFF(i)); | |
142 | } | |
143 | ||
144 | writel(0, base + PCIE_WIN5_CTRL_OFF); | |
145 | writel(0, base + PCIE_WIN5_BASE_OFF); | |
146 | writel(0, base + PCIE_WIN5_REMAP_OFF); | |
147 | ||
148 | /* | |
149 | * Setup windows for DDR banks. Count total DDR size on the fly. | |
150 | */ | |
151 | size = 0; | |
152 | for (i = 0; i < dram->num_cs; i++) { | |
153 | struct mbus_dram_window *cs = dram->cs + i; | |
154 | ||
155 | writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); | |
156 | writel(0, base + PCIE_WIN04_REMAP_OFF(i)); | |
157 | writel(((cs->size - 1) & 0xffff0000) | | |
158 | (cs->mbus_attr << 8) | | |
159 | (dram->mbus_dram_target_id << 4) | 1, | |
160 | base + PCIE_WIN04_CTRL_OFF(i)); | |
161 | ||
162 | size += cs->size; | |
163 | } | |
164 | ||
7788cd55 LB |
165 | /* |
166 | * Round up 'size' to the nearest power of two. | |
167 | */ | |
168 | if ((size & (size - 1)) != 0) | |
169 | size = 1 << fls(size); | |
170 | ||
abc0197d LB |
171 | /* |
172 | * Setup BAR[1] to all DRAM banks. | |
173 | */ | |
174 | writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1)); | |
175 | writel(0, base + PCIE_BAR_HI_OFF(1)); | |
176 | writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1)); | |
177 | } | |
178 | ||
63a9332b | 179 | void __init orion_pcie_setup(void __iomem *base) |
abc0197d LB |
180 | { |
181 | u16 cmd; | |
182 | u32 mask; | |
183 | ||
184 | /* | |
185 | * Point PCIe unit MBUS decode windows to DRAM space. | |
186 | */ | |
63a9332b | 187 | orion_pcie_setup_wins(base, &orion_mbus_dram_info); |
abc0197d LB |
188 | |
189 | /* | |
190 | * Master + slave enable. | |
191 | */ | |
192 | cmd = readw(base + PCIE_CMD_OFF); | |
193 | cmd |= PCI_COMMAND_IO; | |
194 | cmd |= PCI_COMMAND_MEMORY; | |
195 | cmd |= PCI_COMMAND_MASTER; | |
196 | writew(cmd, base + PCIE_CMD_OFF); | |
197 | ||
198 | /* | |
199 | * Enable interrupt lines A-D. | |
200 | */ | |
201 | mask = readl(base + PCIE_MASK_OFF); | |
202 | mask |= 0x0f000000; | |
203 | writel(mask, base + PCIE_MASK_OFF); | |
204 | } | |
205 | ||
206 | int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, | |
207 | u32 devfn, int where, int size, u32 *val) | |
208 | { | |
209 | writel(PCIE_CONF_BUS(bus->number) | | |
210 | PCIE_CONF_DEV(PCI_SLOT(devfn)) | | |
211 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | | |
212 | PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN, | |
213 | base + PCIE_CONF_ADDR_OFF); | |
214 | ||
215 | *val = readl(base + PCIE_CONF_DATA_OFF); | |
216 | ||
217 | if (size == 1) | |
218 | *val = (*val >> (8 * (where & 3))) & 0xff; | |
219 | else if (size == 2) | |
220 | *val = (*val >> (8 * (where & 3))) & 0xffff; | |
221 | ||
222 | return PCIBIOS_SUCCESSFUL; | |
223 | } | |
224 | ||
225 | int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus, | |
226 | u32 devfn, int where, int size, u32 *val) | |
227 | { | |
228 | writel(PCIE_CONF_BUS(bus->number) | | |
229 | PCIE_CONF_DEV(PCI_SLOT(devfn)) | | |
230 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | | |
231 | PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN, | |
232 | base + PCIE_CONF_ADDR_OFF); | |
233 | ||
234 | *val = readl(base + PCIE_CONF_DATA_OFF); | |
235 | ||
236 | if (bus->number != orion_pcie_get_local_bus_nr(base) || | |
237 | PCI_FUNC(devfn) != 0) | |
238 | *val = readl(base + PCIE_HEADER_LOG_4_OFF); | |
239 | ||
240 | if (size == 1) | |
241 | *val = (*val >> (8 * (where & 3))) & 0xff; | |
242 | else if (size == 2) | |
243 | *val = (*val >> (8 * (where & 3))) & 0xffff; | |
244 | ||
245 | return PCIBIOS_SUCCESSFUL; | |
246 | } | |
247 | ||
248 | int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus, | |
249 | u32 devfn, int where, int size, u32 *val) | |
250 | { | |
251 | *val = readl(wa_base + (PCIE_CONF_BUS(bus->number) | | |
252 | PCIE_CONF_DEV(PCI_SLOT(devfn)) | | |
253 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | | |
254 | PCIE_CONF_REG(where))); | |
255 | ||
256 | if (size == 1) | |
257 | *val = (*val >> (8 * (where & 3))) & 0xff; | |
258 | else if (size == 2) | |
259 | *val = (*val >> (8 * (where & 3))) & 0xffff; | |
260 | ||
261 | return PCIBIOS_SUCCESSFUL; | |
262 | } | |
263 | ||
264 | int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus, | |
265 | u32 devfn, int where, int size, u32 val) | |
266 | { | |
267 | int ret = PCIBIOS_SUCCESSFUL; | |
268 | ||
269 | writel(PCIE_CONF_BUS(bus->number) | | |
270 | PCIE_CONF_DEV(PCI_SLOT(devfn)) | | |
271 | PCIE_CONF_FUNC(PCI_FUNC(devfn)) | | |
272 | PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN, | |
273 | base + PCIE_CONF_ADDR_OFF); | |
274 | ||
275 | if (size == 4) { | |
276 | writel(val, base + PCIE_CONF_DATA_OFF); | |
277 | } else if (size == 2) { | |
278 | writew(val, base + PCIE_CONF_DATA_OFF + (where & 3)); | |
279 | } else if (size == 1) { | |
280 | writeb(val, base + PCIE_CONF_DATA_OFF + (where & 3)); | |
281 | } else { | |
282 | ret = PCIBIOS_BAD_REGISTER_NUMBER; | |
283 | } | |
284 | ||
285 | return ret; | |
286 | } |