[deliverable/linux.git] / arch / arm / plat-orion / time.c

/*
 * arch/arm/plat-orion/time.c
 *
 * Marvell Orion SoC timer handling.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * Timer 0 is used as free-running clocksource, while timer 1 is
 * used as clock_event_device.
 */

#include <linux/kernel.h>
#include <linux/timer.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/sched_clock.h>
#include <plat/time.h>
#include <asm/delay.h>

/*
 * MBus bridge block registers.
 */
#define BRIDGE_CAUSE_OFF	0x0110
#define BRIDGE_MASK_OFF		0x0114
#define  BRIDGE_INT_TIMER0	 0x0002
#define  BRIDGE_INT_TIMER1	 0x0004


/*
 * Timer block registers.
 */
#define TIMER_CTRL_OFF		0x0000
#define  TIMER0_EN		 0x0001
#define  TIMER0_RELOAD_EN	 0x0002
#define  TIMER1_EN		 0x0004
#define  TIMER1_RELOAD_EN	 0x0008
#define TIMER0_RELOAD_OFF	0x0010
#define TIMER0_VAL_OFF		0x0014
#define TIMER1_RELOAD_OFF	0x0018
#define TIMER1_VAL_OFF		0x001c


/*
 * SoC-specific data.
 */
static void __iomem *bridge_base;
static u32 bridge_timer1_clr_mask;
static void __iomem *timer_base;


/*
 * Number of timer ticks per jiffy.
 */
static u32 ticks_per_jiffy;


/*
 * Orion's sched_clock implementation. It has a resolution of
 * at least 7.5ns (133MHz TCLK).
 */

static u64 notrace orion_read_sched_clock(void)
{
	return ~readl(timer_base + TIMER0_VAL_OFF);
}

/*
 * Clockevent handling.
 */
static int
orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
{
	unsigned long flags;
	u32 u;

	if (delta == 0)
		return -ETIME;

	local_irq_save(flags);

	/*
	 * Clear and enable clockevent timer interrupt.
	 */
	writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);

	u = readl(bridge_base + BRIDGE_MASK_OFF);
	u |= BRIDGE_INT_TIMER1;
	writel(u, bridge_base + BRIDGE_MASK_OFF);

	/*
	 * Setup new clockevent timer value.
	 */
	writel(delta, timer_base + TIMER1_VAL_OFF);

	/*
	 * Enable the timer.
	 */
	u = readl(timer_base + TIMER_CTRL_OFF);
	u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
	writel(u, timer_base + TIMER_CTRL_OFF);

	local_irq_restore(flags);

	return 0;
}

static int orion_clkevt_shutdown(struct clock_event_device *evt)
{
	unsigned long flags;
	u32 u;

	local_irq_save(flags);

	/* Disable timer */
	u = readl(timer_base + TIMER_CTRL_OFF);
	writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);

	/* Disable timer interrupt */
	u = readl(bridge_base + BRIDGE_MASK_OFF);
	writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);

	/* ACK pending timer interrupt */
	writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);

	local_irq_restore(flags);

	return 0;
}

static int orion_clkevt_set_periodic(struct clock_event_device *evt)
{
	unsigned long flags;
	u32 u;

	local_irq_save(flags);

	/* Setup timer to fire at 1/HZ intervals */
	writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
	writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);

	/* Enable timer interrupt */
	u = readl(bridge_base + BRIDGE_MASK_OFF);
	writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);

	/* Enable timer */
	u = readl(timer_base + TIMER_CTRL_OFF);
	writel(u | TIMER1_EN | TIMER1_RELOAD_EN, timer_base + TIMER_CTRL_OFF);

	local_irq_restore(flags);

	return 0;
}

static struct clock_event_device orion_clkevt = {
	.name			= "orion_tick",
	.features		= CLOCK_EVT_FEAT_ONESHOT |
				  CLOCK_EVT_FEAT_PERIODIC,
	.rating			= 300,
	.set_next_event		= orion_clkevt_next_event,
	.set_state_shutdown	= orion_clkevt_shutdown,
	.set_state_periodic	= orion_clkevt_set_periodic,
	.set_state_oneshot	= orion_clkevt_shutdown,
	.tick_resume		= orion_clkevt_shutdown,
};

static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
{
	/*
	 * ACK timer interrupt and call event handler.
	 */
	writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
	orion_clkevt.event_handler(&orion_clkevt);

	return IRQ_HANDLED;
}

static struct irqaction orion_timer_irq = {
	.name		= "orion_tick",
	.flags		= IRQF_TIMER,
	.handler	= orion_timer_interrupt
};

void __init
orion_time_set_base(void __iomem *_timer_base)
{
	timer_base = _timer_base;
}

static unsigned long orion_delay_timer_read(void)
{
	return ~readl(timer_base + TIMER0_VAL_OFF);
}

static struct delay_timer orion_delay_timer = {
	.read_current_timer = orion_delay_timer_read,
};

void __init
orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
		unsigned int irq, unsigned int tclk)
{
	u32 u;

	/*
	 * Set SoC-specific data.
	 */
	bridge_base = _bridge_base;
	bridge_timer1_clr_mask = _bridge_timer1_clr_mask;

	ticks_per_jiffy = (tclk + HZ/2) / HZ;

	orion_delay_timer.freq = tclk;
	register_current_timer_delay(&orion_delay_timer);

	/*
	 * Set scale and timer for sched_clock.
	 */
	sched_clock_register(orion_read_sched_clock, 32, tclk);

	/*
	 * Setup free-running clocksource timer (interrupts
	 * disabled).
	 */
	writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
	writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
	u = readl(bridge_base + BRIDGE_MASK_OFF);
	writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
	u = readl(timer_base + TIMER_CTRL_OFF);
	writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
	clocksource_mmio_init(timer_base + TIMER0_VAL_OFF, "orion_clocksource",
		tclk, 300, 32, clocksource_mmio_readl_down);

	/*
	 * Setup clockevent timer (interrupt-driven).
	 */
	setup_irq(irq, &orion_timer_irq);
	orion_clkevt.cpumask = cpumask_of(0);
	clockevents_config_and_register(&orion_clkevt, tclk, 1, 0xfffffffe);
}
Commit	Line	Data
2bac1de2 LB	1	/*
	2	* arch/arm/plat-orion/time.c
	3	*
	4	* Marvell Orion SoC timer handling.
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*
	10	* Timer 0 is used as free-running clocksource, while timer 1 is
	11	* used as clock_event_device.
	12	*/
	13
	14	#include <linux/kernel.h>
a399e3fa	15	#include <linux/timer.h>
2bac1de2 LB	16	#include <linux/clockchips.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/irq.h>
38ff87f7	19	#include <linux/sched_clock.h>
48fce88c	20	#include <plat/time.h>
f19768ce	21	#include <asm/delay.h>
2bac1de2 LB	22
2bac1de2 LB	23	/*
4ee1f6b5	24	* MBus bridge block registers.
2bac1de2	25	*/
4ee1f6b5 LB	26	#define BRIDGE_CAUSE_OFF 0x0110
	27	#define BRIDGE_MASK_OFF 0x0114
	28	#define BRIDGE_INT_TIMER0 0x0002
	29	#define BRIDGE_INT_TIMER1 0x0004
2bac1de2 LB	30
	31
	32	/*
	33	* Timer block registers.
	34	*/
4ee1f6b5 LB	35	#define TIMER_CTRL_OFF 0x0000
	36	#define TIMER0_EN 0x0001
	37	#define TIMER0_RELOAD_EN 0x0002
	38	#define TIMER1_EN 0x0004
	39	#define TIMER1_RELOAD_EN 0x0008
	40	#define TIMER0_RELOAD_OFF 0x0010
	41	#define TIMER0_VAL_OFF 0x0014
	42	#define TIMER1_RELOAD_OFF 0x0018
	43	#define TIMER1_VAL_OFF 0x001c
	44
	45
	46	/*
	47	* SoC-specific data.
	48	*/
	49	static void __iomem *bridge_base;
	50	static u32 bridge_timer1_clr_mask;
	51	static void __iomem *timer_base;
	52
	53
	54	/*
	55	* Number of timer ticks per jiffy.
	56	*/
	57	static u32 ticks_per_jiffy;
2bac1de2 LB	58
2bac1de2 LB	59
8a3269fc SA	60	/*
8a3269fc SA	61	* Orion's sched_clock implementation. It has a resolution of
f06a1624	62	* at least 7.5ns (133MHz TCLK).
8a3269fc	63	*/
8a3269fc	64
b44653ba	65	static u64 notrace orion_read_sched_clock(void)
a399e3fa	66	{
2f0778af	67	return ~readl(timer_base + TIMER0_VAL_OFF);
8a3269fc SA	68	}
8a3269fc SA	69
2bac1de2 LB	70	/*
	71	* Clockevent handling.
	72	*/
	73	static int
	74	orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
	75	{
	76	unsigned long flags;
	77	u32 u;
	78
	79	if (delta == 0)
	80	return -ETIME;
	81
	82	local_irq_save(flags);
	83
	84	/*
	85	* Clear and enable clockevent timer interrupt.
	86	*/
4ee1f6b5	87	writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
2bac1de2	88
4ee1f6b5	89	u = readl(bridge_base + BRIDGE_MASK_OFF);
2bac1de2	90	u \|= BRIDGE_INT_TIMER1;
4ee1f6b5	91	writel(u, bridge_base + BRIDGE_MASK_OFF);
2bac1de2 LB	92
	93	/*
	94	* Setup new clockevent timer value.
	95	*/
4ee1f6b5	96	writel(delta, timer_base + TIMER1_VAL_OFF);
2bac1de2 LB	97
	98	/*
	99	* Enable the timer.
	100	*/
4ee1f6b5	101	u = readl(timer_base + TIMER_CTRL_OFF);
2bac1de2	102	u = (u & ~TIMER1_RELOAD_EN) \| TIMER1_EN;
4ee1f6b5	103	writel(u, timer_base + TIMER_CTRL_OFF);
2bac1de2 LB	104
	105	local_irq_restore(flags);
	106
	107	return 0;
	108	}
	109
10dca88a	110	static int orion_clkevt_shutdown(struct clock_event_device *evt)
2bac1de2 LB	111	{
	112	unsigned long flags;
	113	u32 u;
	114
	115	local_irq_save(flags);
10dca88a VK	116
	117	/* Disable timer */
	118	u = readl(timer_base + TIMER_CTRL_OFF);
	119	writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
	120
	121	/* Disable timer interrupt */
	122	u = readl(bridge_base + BRIDGE_MASK_OFF);
	123	writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
	124
	125	/* ACK pending timer interrupt */
	126	writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
	127
	128	local_irq_restore(flags);
	129
	130	return 0;
	131	}
	132
	133	static int orion_clkevt_set_periodic(struct clock_event_device *evt)
	134	{
	135	unsigned long flags;
	136	u32 u;
	137
	138	local_irq_save(flags);
	139
	140	/* Setup timer to fire at 1/HZ intervals */
	141	writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
	142	writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
	143
	144	/* Enable timer interrupt */
	145	u = readl(bridge_base + BRIDGE_MASK_OFF);
	146	writel(u \| BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
	147
	148	/* Enable timer */
	149	u = readl(timer_base + TIMER_CTRL_OFF);
	150	writel(u \| TIMER1_EN \| TIMER1_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
	151
2bac1de2	152	local_irq_restore(flags);
10dca88a VK	153
10dca88a VK	154	return 0;
2bac1de2 LB	155	}
	156
	157	static struct clock_event_device orion_clkevt = {
10dca88a VK	158	.name = "orion_tick",
	159	.features = CLOCK_EVT_FEAT_ONESHOT \|
	160	CLOCK_EVT_FEAT_PERIODIC,
	161	.rating = 300,
	162	.set_next_event = orion_clkevt_next_event,
	163	.set_state_shutdown = orion_clkevt_shutdown,
	164	.set_state_periodic = orion_clkevt_set_periodic,
	165	.set_state_oneshot = orion_clkevt_shutdown,
	166	.tick_resume = orion_clkevt_shutdown,
2bac1de2 LB	167	};
	168
	169	static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
	170	{
	171	/*
	172	* ACK timer interrupt and call event handler.
	173	*/
4ee1f6b5	174	writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
2bac1de2 LB	175	orion_clkevt.event_handler(&orion_clkevt);
	176
	177	return IRQ_HANDLED;
	178	}
	179
	180	static struct irqaction orion_timer_irq = {
	181	.name = "orion_tick",
eb4d552b	182	.flags = IRQF_TIMER,
2bac1de2 LB	183	.handler = orion_timer_interrupt
	184	};
	185
4ee1f6b5	186	void __init
e96a0309	187	orion_time_set_base(void __iomem *_timer_base)
4ee1f6b5	188	{
e96a0309	189	timer_base = _timer_base;
4ee1f6b5 LB	190	}
4ee1f6b5 LB	191
f19768ce RK	192	static unsigned long orion_delay_timer_read(void)
	193	{
	194	return ~readl(timer_base + TIMER0_VAL_OFF);
	195	}
	196
	197	static struct delay_timer orion_delay_timer = {
	198	.read_current_timer = orion_delay_timer_read,
	199	};
	200
4ee1f6b5	201	void __init
e96a0309	202	orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
4ee1f6b5	203	unsigned int irq, unsigned int tclk)
2bac1de2 LB	204	{
	205	u32 u;
	206
4ee1f6b5 LB	207	/*
	208	* Set SoC-specific data.
	209	*/
e96a0309	210	bridge_base = _bridge_base;
4ee1f6b5 LB	211	bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
4ee1f6b5 LB	212
2bac1de2 LB	213	ticks_per_jiffy = (tclk + HZ/2) / HZ;
2bac1de2 LB	214
f19768ce RK	215	orion_delay_timer.freq = tclk;
	216	register_current_timer_delay(&orion_delay_timer);
	217
8a3269fc	218	/*
4ee1f6b5	219	* Set scale and timer for sched_clock.
8a3269fc	220	*/
b44653ba	221	sched_clock_register(orion_read_sched_clock, 32, tclk);
2bac1de2 LB	222
	223	/*
	224	* Setup free-running clocksource timer (interrupts
4ee1f6b5	225	* disabled).
2bac1de2	226	*/
4ee1f6b5 LB	227	writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
	228	writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
	229	u = readl(bridge_base + BRIDGE_MASK_OFF);
	230	writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
	231	u = readl(timer_base + TIMER_CTRL_OFF);
	232	writel(u \| TIMER0_EN \| TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
bfe45e0b RK	233	clocksource_mmio_init(timer_base + TIMER0_VAL_OFF, "orion_clocksource",
bfe45e0b RK	234	tclk, 300, 32, clocksource_mmio_readl_down);
2bac1de2	235
2bac1de2	236	/*
4ee1f6b5	237	* Setup clockevent timer (interrupt-driven).
2bac1de2 LB	238	*/
2bac1de2 LB	239	setup_irq(irq, &orion_timer_irq);
320ab2b0	240	orion_clkevt.cpumask = cpumask_of(0);
838a2ae8	241	clockevents_config_and_register(&orion_clkevt, tclk, 1, 0xfffffffe);
2bac1de2	242	}