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2bac1de2 LB |
1 | /* |
2 | * arch/arm/plat-orion/time.c | |
3 | * | |
4 | * Marvell Orion SoC timer handling. | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public | |
7 | * License version 2. This program is licensed "as is" without any | |
8 | * warranty of any kind, whether express or implied. | |
9 | * | |
10 | * Timer 0 is used as free-running clocksource, while timer 1 is | |
11 | * used as clock_event_device. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
a399e3fa | 15 | #include <linux/sched.h> |
a399e3fa | 16 | #include <linux/timer.h> |
2bac1de2 LB |
17 | #include <linux/clockchips.h> |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/irq.h> | |
f06a1624 | 20 | #include <asm/sched_clock.h> |
2bac1de2 LB |
21 | |
22 | /* | |
4ee1f6b5 | 23 | * MBus bridge block registers. |
2bac1de2 | 24 | */ |
4ee1f6b5 LB |
25 | #define BRIDGE_CAUSE_OFF 0x0110 |
26 | #define BRIDGE_MASK_OFF 0x0114 | |
27 | #define BRIDGE_INT_TIMER0 0x0002 | |
28 | #define BRIDGE_INT_TIMER1 0x0004 | |
2bac1de2 LB |
29 | |
30 | ||
31 | /* | |
32 | * Timer block registers. | |
33 | */ | |
4ee1f6b5 LB |
34 | #define TIMER_CTRL_OFF 0x0000 |
35 | #define TIMER0_EN 0x0001 | |
36 | #define TIMER0_RELOAD_EN 0x0002 | |
37 | #define TIMER1_EN 0x0004 | |
38 | #define TIMER1_RELOAD_EN 0x0008 | |
39 | #define TIMER0_RELOAD_OFF 0x0010 | |
40 | #define TIMER0_VAL_OFF 0x0014 | |
41 | #define TIMER1_RELOAD_OFF 0x0018 | |
42 | #define TIMER1_VAL_OFF 0x001c | |
43 | ||
44 | ||
45 | /* | |
46 | * SoC-specific data. | |
47 | */ | |
48 | static void __iomem *bridge_base; | |
49 | static u32 bridge_timer1_clr_mask; | |
50 | static void __iomem *timer_base; | |
51 | ||
52 | ||
53 | /* | |
54 | * Number of timer ticks per jiffy. | |
55 | */ | |
56 | static u32 ticks_per_jiffy; | |
2bac1de2 LB |
57 | |
58 | ||
8a3269fc SA |
59 | /* |
60 | * Orion's sched_clock implementation. It has a resolution of | |
f06a1624 | 61 | * at least 7.5ns (133MHz TCLK). |
8a3269fc | 62 | */ |
f06a1624 | 63 | static DEFINE_CLOCK_DATA(cd); |
8a3269fc | 64 | |
5e06b649 | 65 | unsigned long long notrace sched_clock(void) |
a399e3fa | 66 | { |
4ee1f6b5 | 67 | u32 cyc = ~readl(timer_base + TIMER0_VAL_OFF); |
f06a1624 | 68 | return cyc_to_sched_clock(&cd, cyc, (u32)~0); |
a399e3fa NP |
69 | } |
70 | ||
a399e3fa | 71 | |
f06a1624 | 72 | static void notrace orion_update_sched_clock(void) |
a399e3fa | 73 | { |
4ee1f6b5 | 74 | u32 cyc = ~readl(timer_base + TIMER0_VAL_OFF); |
f06a1624 | 75 | update_sched_clock(&cd, cyc, (u32)~0); |
a399e3fa NP |
76 | } |
77 | ||
78 | static void __init setup_sched_clock(unsigned long tclk) | |
8a3269fc | 79 | { |
f06a1624 | 80 | init_sched_clock(&cd, orion_update_sched_clock, 32, tclk); |
8a3269fc SA |
81 | } |
82 | ||
2bac1de2 LB |
83 | /* |
84 | * Clocksource handling. | |
85 | */ | |
8e19608e | 86 | static cycle_t orion_clksrc_read(struct clocksource *cs) |
2bac1de2 | 87 | { |
4ee1f6b5 | 88 | return 0xffffffff - readl(timer_base + TIMER0_VAL_OFF); |
2bac1de2 LB |
89 | } |
90 | ||
91 | static struct clocksource orion_clksrc = { | |
92 | .name = "orion_clocksource", | |
2bac1de2 LB |
93 | .rating = 300, |
94 | .read = orion_clksrc_read, | |
95 | .mask = CLOCKSOURCE_MASK(32), | |
96 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
97 | }; | |
98 | ||
99 | ||
100 | ||
101 | /* | |
102 | * Clockevent handling. | |
103 | */ | |
104 | static int | |
105 | orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) | |
106 | { | |
107 | unsigned long flags; | |
108 | u32 u; | |
109 | ||
110 | if (delta == 0) | |
111 | return -ETIME; | |
112 | ||
113 | local_irq_save(flags); | |
114 | ||
115 | /* | |
116 | * Clear and enable clockevent timer interrupt. | |
117 | */ | |
4ee1f6b5 | 118 | writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); |
2bac1de2 | 119 | |
4ee1f6b5 | 120 | u = readl(bridge_base + BRIDGE_MASK_OFF); |
2bac1de2 | 121 | u |= BRIDGE_INT_TIMER1; |
4ee1f6b5 | 122 | writel(u, bridge_base + BRIDGE_MASK_OFF); |
2bac1de2 LB |
123 | |
124 | /* | |
125 | * Setup new clockevent timer value. | |
126 | */ | |
4ee1f6b5 | 127 | writel(delta, timer_base + TIMER1_VAL_OFF); |
2bac1de2 LB |
128 | |
129 | /* | |
130 | * Enable the timer. | |
131 | */ | |
4ee1f6b5 | 132 | u = readl(timer_base + TIMER_CTRL_OFF); |
2bac1de2 | 133 | u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN; |
4ee1f6b5 | 134 | writel(u, timer_base + TIMER_CTRL_OFF); |
2bac1de2 LB |
135 | |
136 | local_irq_restore(flags); | |
137 | ||
138 | return 0; | |
139 | } | |
140 | ||
141 | static void | |
142 | orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) | |
143 | { | |
144 | unsigned long flags; | |
145 | u32 u; | |
146 | ||
147 | local_irq_save(flags); | |
148 | if (mode == CLOCK_EVT_MODE_PERIODIC) { | |
149 | /* | |
150 | * Setup timer to fire at 1/HZ intervals. | |
151 | */ | |
4ee1f6b5 LB |
152 | writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF); |
153 | writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF); | |
2bac1de2 LB |
154 | |
155 | /* | |
156 | * Enable timer interrupt. | |
157 | */ | |
4ee1f6b5 LB |
158 | u = readl(bridge_base + BRIDGE_MASK_OFF); |
159 | writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); | |
2bac1de2 LB |
160 | |
161 | /* | |
162 | * Enable timer. | |
163 | */ | |
4ee1f6b5 LB |
164 | u = readl(timer_base + TIMER_CTRL_OFF); |
165 | writel(u | TIMER1_EN | TIMER1_RELOAD_EN, | |
166 | timer_base + TIMER_CTRL_OFF); | |
2bac1de2 LB |
167 | } else { |
168 | /* | |
169 | * Disable timer. | |
170 | */ | |
4ee1f6b5 LB |
171 | u = readl(timer_base + TIMER_CTRL_OFF); |
172 | writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF); | |
2bac1de2 LB |
173 | |
174 | /* | |
175 | * Disable timer interrupt. | |
176 | */ | |
4ee1f6b5 LB |
177 | u = readl(bridge_base + BRIDGE_MASK_OFF); |
178 | writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); | |
2bac1de2 LB |
179 | |
180 | /* | |
181 | * ACK pending timer interrupt. | |
182 | */ | |
4ee1f6b5 | 183 | writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); |
2bac1de2 LB |
184 | |
185 | } | |
186 | local_irq_restore(flags); | |
187 | } | |
188 | ||
189 | static struct clock_event_device orion_clkevt = { | |
190 | .name = "orion_tick", | |
191 | .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, | |
192 | .shift = 32, | |
193 | .rating = 300, | |
2bac1de2 LB |
194 | .set_next_event = orion_clkevt_next_event, |
195 | .set_mode = orion_clkevt_mode, | |
196 | }; | |
197 | ||
198 | static irqreturn_t orion_timer_interrupt(int irq, void *dev_id) | |
199 | { | |
200 | /* | |
201 | * ACK timer interrupt and call event handler. | |
202 | */ | |
4ee1f6b5 | 203 | writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); |
2bac1de2 LB |
204 | orion_clkevt.event_handler(&orion_clkevt); |
205 | ||
206 | return IRQ_HANDLED; | |
207 | } | |
208 | ||
209 | static struct irqaction orion_timer_irq = { | |
210 | .name = "orion_tick", | |
211 | .flags = IRQF_DISABLED | IRQF_TIMER, | |
212 | .handler = orion_timer_interrupt | |
213 | }; | |
214 | ||
4ee1f6b5 LB |
215 | void __init |
216 | orion_time_set_base(u32 _timer_base) | |
217 | { | |
218 | timer_base = (void __iomem *)_timer_base; | |
219 | } | |
220 | ||
221 | void __init | |
222 | orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask, | |
223 | unsigned int irq, unsigned int tclk) | |
2bac1de2 LB |
224 | { |
225 | u32 u; | |
226 | ||
4ee1f6b5 LB |
227 | /* |
228 | * Set SoC-specific data. | |
229 | */ | |
230 | bridge_base = (void __iomem *)_bridge_base; | |
231 | bridge_timer1_clr_mask = _bridge_timer1_clr_mask; | |
232 | ||
2bac1de2 LB |
233 | ticks_per_jiffy = (tclk + HZ/2) / HZ; |
234 | ||
8a3269fc | 235 | /* |
4ee1f6b5 | 236 | * Set scale and timer for sched_clock. |
8a3269fc | 237 | */ |
a399e3fa | 238 | setup_sched_clock(tclk); |
2bac1de2 LB |
239 | |
240 | /* | |
241 | * Setup free-running clocksource timer (interrupts | |
4ee1f6b5 | 242 | * disabled). |
2bac1de2 | 243 | */ |
4ee1f6b5 LB |
244 | writel(0xffffffff, timer_base + TIMER0_VAL_OFF); |
245 | writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); | |
246 | u = readl(bridge_base + BRIDGE_MASK_OFF); | |
247 | writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF); | |
248 | u = readl(timer_base + TIMER_CTRL_OFF); | |
249 | writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF); | |
1d0ac3cd | 250 | clocksource_register_hz(&orion_clksrc, tclk); |
2bac1de2 | 251 | |
2bac1de2 | 252 | /* |
4ee1f6b5 | 253 | * Setup clockevent timer (interrupt-driven). |
2bac1de2 LB |
254 | */ |
255 | setup_irq(irq, &orion_timer_irq); | |
256 | orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift); | |
257 | orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt); | |
258 | orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt); | |
320ab2b0 | 259 | orion_clkevt.cpumask = cpumask_of(0); |
2bac1de2 LB |
260 | clockevents_register_device(&orion_clkevt); |
261 | } |