[deliverable/linux.git] / arch / arm / plat-orion / time.c

/*
 * arch/arm/plat-orion/time.c
 *
 * Marvell Orion SoC timer handling.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * Timer 0 is used as free-running clocksource, while timer 1 is
 * used as clock_event_device.
 */

#include <linux/kernel.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/mach/time.h>
#include <mach/hardware.h>

/*
 * Number of timer ticks per jiffy.
 */
static u32 ticks_per_jiffy;


/*
 * Timer block registers.
 */
#define TIMER_CTRL		(TIMER_VIRT_BASE + 0x0000)
#define  TIMER0_EN		0x0001
#define  TIMER0_RELOAD_EN	0x0002
#define  TIMER1_EN		0x0004
#define  TIMER1_RELOAD_EN	0x0008
#define TIMER0_RELOAD		(TIMER_VIRT_BASE + 0x0010)
#define TIMER0_VAL		(TIMER_VIRT_BASE + 0x0014)
#define TIMER1_RELOAD		(TIMER_VIRT_BASE + 0x0018)
#define TIMER1_VAL		(TIMER_VIRT_BASE + 0x001c)


/*
 * Clocksource handling.
 */
static cycle_t orion_clksrc_read(struct clocksource *cs)
{
	return 0xffffffff - readl(TIMER0_VAL);
}

static struct clocksource orion_clksrc = {
	.name		= "orion_clocksource",
	.shift		= 20,
	.rating		= 300,
	.read		= orion_clksrc_read,
	.mask		= CLOCKSOURCE_MASK(32),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};


/*
 * Clockevent handling.
 */
static int
orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
{
	unsigned long flags;
	u32 u;

	if (delta == 0)
		return -ETIME;

	local_irq_save(flags);

	/*
	 * Clear and enable clockevent timer interrupt.
	 */
	writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);

	u = readl(BRIDGE_MASK);
	u |= BRIDGE_INT_TIMER1;
	writel(u, BRIDGE_MASK);

	/*
	 * Setup new clockevent timer value.
	 */
	writel(delta, TIMER1_VAL);

	/*
	 * Enable the timer.
	 */
	u = readl(TIMER_CTRL);
	u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
	writel(u, TIMER_CTRL);

	local_irq_restore(flags);

	return 0;
}

static void
orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
{
	unsigned long flags;
	u32 u;

	local_irq_save(flags);
	if (mode == CLOCK_EVT_MODE_PERIODIC) {
		/*
		 * Setup timer to fire at 1/HZ intervals.
		 */
		writel(ticks_per_jiffy - 1, TIMER1_RELOAD);
		writel(ticks_per_jiffy - 1, TIMER1_VAL);

		/*
		 * Enable timer interrupt.
		 */
		u = readl(BRIDGE_MASK);
		writel(u | BRIDGE_INT_TIMER1, BRIDGE_MASK);

		/*
		 * Enable timer.
		 */
		u = readl(TIMER_CTRL);
		writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL);
	} else {
		/*
		 * Disable timer.
		 */
		u = readl(TIMER_CTRL);
		writel(u & ~TIMER1_EN, TIMER_CTRL);

		/*
		 * Disable timer interrupt.
		 */
		u = readl(BRIDGE_MASK);
		writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK);

		/*
		 * ACK pending timer interrupt.
		 */
		writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);

	}
	local_irq_restore(flags);
}

static struct clock_event_device orion_clkevt = {
	.name		= "orion_tick",
	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
	.shift		= 32,
	.rating		= 300,
	.set_next_event	= orion_clkevt_next_event,
	.set_mode	= orion_clkevt_mode,
};

static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
{
	/*
	 * ACK timer interrupt and call event handler.
	 */
	writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
	orion_clkevt.event_handler(&orion_clkevt);

	return IRQ_HANDLED;
}

static struct irqaction orion_timer_irq = {
	.name		= "orion_tick",
	.flags		= IRQF_DISABLED | IRQF_TIMER,
	.handler	= orion_timer_interrupt
};

void __init orion_time_init(unsigned int irq, unsigned int tclk)
{
	u32 u;

	ticks_per_jiffy = (tclk + HZ/2) / HZ;


	/*
	 * Setup free-running clocksource timer (interrupts
	 * disabled.)
	 */
	writel(0xffffffff, TIMER0_VAL);
	writel(0xffffffff, TIMER0_RELOAD);
	u = readl(BRIDGE_MASK);
	writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK);
	u = readl(TIMER_CTRL);
	writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL);
	orion_clksrc.mult = clocksource_hz2mult(tclk, orion_clksrc.shift);
	clocksource_register(&orion_clksrc);


	/*
	 * Setup clockevent timer (interrupt-driven.)
	 */
	setup_irq(irq, &orion_timer_irq);
	orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
	orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt);
	orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt);
	orion_clkevt.cpumask = cpumask_of(0);
	clockevents_register_device(&orion_clkevt);
}
Commit	Line	Data
2bac1de2 LB	1	/*
	2	* arch/arm/plat-orion/time.c
	3	*
	4	* Marvell Orion SoC timer handling.
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*
	10	* Timer 0 is used as free-running clocksource, while timer 1 is
	11	* used as clock_event_device.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/clockchips.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/irq.h>
	18	#include <asm/mach/time.h>
a09e64fb	19	#include <mach/hardware.h>
2bac1de2 LB	20
	21	/*
	22	* Number of timer ticks per jiffy.
	23	*/
	24	static u32 ticks_per_jiffy;
	25
	26
	27	/*
	28	* Timer block registers.
	29	*/
	30	#define TIMER_CTRL (TIMER_VIRT_BASE + 0x0000)
	31	#define TIMER0_EN 0x0001
	32	#define TIMER0_RELOAD_EN 0x0002
	33	#define TIMER1_EN 0x0004
	34	#define TIMER1_RELOAD_EN 0x0008
	35	#define TIMER0_RELOAD (TIMER_VIRT_BASE + 0x0010)
	36	#define TIMER0_VAL (TIMER_VIRT_BASE + 0x0014)
	37	#define TIMER1_RELOAD (TIMER_VIRT_BASE + 0x0018)
	38	#define TIMER1_VAL (TIMER_VIRT_BASE + 0x001c)
	39
	40
	41	/*
	42	* Clocksource handling.
	43	*/
8e19608e	44	static cycle_t orion_clksrc_read(struct clocksource *cs)
2bac1de2 LB	45	{
	46	return 0xffffffff - readl(TIMER0_VAL);
	47	}
	48
	49	static struct clocksource orion_clksrc = {
	50	.name = "orion_clocksource",
	51	.shift = 20,
	52	.rating = 300,
	53	.read = orion_clksrc_read,
	54	.mask = CLOCKSOURCE_MASK(32),
	55	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	56	};
	57
	58
	59
	60	/*
	61	* Clockevent handling.
	62	*/
	63	static int
	64	orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
	65	{
	66	unsigned long flags;
	67	u32 u;
	68
	69	if (delta == 0)
	70	return -ETIME;
	71
	72	local_irq_save(flags);
	73
	74	/*
	75	* Clear and enable clockevent timer interrupt.
	76	*/
1219715d	77	writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
2bac1de2 LB	78
	79	u = readl(BRIDGE_MASK);
	80	u \|= BRIDGE_INT_TIMER1;
	81	writel(u, BRIDGE_MASK);
	82
	83	/*
	84	* Setup new clockevent timer value.
	85	*/
	86	writel(delta, TIMER1_VAL);
	87
	88	/*
	89	* Enable the timer.
	90	*/
	91	u = readl(TIMER_CTRL);
	92	u = (u & ~TIMER1_RELOAD_EN) \| TIMER1_EN;
	93	writel(u, TIMER_CTRL);
	94
	95	local_irq_restore(flags);
	96
	97	return 0;
	98	}
	99
	100	static void
	101	orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
	102	{
	103	unsigned long flags;
	104	u32 u;
	105
	106	local_irq_save(flags);
	107	if (mode == CLOCK_EVT_MODE_PERIODIC) {
	108	/*
	109	* Setup timer to fire at 1/HZ intervals.
	110	*/
	111	writel(ticks_per_jiffy - 1, TIMER1_RELOAD);
	112	writel(ticks_per_jiffy - 1, TIMER1_VAL);
	113
	114	/*
	115	* Enable timer interrupt.
	116	*/
	117	u = readl(BRIDGE_MASK);
	118	writel(u \| BRIDGE_INT_TIMER1, BRIDGE_MASK);
	119
	120	/*
	121	* Enable timer.
	122	*/
	123	u = readl(TIMER_CTRL);
	124	writel(u \| TIMER1_EN \| TIMER1_RELOAD_EN, TIMER_CTRL);
	125	} else {
	126	/*
	127	* Disable timer.
	128	*/
	129	u = readl(TIMER_CTRL);
	130	writel(u & ~TIMER1_EN, TIMER_CTRL);
	131
	132	/*
	133	* Disable timer interrupt.
	134	*/
	135	u = readl(BRIDGE_MASK);
	136	writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK);
	137
	138	/*
	139	* ACK pending timer interrupt.
	140	*/
1219715d	141	writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
2bac1de2 LB	142
	143	}
	144	local_irq_restore(flags);
	145	}
	146
	147	static struct clock_event_device orion_clkevt = {
	148	.name = "orion_tick",
	149	.features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_PERIODIC,
	150	.shift = 32,
	151	.rating = 300,
2bac1de2 LB	152	.set_next_event = orion_clkevt_next_event,
	153	.set_mode = orion_clkevt_mode,
	154	};
	155
	156	static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
	157	{
	158	/*
	159	* ACK timer interrupt and call event handler.
	160	*/
1219715d	161	writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
2bac1de2 LB	162	orion_clkevt.event_handler(&orion_clkevt);
	163
	164	return IRQ_HANDLED;
	165	}
	166
	167	static struct irqaction orion_timer_irq = {
	168	.name = "orion_tick",
	169	.flags = IRQF_DISABLED \| IRQF_TIMER,
	170	.handler = orion_timer_interrupt
	171	};
	172
	173	void __init orion_time_init(unsigned int irq, unsigned int tclk)
	174	{
	175	u32 u;
	176
	177	ticks_per_jiffy = (tclk + HZ/2) / HZ;
	178
	179
	180	/*
	181	* Setup free-running clocksource timer (interrupts
	182	* disabled.)
	183	*/
	184	writel(0xffffffff, TIMER0_VAL);
	185	writel(0xffffffff, TIMER0_RELOAD);
	186	u = readl(BRIDGE_MASK);
	187	writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK);
	188	u = readl(TIMER_CTRL);
	189	writel(u \| TIMER0_EN \| TIMER0_RELOAD_EN, TIMER_CTRL);
	190	orion_clksrc.mult = clocksource_hz2mult(tclk, orion_clksrc.shift);
	191	clocksource_register(&orion_clksrc);
	192
	193
	194	/*
	195	* Setup clockevent timer (interrupt-driven.)
	196	*/
	197	setup_irq(irq, &orion_timer_irq);
	198	orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
	199	orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt);
	200	orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt);
320ab2b0	201	orion_clkevt.cpumask = cpumask_of(0);
2bac1de2 LB	202	clockevents_register_device(&orion_clkevt);
2bac1de2 LB	203	}