Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
bd5ce433 | 2 | * linux/arch/arm/plat-pxa/dma.c |
1da177e4 LT |
3 | * |
4 | * PXA DMA registration and IRQ dispatching | |
5 | * | |
6 | * Author: Nicolas Pitre | |
7 | * Created: Nov 15, 2001 | |
8 | * Copyright: MontaVista Software Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/module.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/errno.h> | |
20 | ||
21 | #include <asm/system.h> | |
22 | #include <asm/irq.h> | |
a09e64fb | 23 | #include <mach/hardware.h> |
dcea83ad | 24 | #include <mach/dma.h> |
1da177e4 | 25 | |
f53f066c | 26 | struct dma_channel { |
1da177e4 | 27 | char *name; |
f53f066c | 28 | pxa_dma_prio prio; |
0cd61b68 | 29 | void (*irq_handler)(int, void *); |
1da177e4 | 30 | void *data; |
f53f066c | 31 | }; |
1da177e4 | 32 | |
f53f066c EM |
33 | static struct dma_channel *dma_channels; |
34 | static int num_dma_channels; | |
1da177e4 LT |
35 | |
36 | int pxa_request_dma (char *name, pxa_dma_prio prio, | |
bd5ce433 EM |
37 | void (*irq_handler)(int, void *), |
38 | void *data) | |
1da177e4 LT |
39 | { |
40 | unsigned long flags; | |
41 | int i, found = 0; | |
42 | ||
43 | /* basic sanity checks */ | |
44 | if (!name || !irq_handler) | |
45 | return -EINVAL; | |
46 | ||
47 | local_irq_save(flags); | |
48 | ||
99532559 NP |
49 | do { |
50 | /* try grabbing a DMA channel with the requested priority */ | |
f53f066c EM |
51 | for (i = 0; i < num_dma_channels; i++) { |
52 | if ((dma_channels[i].prio == prio) && | |
53 | !dma_channels[i].name) { | |
1da177e4 LT |
54 | found = 1; |
55 | break; | |
56 | } | |
57 | } | |
99532559 NP |
58 | /* if requested prio group is full, try a hier priority */ |
59 | } while (!found && prio--); | |
1da177e4 LT |
60 | |
61 | if (found) { | |
62 | DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; | |
63 | dma_channels[i].name = name; | |
64 | dma_channels[i].irq_handler = irq_handler; | |
65 | dma_channels[i].data = data; | |
66 | } else { | |
67 | printk (KERN_WARNING "No more available DMA channels for %s\n", name); | |
68 | i = -ENODEV; | |
69 | } | |
70 | ||
71 | local_irq_restore(flags); | |
72 | return i; | |
73 | } | |
74 | ||
75 | void pxa_free_dma (int dma_ch) | |
76 | { | |
77 | unsigned long flags; | |
78 | ||
79 | if (!dma_channels[dma_ch].name) { | |
80 | printk (KERN_CRIT | |
81 | "%s: trying to free channel %d which is already freed\n", | |
8e86f427 | 82 | __func__, dma_ch); |
1da177e4 LT |
83 | return; |
84 | } | |
85 | ||
86 | local_irq_save(flags); | |
87 | DCSR(dma_ch) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; | |
88 | dma_channels[dma_ch].name = NULL; | |
89 | local_irq_restore(flags); | |
90 | } | |
91 | ||
0cd61b68 | 92 | static irqreturn_t dma_irq_handler(int irq, void *dev_id) |
1da177e4 LT |
93 | { |
94 | int i, dint = DINT; | |
95 | ||
f53f066c | 96 | for (i = 0; i < num_dma_channels; i++) { |
1da177e4 LT |
97 | if (dint & (1 << i)) { |
98 | struct dma_channel *channel = &dma_channels[i]; | |
99 | if (channel->name && channel->irq_handler) { | |
0cd61b68 | 100 | channel->irq_handler(i, channel->data); |
1da177e4 LT |
101 | } else { |
102 | /* | |
103 | * IRQ for an unregistered DMA channel: | |
104 | * let's clear the interrupts and disable it. | |
105 | */ | |
106 | printk (KERN_WARNING "spurious IRQ for DMA channel %d\n", i); | |
107 | DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; | |
108 | } | |
109 | } | |
110 | } | |
111 | return IRQ_HANDLED; | |
112 | } | |
113 | ||
fef1f99a | 114 | int __init pxa_init_dma(int irq, int num_ch) |
1da177e4 | 115 | { |
f53f066c | 116 | int i, ret; |
1da177e4 | 117 | |
f53f066c EM |
118 | dma_channels = kzalloc(sizeof(struct dma_channel) * num_ch, GFP_KERNEL); |
119 | if (dma_channels == NULL) | |
120 | return -ENOMEM; | |
121 | ||
f53f066c EM |
122 | /* dma channel priorities on pxa2xx processors: |
123 | * ch 0 - 3, 16 - 19 <--> (0) DMA_PRIO_HIGH | |
124 | * ch 4 - 7, 20 - 23 <--> (1) DMA_PRIO_MEDIUM | |
125 | * ch 8 - 15, 24 - 31 <--> (2) DMA_PRIO_LOW | |
126 | */ | |
26a55226 EM |
127 | for (i = 0; i < num_ch; i++) { |
128 | DCSR(i) = 0; | |
f53f066c | 129 | dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW); |
26a55226 EM |
130 | } |
131 | ||
fef1f99a | 132 | ret = request_irq(irq, dma_irq_handler, IRQF_DISABLED, "DMA", NULL); |
26a55226 EM |
133 | if (ret) { |
134 | printk (KERN_CRIT "Wow! Can't register IRQ for DMA\n"); | |
135 | kfree(dma_channels); | |
136 | return ret; | |
137 | } | |
f53f066c EM |
138 | |
139 | num_dma_channels = num_ch; | |
140 | return 0; | |
141 | } | |
1da177e4 LT |
142 | |
143 | EXPORT_SYMBOL(pxa_request_dma); | |
144 | EXPORT_SYMBOL(pxa_free_dma); |