[deliverable/linux.git] / arch / arm / plat-pxa / dma.c

/*
 *  linux/arch/arm/plat-pxa/dma.c
 *
 *  PXA DMA registration and IRQ dispatching
 *
 *  Author:	Nicolas Pitre
 *  Created:	Nov 15, 2001
 *  Copyright:	MontaVista Software Inc.
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/errno.h>
#include <linux/dma-mapping.h>

#include <asm/irq.h>
#include <asm/memory.h>
#include <mach/hardware.h>
#include <mach/dma.h>

#define DMA_DEBUG_NAME		"pxa_dma"
#define DMA_MAX_REQUESTERS	64

struct dma_channel {
	char *name;
	pxa_dma_prio prio;
	void (*irq_handler)(int, void *);
	void *data;
	spinlock_t lock;
};

static struct dma_channel *dma_channels;
static int num_dma_channels;

/*
 * Debug fs
 */
#ifdef CONFIG_DEBUG_FS
#include <linux/debugfs.h>
#include <linux/uaccess.h>
#include <linux/seq_file.h>

static struct dentry *dbgfs_root, *dbgfs_state, **dbgfs_chan;

static int dbg_show_requester_chan(struct seq_file *s, void *p)
{
	int chan = (int)s->private;
	int i;
	u32 drcmr;

	seq_printf(s, "DMA channel %d requesters list :\n", chan);
	for (i = 0; i < DMA_MAX_REQUESTERS; i++) {
		drcmr = DRCMR(i);
		if ((drcmr & DRCMR_CHLNUM) == chan)
			seq_printf(s, "\tRequester %d (MAPVLD=%d)\n",
				   i, !!(drcmr & DRCMR_MAPVLD));
	}

	return 0;
}

static inline int dbg_burst_from_dcmd(u32 dcmd)
{
	int burst = (dcmd >> 16) & 0x3;

	return burst ? 4 << burst : 0;
}

static int is_phys_valid(unsigned long addr)
{
	return pfn_valid(__phys_to_pfn(addr));
}

#define DCSR_STR(flag) (dcsr & DCSR_##flag ? #flag" " : "")
#define DCMD_STR(flag) (dcmd & DCMD_##flag ? #flag" " : "")

static int dbg_show_descriptors(struct seq_file *s, void *p)
{
	int chan = (int)s->private;
	int i, max_show = 20, burst, width;
	u32 dcmd;
	unsigned long phys_desc;
	struct pxa_dma_desc *desc;
	unsigned long flags;

	spin_lock_irqsave(&dma_channels[chan].lock, flags);
	phys_desc = DDADR(chan);

	seq_printf(s, "DMA channel %d descriptors :\n", chan);
	seq_printf(s, "[%03d] First descriptor unknown\n", 0);
	for (i = 1; i < max_show && is_phys_valid(phys_desc); i++) {
		desc = phys_to_virt(phys_desc);
		dcmd = desc->dcmd;
		burst = dbg_burst_from_dcmd(dcmd);
		width = (1 << ((dcmd >> 14) & 0x3)) >> 1;

		seq_printf(s, "[%03d] Desc at %08lx(virt %p)\n",
			   i, phys_desc, desc);
		seq_printf(s, "\tDDADR = %08x\n", desc->ddadr);
		seq_printf(s, "\tDSADR = %08x\n", desc->dsadr);
		seq_printf(s, "\tDTADR = %08x\n", desc->dtadr);
		seq_printf(s, "\tDCMD  = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n",
			   dcmd,
			   DCMD_STR(INCSRCADDR), DCMD_STR(INCTRGADDR),
			   DCMD_STR(FLOWSRC), DCMD_STR(FLOWTRG),
			   DCMD_STR(STARTIRQEN), DCMD_STR(ENDIRQEN),
			   DCMD_STR(ENDIAN), burst, width,
			   dcmd & DCMD_LENGTH);
		phys_desc = desc->ddadr;
	}
	if (i == max_show)
		seq_printf(s, "[%03d] Desc at %08lx ... max display reached\n",
			   i, phys_desc);
	else
		seq_printf(s, "[%03d] Desc at %08lx is %s\n",
			   i, phys_desc, phys_desc == DDADR_STOP ?
			   "DDADR_STOP" : "invalid");

	spin_unlock_irqrestore(&dma_channels[chan].lock, flags);

	return 0;
}

static int dbg_show_chan_state(struct seq_file *s, void *p)
{
	int chan = (int)s->private;
	u32 dcsr, dcmd;
	int burst, width;
	static char *str_prio[] = { "high", "normal", "low" };

	dcsr = DCSR(chan);
	dcmd = DCMD(chan);
	burst = dbg_burst_from_dcmd(dcmd);
	width = (1 << ((dcmd >> 14) & 0x3)) >> 1;

	seq_printf(s, "DMA channel %d\n", chan);
	seq_printf(s, "\tPriority : %s\n", str_prio[dma_channels[chan].prio]);
	seq_printf(s, "\tUnaligned transfer bit: %s\n",
		   DALGN & (1 << chan) ? "yes" : "no");
	seq_printf(s, "\tDCSR  = %08x (%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
		   dcsr, DCSR_STR(RUN), DCSR_STR(NODESC),
		   DCSR_STR(STOPIRQEN), DCSR_STR(EORIRQEN),
		   DCSR_STR(EORJMPEN), DCSR_STR(EORSTOPEN),
		   DCSR_STR(SETCMPST), DCSR_STR(CLRCMPST),
		   DCSR_STR(CMPST), DCSR_STR(EORINTR), DCSR_STR(REQPEND),
		   DCSR_STR(STOPSTATE), DCSR_STR(ENDINTR),
		   DCSR_STR(STARTINTR), DCSR_STR(BUSERR));

	seq_printf(s, "\tDCMD  = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n",
		   dcmd,
		   DCMD_STR(INCSRCADDR), DCMD_STR(INCTRGADDR),
		   DCMD_STR(FLOWSRC), DCMD_STR(FLOWTRG),
		   DCMD_STR(STARTIRQEN), DCMD_STR(ENDIRQEN),
		   DCMD_STR(ENDIAN), burst, width, dcmd & DCMD_LENGTH);
	seq_printf(s, "\tDSADR = %08x\n", DSADR(chan));
	seq_printf(s, "\tDTADR = %08x\n", DTADR(chan));
	seq_printf(s, "\tDDADR = %08x\n", DDADR(chan));

	return 0;
}

static int dbg_show_state(struct seq_file *s, void *p)
{
	/* basic device status */
	seq_puts(s, "DMA engine status\n");
	seq_printf(s, "\tChannel number: %d\n", num_dma_channels);

	return 0;
}

#define DBGFS_FUNC_DECL(name) \
static int dbg_open_##name(struct inode *inode, struct file *file) \
{ \
	return single_open(file, dbg_show_##name, inode->i_private); \
} \
static const struct file_operations dbg_fops_##name = { \
	.owner		= THIS_MODULE, \
	.open		= dbg_open_##name, \
	.llseek		= seq_lseek, \
	.read		= seq_read, \
	.release	= single_release, \
}

DBGFS_FUNC_DECL(state);
DBGFS_FUNC_DECL(chan_state);
DBGFS_FUNC_DECL(descriptors);
DBGFS_FUNC_DECL(requester_chan);

static struct dentry *pxa_dma_dbg_alloc_chan(int ch, struct dentry *chandir)
{
	char chan_name[11];
	struct dentry *chan, *chan_state = NULL, *chan_descr = NULL;
	struct dentry *chan_reqs = NULL;
	void *dt;

	scnprintf(chan_name, sizeof(chan_name), "%d", ch);
	chan = debugfs_create_dir(chan_name, chandir);
	dt = (void *)ch;

	if (chan)
		chan_state = debugfs_create_file("state", 0400, chan, dt,
						 &dbg_fops_chan_state);
	if (chan_state)
		chan_descr = debugfs_create_file("descriptors", 0400, chan, dt,
						 &dbg_fops_descriptors);
	if (chan_descr)
		chan_reqs = debugfs_create_file("requesters", 0400, chan, dt,
						&dbg_fops_requester_chan);
	if (!chan_reqs)
		goto err_state;

	return chan;

err_state:
	debugfs_remove_recursive(chan);
	return NULL;
}

static void pxa_dma_init_debugfs(void)
{
	int i;
	struct dentry *chandir;

	dbgfs_root = debugfs_create_dir(DMA_DEBUG_NAME, NULL);
	if (IS_ERR(dbgfs_root) || !dbgfs_root)
		goto err_root;

	dbgfs_state = debugfs_create_file("state", 0400, dbgfs_root, NULL,
					  &dbg_fops_state);
	if (!dbgfs_state)
		goto err_state;

	dbgfs_chan = kmalloc(sizeof(*dbgfs_state) * num_dma_channels,
			     GFP_KERNEL);
	if (!dbgfs_chan)
		goto err_alloc;

	chandir = debugfs_create_dir("channels", dbgfs_root);
	if (!chandir)
		goto err_chandir;

	for (i = 0; i < num_dma_channels; i++) {
		dbgfs_chan[i] = pxa_dma_dbg_alloc_chan(i, chandir);
		if (!dbgfs_chan[i])
			goto err_chans;
	}

	return;
err_chans:
err_chandir:
	kfree(dbgfs_chan);
err_alloc:
err_state:
	debugfs_remove_recursive(dbgfs_root);
err_root:
	pr_err("pxa_dma: debugfs is not available\n");
}

static void __exit pxa_dma_cleanup_debugfs(void)
{
	debugfs_remove_recursive(dbgfs_root);
}
#else
static inline void pxa_dma_init_debugfs(void) {}
static inline void pxa_dma_cleanup_debugfs(void) {}
#endif

int pxa_request_dma (char *name, pxa_dma_prio prio,
			void (*irq_handler)(int, void *),
			void *data)
{
	unsigned long flags;
	int i, found = 0;

	/* basic sanity checks */
	if (!name || !irq_handler)
		return -EINVAL;

	local_irq_save(flags);

	do {
		/* try grabbing a DMA channel with the requested priority */
		for (i = 0; i < num_dma_channels; i++) {
			if ((dma_channels[i].prio == prio) &&
			    !dma_channels[i].name &&
			    !pxad_toggle_reserved_channel(i)) {
				found = 1;
				break;
			}
		}
		/* if requested prio group is full, try a hier priority */
	} while (!found && prio--);

	if (found) {
		DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
		dma_channels[i].name = name;
		dma_channels[i].irq_handler = irq_handler;
		dma_channels[i].data = data;
	} else {
		printk (KERN_WARNING "No more available DMA channels for %s\n", name);
		i = -ENODEV;
	}

	local_irq_restore(flags);
	return i;
}
EXPORT_SYMBOL(pxa_request_dma);

void pxa_free_dma (int dma_ch)
{
	unsigned long flags;

	if (!dma_channels[dma_ch].name) {
		printk (KERN_CRIT
			"%s: trying to free channel %d which is already freed\n",
			__func__, dma_ch);
		return;
	}

	local_irq_save(flags);
	DCSR(dma_ch) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
	dma_channels[dma_ch].name = NULL;
	pxad_toggle_reserved_channel(dma_ch);
	local_irq_restore(flags);
}
EXPORT_SYMBOL(pxa_free_dma);

static irqreturn_t dma_irq_handler(int irq, void *dev_id)
{
	int i, dint = DINT, done = 0;
	struct dma_channel *channel;

	while (dint) {
		i = __ffs(dint);
		dint &= (dint - 1);
		channel = &dma_channels[i];
		if (channel->name && channel->irq_handler) {
			channel->irq_handler(i, channel->data);
			done++;
		}
	}
	if (done)
		return IRQ_HANDLED;
	else
		return IRQ_NONE;
}

int __init pxa_init_dma(int irq, int num_ch)
{
	int i, ret;

	dma_channels = kzalloc(sizeof(struct dma_channel) * num_ch, GFP_KERNEL);
	if (dma_channels == NULL)
		return -ENOMEM;

	/* dma channel priorities on pxa2xx processors:
	 * ch 0 - 3,  16 - 19  <--> (0) DMA_PRIO_HIGH
	 * ch 4 - 7,  20 - 23  <--> (1) DMA_PRIO_MEDIUM
	 * ch 8 - 15, 24 - 31  <--> (2) DMA_PRIO_LOW
	 */
	for (i = 0; i < num_ch; i++) {
		DCSR(i) = 0;
		dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW);
		spin_lock_init(&dma_channels[i].lock);
	}

	ret = request_irq(irq, dma_irq_handler, IRQF_SHARED, "DMA",
			  dma_channels);
	if (ret) {
		printk (KERN_CRIT "Wow!  Can't register IRQ for DMA\n");
		kfree(dma_channels);
		return ret;
	}
	num_dma_channels = num_ch;

	pxa_dma_init_debugfs();

	return 0;
}
Commit	Line	Data
1da177e4	1	/*
bd5ce433	2	* linux/arch/arm/plat-pxa/dma.c
1da177e4 LT	3	*
	4	* PXA DMA registration and IRQ dispatching
	5	*
	6	* Author: Nicolas Pitre
	7	* Created: Nov 15, 2001
	8	* Copyright: MontaVista Software Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/module.h>
	16	#include <linux/init.h>
5a0e3ad6	17	#include <linux/slab.h>
1da177e4 LT	18	#include <linux/kernel.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/errno.h>
d294948c	21	#include <linux/dma-mapping.h>
1da177e4	22
1da177e4	23	#include <asm/irq.h>
d294948c	24	#include <asm/memory.h>
a09e64fb	25	#include <mach/hardware.h>
dcea83ad	26	#include <mach/dma.h>
1da177e4	27
d294948c RJ	28	#define DMA_DEBUG_NAME "pxa_dma"
	29	#define DMA_MAX_REQUESTERS 64
	30
f53f066c	31	struct dma_channel {
1da177e4	32	char *name;
f53f066c	33	pxa_dma_prio prio;
0cd61b68	34	void (irq_handler)(int, void );
1da177e4	35	void *data;
d294948c	36	spinlock_t lock;
f53f066c	37	};
1da177e4	38
f53f066c EM	39	static struct dma_channel *dma_channels;
f53f066c EM	40	static int num_dma_channels;
1da177e4	41
d294948c RJ	42	/*
	43	* Debug fs
	44	*/
	45	#ifdef CONFIG_DEBUG_FS
	46	#include <linux/debugfs.h>
	47	#include <linux/uaccess.h>
	48	#include <linux/seq_file.h>
	49
	50	static struct dentry dbgfs_root, dbgfs_state, **dbgfs_chan;
	51
	52	static int dbg_show_requester_chan(struct seq_file s, void p)
	53	{
d294948c RJ	54	int chan = (int)s->private;
	55	int i;
	56	u32 drcmr;
	57
cd2b2937	58	seq_printf(s, "DMA channel %d requesters list :\n", chan);
d294948c RJ	59	for (i = 0; i < DMA_MAX_REQUESTERS; i++) {
	60	drcmr = DRCMR(i);
	61	if ((drcmr & DRCMR_CHLNUM) == chan)
cd2b2937 JP	62	seq_printf(s, "\tRequester %d (MAPVLD=%d)\n",
cd2b2937 JP	63	i, !!(drcmr & DRCMR_MAPVLD));
d294948c	64	}
cd2b2937 JP	65
cd2b2937 JP	66	return 0;
d294948c RJ	67	}
	68
	69	static inline int dbg_burst_from_dcmd(u32 dcmd)
	70	{
	71	int burst = (dcmd >> 16) & 0x3;
	72
	73	return burst ? 4 << burst : 0;
	74	}
	75
	76	static int is_phys_valid(unsigned long addr)
	77	{
	78	return pfn_valid(__phys_to_pfn(addr));
	79	}
	80
	81	#define DCSR_STR(flag) (dcsr & DCSR_##flag ? #flag" " : "")
	82	#define DCMD_STR(flag) (dcmd & DCMD_##flag ? #flag" " : "")
	83
	84	static int dbg_show_descriptors(struct seq_file s, void p)
	85	{
d294948c RJ	86	int chan = (int)s->private;
	87	int i, max_show = 20, burst, width;
	88	u32 dcmd;
	89	unsigned long phys_desc;
	90	struct pxa_dma_desc *desc;
	91	unsigned long flags;
	92
	93	spin_lock_irqsave(&dma_channels[chan].lock, flags);
	94	phys_desc = DDADR(chan);
	95
cd2b2937 JP	96	seq_printf(s, "DMA channel %d descriptors :\n", chan);
cd2b2937 JP	97	seq_printf(s, "[%03d] First descriptor unknown\n", 0);
d294948c RJ	98	for (i = 1; i < max_show && is_phys_valid(phys_desc); i++) {
	99	desc = phys_to_virt(phys_desc);
	100	dcmd = desc->dcmd;
	101	burst = dbg_burst_from_dcmd(dcmd);
	102	width = (1 << ((dcmd >> 14) & 0x3)) >> 1;
	103
cd2b2937 JP	104	seq_printf(s, "[%03d] Desc at %08lx(virt %p)\n",
	105	i, phys_desc, desc);
	106	seq_printf(s, "\tDDADR = %08x\n", desc->ddadr);
	107	seq_printf(s, "\tDSADR = %08x\n", desc->dsadr);
	108	seq_printf(s, "\tDTADR = %08x\n", desc->dtadr);
	109	seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n",
	110	dcmd,
	111	DCMD_STR(INCSRCADDR), DCMD_STR(INCTRGADDR),
	112	DCMD_STR(FLOWSRC), DCMD_STR(FLOWTRG),
	113	DCMD_STR(STARTIRQEN), DCMD_STR(ENDIRQEN),
	114	DCMD_STR(ENDIAN), burst, width,
	115	dcmd & DCMD_LENGTH);
d294948c RJ	116	phys_desc = desc->ddadr;
	117	}
	118	if (i == max_show)
cd2b2937 JP	119	seq_printf(s, "[%03d] Desc at %08lx ... max display reached\n",
cd2b2937 JP	120	i, phys_desc);
d294948c	121	else
cd2b2937 JP	122	seq_printf(s, "[%03d] Desc at %08lx is %s\n",
	123	i, phys_desc, phys_desc == DDADR_STOP ?
	124	"DDADR_STOP" : "invalid");
d294948c RJ	125
d294948c RJ	126	spin_unlock_irqrestore(&dma_channels[chan].lock, flags);
cd2b2937 JP	127
cd2b2937 JP	128	return 0;
d294948c RJ	129	}
	130
	131	static int dbg_show_chan_state(struct seq_file s, void p)
	132	{
d294948c RJ	133	int chan = (int)s->private;
	134	u32 dcsr, dcmd;
	135	int burst, width;
	136	static char *str_prio[] = { "high", "normal", "low" };
	137
	138	dcsr = DCSR(chan);
	139	dcmd = DCMD(chan);
	140	burst = dbg_burst_from_dcmd(dcmd);
	141	width = (1 << ((dcmd >> 14) & 0x3)) >> 1;
	142
cd2b2937 JP	143	seq_printf(s, "DMA channel %d\n", chan);
	144	seq_printf(s, "\tPriority : %s\n", str_prio[dma_channels[chan].prio]);
	145	seq_printf(s, "\tUnaligned transfer bit: %s\n",
	146	DALGN & (1 << chan) ? "yes" : "no");
	147	seq_printf(s, "\tDCSR = %08x (%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
	148	dcsr, DCSR_STR(RUN), DCSR_STR(NODESC),
	149	DCSR_STR(STOPIRQEN), DCSR_STR(EORIRQEN),
	150	DCSR_STR(EORJMPEN), DCSR_STR(EORSTOPEN),
	151	DCSR_STR(SETCMPST), DCSR_STR(CLRCMPST),
	152	DCSR_STR(CMPST), DCSR_STR(EORINTR), DCSR_STR(REQPEND),
	153	DCSR_STR(STOPSTATE), DCSR_STR(ENDINTR),
	154	DCSR_STR(STARTINTR), DCSR_STR(BUSERR));
	155
	156	seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n",
	157	dcmd,
	158	DCMD_STR(INCSRCADDR), DCMD_STR(INCTRGADDR),
	159	DCMD_STR(FLOWSRC), DCMD_STR(FLOWTRG),
	160	DCMD_STR(STARTIRQEN), DCMD_STR(ENDIRQEN),
	161	DCMD_STR(ENDIAN), burst, width, dcmd & DCMD_LENGTH);
	162	seq_printf(s, "\tDSADR = %08x\n", DSADR(chan));
	163	seq_printf(s, "\tDTADR = %08x\n", DTADR(chan));
	164	seq_printf(s, "\tDDADR = %08x\n", DDADR(chan));
	165
	166	return 0;
d294948c RJ	167	}
	168
	169	static int dbg_show_state(struct seq_file s, void p)
	170	{
d294948c	171	/* basic device status */
cd2b2937 JP	172	seq_puts(s, "DMA engine status\n");
cd2b2937 JP	173	seq_printf(s, "\tChannel number: %d\n", num_dma_channels);
d294948c	174
cd2b2937	175	return 0;
d294948c RJ	176	}
	177
	178	#define DBGFS_FUNC_DECL(name) \
	179	static int dbg_open_##name(struct inode inode, struct file file) \
	180	{ \
	181	return single_open(file, dbg_show_##name, inode->i_private); \
	182	} \
	183	static const struct file_operations dbg_fops_##name = { \
	184	.owner = THIS_MODULE, \
	185	.open = dbg_open_##name, \
	186	.llseek = seq_lseek, \
	187	.read = seq_read, \
	188	.release = single_release, \
	189	}
	190
	191	DBGFS_FUNC_DECL(state);
	192	DBGFS_FUNC_DECL(chan_state);
	193	DBGFS_FUNC_DECL(descriptors);
	194	DBGFS_FUNC_DECL(requester_chan);
	195
	196	static struct dentry pxa_dma_dbg_alloc_chan(int ch, struct dentry chandir)
	197	{
	198	char chan_name[11];
	199	struct dentry chan, chan_state = NULL, *chan_descr = NULL;
	200	struct dentry *chan_reqs = NULL;
	201	void *dt;
	202
	203	scnprintf(chan_name, sizeof(chan_name), "%d", ch);
	204	chan = debugfs_create_dir(chan_name, chandir);
	205	dt = (void *)ch;
	206
	207	if (chan)
	208	chan_state = debugfs_create_file("state", 0400, chan, dt,
	209	&dbg_fops_chan_state);
	210	if (chan_state)
	211	chan_descr = debugfs_create_file("descriptors", 0400, chan, dt,
	212	&dbg_fops_descriptors);
	213	if (chan_descr)
	214	chan_reqs = debugfs_create_file("requesters", 0400, chan, dt,
	215	&dbg_fops_requester_chan);
	216	if (!chan_reqs)
	217	goto err_state;
	218
	219	return chan;
	220
	221	err_state:
	222	debugfs_remove_recursive(chan);
	223	return NULL;
	224	}
	225
	226	static void pxa_dma_init_debugfs(void)
	227	{
	228	int i;
	229	struct dentry *chandir;
	230
	231	dbgfs_root = debugfs_create_dir(DMA_DEBUG_NAME, NULL);
	232	if (IS_ERR(dbgfs_root) \|\| !dbgfs_root)
	233	goto err_root;
	234
	235	dbgfs_state = debugfs_create_file("state", 0400, dbgfs_root, NULL,
	236	&dbg_fops_state);
	237	if (!dbgfs_state)
	238	goto err_state;
	239
240	dbgfs_chan = kmalloc(sizeof(dbgfs_state) num_dma_channels,
241	GFP_KERNEL);
d54690fe	242	if (!dbgfs_chan)
d294948c RJ	243	goto err_alloc;
	244
	245	chandir = debugfs_create_dir("channels", dbgfs_root);
	246	if (!chandir)
	247	goto err_chandir;
	248
	249	for (i = 0; i < num_dma_channels; i++) {
	250	dbgfs_chan[i] = pxa_dma_dbg_alloc_chan(i, chandir);
	251	if (!dbgfs_chan[i])
	252	goto err_chans;
	253	}
	254
	255	return;
	256	err_chans:
	257	err_chandir:
	258	kfree(dbgfs_chan);
	259	err_alloc:
	260	err_state:
	261	debugfs_remove_recursive(dbgfs_root);
	262	err_root:
	263	pr_err("pxa_dma: debugfs is not available\n");
	264	}
	265
	266	static void __exit pxa_dma_cleanup_debugfs(void)
	267	{
	268	debugfs_remove_recursive(dbgfs_root);
	269	}
	270	#else
	271	static inline void pxa_dma_init_debugfs(void) {}
	272	static inline void pxa_dma_cleanup_debugfs(void) {}
	273	#endif
	274
1da177e4	275	int pxa_request_dma (char *name, pxa_dma_prio prio,
bd5ce433 EM	276	void (irq_handler)(int, void ),
bd5ce433 EM	277	void *data)
1da177e4 LT	278	{
	279	unsigned long flags;
	280	int i, found = 0;
	281
	282	/* basic sanity checks */
	283	if (!name \|\| !irq_handler)
	284	return -EINVAL;
	285
	286	local_irq_save(flags);
	287
99532559 NP	288	do {
99532559 NP	289	/* try grabbing a DMA channel with the requested priority */
f53f066c EM	290	for (i = 0; i < num_dma_channels; i++) {
f53f066c EM	291	if ((dma_channels[i].prio == prio) &&
4be0856f RJ	292	!dma_channels[i].name &&
4be0856f RJ	293	!pxad_toggle_reserved_channel(i)) {
1da177e4 LT	294	found = 1;
	295	break;
	296	}
	297	}
99532559 NP	298	/* if requested prio group is full, try a hier priority */
99532559 NP	299	} while (!found && prio--);
1da177e4 LT	300
	301	if (found) {
	302	DCSR(i) = DCSR_STARTINTR\|DCSR_ENDINTR\|DCSR_BUSERR;
	303	dma_channels[i].name = name;
	304	dma_channels[i].irq_handler = irq_handler;
	305	dma_channels[i].data = data;
	306	} else {
	307	printk (KERN_WARNING "No more available DMA channels for %s\n", name);
	308	i = -ENODEV;
	309	}
	310
	311	local_irq_restore(flags);
	312	return i;
	313	}
43c6342b	314	EXPORT_SYMBOL(pxa_request_dma);
1da177e4 LT	315
	316	void pxa_free_dma (int dma_ch)
	317	{
	318	unsigned long flags;
	319
	320	if (!dma_channels[dma_ch].name) {
	321	printk (KERN_CRIT
	322	"%s: trying to free channel %d which is already freed\n",
8e86f427	323	__func__, dma_ch);
1da177e4 LT	324	return;
	325	}
	326
	327	local_irq_save(flags);
	328	DCSR(dma_ch) = DCSR_STARTINTR\|DCSR_ENDINTR\|DCSR_BUSERR;
	329	dma_channels[dma_ch].name = NULL;
4be0856f	330	pxad_toggle_reserved_channel(dma_ch);
1da177e4 LT	331	local_irq_restore(flags);
1da177e4 LT	332	}
43c6342b	333	EXPORT_SYMBOL(pxa_free_dma);
1da177e4	334
0cd61b68	335	static irqreturn_t dma_irq_handler(int irq, void *dev_id)
1da177e4	336	{
4be0856f	337	int i, dint = DINT, done = 0;
d46f5e4a RJ	338	struct dma_channel *channel;
	339
	340	while (dint) {
	341	i = __ffs(dint);
	342	dint &= (dint - 1);
	343	channel = &dma_channels[i];
	344	if (channel->name && channel->irq_handler) {
	345	channel->irq_handler(i, channel->data);
4be0856f	346	done++;
1da177e4 LT	347	}
1da177e4 LT	348	}
4be0856f RJ	349	if (done)
	350	return IRQ_HANDLED;
	351	else
	352	return IRQ_NONE;
1da177e4 LT	353	}
1da177e4 LT	354
fef1f99a	355	int __init pxa_init_dma(int irq, int num_ch)
1da177e4	356	{
f53f066c	357	int i, ret;
1da177e4	358
f53f066c EM	359	dma_channels = kzalloc(sizeof(struct dma_channel) * num_ch, GFP_KERNEL);
	360	if (dma_channels == NULL)
	361	return -ENOMEM;
	362
f53f066c EM	363	/* dma channel priorities on pxa2xx processors:
	364	* ch 0 - 3, 16 - 19 <--> (0) DMA_PRIO_HIGH
	365	* ch 4 - 7, 20 - 23 <--> (1) DMA_PRIO_MEDIUM
	366	* ch 8 - 15, 24 - 31 <--> (2) DMA_PRIO_LOW
	367	*/
26a55226 EM	368	for (i = 0; i < num_ch; i++) {
26a55226 EM	369	DCSR(i) = 0;
f53f066c	370	dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW);
d294948c	371	spin_lock_init(&dma_channels[i].lock);
26a55226 EM	372	}
26a55226 EM	373
4be0856f RJ	374	ret = request_irq(irq, dma_irq_handler, IRQF_SHARED, "DMA",
4be0856f RJ	375	dma_channels);
26a55226 EM	376	if (ret) {
	377	printk (KERN_CRIT "Wow! Can't register IRQ for DMA\n");
	378	kfree(dma_channels);
	379	return ret;
	380	}
f53f066c	381	num_dma_channels = num_ch;
d294948c RJ	382
	383	pxa_dma_init_debugfs();
	384
f53f066c EM	385	return 0;
f53f066c EM	386	}