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a21765a7 BD |
1 | # Copyright 2007 Simtec Electronics |
2 | # | |
3 | # Licensed under GPLv2 | |
4 | ||
5 | config PLAT_S3C24XX | |
6 | bool | |
b130d5c2 | 7 | depends on ARCH_S3C24XX |
bcae8aeb | 8 | default y |
7d477a04 | 9 | select NO_IOPORT |
bb2b180c | 10 | select ARCH_REQUIRE_GPIOLIB |
258b78c3 | 11 | select S3C_DEV_NAND |
a21765a7 | 12 | help |
d58153d8 | 13 | Base platform code for any Samsung S3C24XX device |
a21765a7 | 14 | |
b8870605 BD |
15 | if PLAT_S3C24XX |
16 | ||
89f1fa08 BD |
17 | # low-level serial option nodes |
18 | ||
19 | config CPU_LLSERIAL_S3C2410_ONLY | |
20 | bool | |
21 | default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440 | |
22 | ||
23 | config CPU_LLSERIAL_S3C2440_ONLY | |
24 | bool | |
25 | default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410 | |
26 | ||
27 | config CPU_LLSERIAL_S3C2410 | |
28 | bool | |
29 | help | |
30 | Selected if there is an S3C2410 (or register compatible) serial | |
31 | low-level implementation needed | |
32 | ||
33 | config CPU_LLSERIAL_S3C2440 | |
34 | bool | |
35 | help | |
36 | Selected if there is an S3C2440 (or register compatible) serial | |
37 | low-level implementation needed | |
38 | ||
1b3ba688 BD |
39 | # code that is shared between a number of the s3c24xx implementations |
40 | ||
41 | config S3C2410_CLOCK | |
42 | bool | |
43 | help | |
44 | Clock code for the S3C2410, and similar processors which | |
45 | is currently includes the S3C2410, S3C2440, S3C2442. | |
46 | ||
93bc6b63 BD |
47 | config S3C24XX_DCLK |
48 | bool | |
49 | help | |
50 | Clock code for supporting DCLK/CLKOUT on S3C24XX architectures | |
51 | ||
e2178d43 BD |
52 | # gpio configurations |
53 | ||
54 | config S3C24XX_GPIO_EXTRA | |
55 | int | |
56 | default 128 if S3C24XX_GPIO_EXTRA128 | |
57 | default 64 if S3C24XX_GPIO_EXTRA64 | |
14477095 | 58 | default 16 if ARCH_H1940 |
e2178d43 BD |
59 | default 0 |
60 | ||
61 | config S3C24XX_GPIO_EXTRA64 | |
62 | bool | |
63 | help | |
64 | Add an extra 64 gpio numbers to the available GPIO pool. This is | |
65 | available for boards that need extra gpios for external devices. | |
66 | ||
67 | config S3C24XX_GPIO_EXTRA128 | |
68 | bool | |
69 | help | |
70 | Add an extra 128 gpio numbers to the available GPIO pool. This is | |
71 | available for boards that need extra gpios for external devices. | |
72 | ||
85fd6d63 | 73 | config S3C24XX_DMA |
a21765a7 | 74 | bool "S3C2410 DMA support" |
b130d5c2 | 75 | depends on ARCH_S3C24XX |
97c1b145 | 76 | select S3C_DMA |
a21765a7 BD |
77 | help |
78 | S3C2410 DMA support. This is needed for drivers like sound which | |
79 | use the S3C2410's DMA system to move data to and from the | |
80 | peripheral blocks. | |
81 | ||
82 | config S3C2410_DMA_DEBUG | |
83 | bool "S3C2410 DMA support debug" | |
b130d5c2 | 84 | depends on ARCH_S3C24XX && S3C2410_DMA |
a21765a7 BD |
85 | help |
86 | Enable debugging output for the DMA code. This option sends info | |
87 | to the kernel log, at priority KERN_DEBUG. | |
88 | ||
b2a6cf3b BD |
89 | # common code for s3c24xx based machines, such as the SMDKs. |
90 | ||
831a6fcb BD |
91 | # cpu frequency items common between s3c2410 and s3c2440/s3c2442 |
92 | ||
93 | config S3C2410_IOTIMING | |
94 | bool | |
95 | depends on CPU_FREQ_S3C24XX | |
96 | help | |
97 | Internal node to select io timing code that is common to the s3c2410 | |
98 | and s3c2440/s3c2442 cpu frequency support. | |
99 | ||
a24c091d BD |
100 | config S3C2410_CPUFREQ_UTILS |
101 | bool | |
102 | depends on CPU_FREQ_S3C24XX | |
103 | help | |
104 | Internal node to select timing code that is common to the s3c2410 | |
105 | and s3c2440/s3c244 cpu frequency support. | |
106 | ||
140780ab BD |
107 | # cpu frequency support common to s3c2412, s3c2413 and s3c2442 |
108 | ||
109 | config S3C2412_IOTIMING | |
110 | bool | |
111 | depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443) | |
112 | help | |
113 | Intel node to select io timing code that is common to the s3c2412 | |
114 | and the s3c2443. | |
115 | ||
b8870605 | 116 | endif |