[deliverable/linux.git] / arch / arm / plat-s3c24xx / gpiolib.c

/* linux/arch/arm/plat-s3c24xx/gpiolib.c
 *
 * Copyright (c) 2008 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C24XX GPIOlib support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
*/

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/gpio.h>

#include <mach/gpio-core.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <plat/pm.h>

#include <mach/regs-gpio.h>

static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
{
	return -EINVAL;
}

static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
					unsigned offset, int value)
{
	struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
	void __iomem *base = ourchip->base;
	unsigned long flags;
	unsigned long dat;
	unsigned long con;

	local_irq_save(flags);

	con = __raw_readl(base + 0x00);
	dat = __raw_readl(base + 0x04);

	dat &= ~(1 << offset);
	if (value)
		dat |= 1 << offset;

	__raw_writel(dat, base + 0x04);

	con &= ~(1 << offset);

	__raw_writel(con, base + 0x00);
	__raw_writel(dat, base + 0x04);

	local_irq_restore(flags);
	return 0;
}

static int s3c24xx_gpiolib_bankf_toirq(struct gpio_chip *chip, unsigned offset)
{
	if (offset < 4)
		return IRQ_EINT0 + offset;
	
	if (offset < 8)
		return IRQ_EINT4 + offset - 4;
	
	return -EINVAL;
}

static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
{
	return IRQ_EINT8 + offset;
}

struct s3c_gpio_chip s3c24xx_gpios[] = {
	[0] = {
		.base	= S3C24XX_GPIO_BASE(S3C2410_GPA0),
		.pm	= __gpio_pm(&s3c_gpio_pm_1bit),
		.chip	= {
			.base			= S3C2410_GPA0,
			.owner			= THIS_MODULE,
			.label			= "GPIOA",
			.ngpio			= 24,
			.direction_input	= s3c24xx_gpiolib_banka_input,
			.direction_output	= s3c24xx_gpiolib_banka_output,
		},
	},
	[1] = {
		.base	= S3C24XX_GPIO_BASE(S3C2410_GPB0),
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPB0,
			.owner			= THIS_MODULE,
			.label			= "GPIOB",
			.ngpio			= 16,
		},
	},
	[2] = {
		.base	= S3C24XX_GPIO_BASE(S3C2410_GPC0),
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPC0,
			.owner			= THIS_MODULE,
			.label			= "GPIOC",
			.ngpio			= 16,
		},
	},
	[3] = {
		.base	= S3C24XX_GPIO_BASE(S3C2410_GPD0),
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPD0,
			.owner			= THIS_MODULE,
			.label			= "GPIOD",
			.ngpio			= 16,
		},
	},
	[4] = {
		.base	= S3C24XX_GPIO_BASE(S3C2410_GPE0),
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPE0,
			.label			= "GPIOE",
			.owner			= THIS_MODULE,
			.ngpio			= 16,
		},
	},
	[5] = {
		.base	= S3C24XX_GPIO_BASE(S3C2410_GPF0),
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPF0,
			.owner			= THIS_MODULE,
			.label			= "GPIOF",
			.ngpio			= 8,
			.to_irq			= s3c24xx_gpiolib_bankf_toirq,
		},
	},
	[6] = {
		.base	= S3C24XX_GPIO_BASE(S3C2410_GPG0),
		.pm	= __gpio_pm(&s3c_gpio_pm_2bit),
		.chip	= {
			.base			= S3C2410_GPG0,
			.owner			= THIS_MODULE,
			.label			= "GPIOG",
			.ngpio			= 10,
			.to_irq			= s3c24xx_gpiolib_bankg_toirq,
		},
	},
};

static __init int s3c24xx_gpiolib_init(void)
{
	struct s3c_gpio_chip *chip = s3c24xx_gpios;
	int gpn;

	for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++)
		s3c_gpiolib_add(chip);

	return 0;
}

arch_initcall(s3c24xx_gpiolib_init);
Commit	Line	Data
f348a2a2 BD	1	/* linux/arch/arm/plat-s3c24xx/gpiolib.c
	2	*
	3	* Copyright (c) 2008 Simtec Electronics
	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
	7	* S3C24XX GPIOlib support
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/module.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/ioport.h>
	19	#include <linux/io.h>
	20	#include <linux/gpio.h>
	21
ec5cfbfc	22	#include <mach/gpio-core.h>
a09e64fb	23	#include <mach/hardware.h>
f348a2a2	24	#include <asm/irq.h>
d87964c4	25	#include <plat/pm.h>
f348a2a2	26
a09e64fb	27	#include <mach/regs-gpio.h>
f348a2a2	28
f348a2a2 BD	29	static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
	30	{
	31	return -EINVAL;
	32	}
	33
	34	static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
	35	unsigned offset, int value)
	36	{
7db6c82a	37	struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
f348a2a2 BD	38	void __iomem *base = ourchip->base;
	39	unsigned long flags;
	40	unsigned long dat;
	41	unsigned long con;
	42
	43	local_irq_save(flags);
	44
	45	con = __raw_readl(base + 0x00);
	46	dat = __raw_readl(base + 0x04);
	47
	48	dat &= ~(1 << offset);
	49	if (value)
	50	dat \|= 1 << offset;
	51
	52	__raw_writel(dat, base + 0x04);
	53
	54	con &= ~(1 << offset);
	55
	56	__raw_writel(con, base + 0x00);
	57	__raw_writel(dat, base + 0x04);
	58
	59	local_irq_restore(flags);
	60	return 0;
	61	}
	62
43ae6599 BD	63	static int s3c24xx_gpiolib_bankf_toirq(struct gpio_chip *chip, unsigned offset)
	64	{
	65	if (offset < 4)
	66	return IRQ_EINT0 + offset;
	67
	68	if (offset < 8)
	69	return IRQ_EINT4 + offset - 4;
	70
	71	return -EINVAL;
	72	}
	73
	74	static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
	75	{
	76	return IRQ_EINT8 + offset;
	77	}
	78
21b23664	79	struct s3c_gpio_chip s3c24xx_gpios[] = {
f348a2a2 BD	80	[0] = {
f348a2a2 BD	81	.base = S3C24XX_GPIO_BASE(S3C2410_GPA0),
d87964c4	82	.pm = __gpio_pm(&s3c_gpio_pm_1bit),
f348a2a2 BD	83	.chip = {
	84	.base = S3C2410_GPA0,
	85	.owner = THIS_MODULE,
	86	.label = "GPIOA",
	87	.ngpio = 24,
	88	.direction_input = s3c24xx_gpiolib_banka_input,
	89	.direction_output = s3c24xx_gpiolib_banka_output,
f348a2a2 BD	90	},
	91	},
	92	[1] = {
	93	.base = S3C24XX_GPIO_BASE(S3C2410_GPB0),
d87964c4	94	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
f348a2a2 BD	95	.chip = {
	96	.base = S3C2410_GPB0,
	97	.owner = THIS_MODULE,
	98	.label = "GPIOB",
	99	.ngpio = 16,
f348a2a2 BD	100	},
	101	},
	102	[2] = {
	103	.base = S3C24XX_GPIO_BASE(S3C2410_GPC0),
d87964c4	104	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
f348a2a2 BD	105	.chip = {
	106	.base = S3C2410_GPC0,
	107	.owner = THIS_MODULE,
	108	.label = "GPIOC",
	109	.ngpio = 16,
f348a2a2 BD	110	},
	111	},
	112	[3] = {
	113	.base = S3C24XX_GPIO_BASE(S3C2410_GPD0),
d87964c4	114	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
f348a2a2 BD	115	.chip = {
	116	.base = S3C2410_GPD0,
	117	.owner = THIS_MODULE,
	118	.label = "GPIOD",
	119	.ngpio = 16,
f348a2a2 BD	120	},
	121	},
	122	[4] = {
	123	.base = S3C24XX_GPIO_BASE(S3C2410_GPE0),
d87964c4	124	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
f348a2a2 BD	125	.chip = {
	126	.base = S3C2410_GPE0,
	127	.label = "GPIOE",
	128	.owner = THIS_MODULE,
	129	.ngpio = 16,
f348a2a2 BD	130	},
	131	},
	132	[5] = {
	133	.base = S3C24XX_GPIO_BASE(S3C2410_GPF0),
d87964c4	134	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
f348a2a2 BD	135	.chip = {
	136	.base = S3C2410_GPF0,
	137	.owner = THIS_MODULE,
	138	.label = "GPIOF",
	139	.ngpio = 8,
43ae6599	140	.to_irq = s3c24xx_gpiolib_bankf_toirq,
f348a2a2 BD	141	},
	142	},
	143	[6] = {
	144	.base = S3C24XX_GPIO_BASE(S3C2410_GPG0),
d87964c4	145	.pm = __gpio_pm(&s3c_gpio_pm_2bit),
f348a2a2 BD	146	.chip = {
	147	.base = S3C2410_GPG0,
	148	.owner = THIS_MODULE,
	149	.label = "GPIOG",
	150	.ngpio = 10,
43ae6599	151	.to_irq = s3c24xx_gpiolib_bankg_toirq,
f348a2a2 BD	152	},
	153	},
	154	};
	155
	156	static __init int s3c24xx_gpiolib_init(void)
	157	{
21b23664	158	struct s3c_gpio_chip *chip = s3c24xx_gpios;
f348a2a2 BD	159	int gpn;
f348a2a2 BD	160
21b23664	161	for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++)
7db6c82a	162	s3c_gpiolib_add(chip);
f348a2a2 BD	163
	164	return 0;
	165	}
	166
	167	arch_initcall(s3c24xx_gpiolib_init);