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1 | /* linux/arch/arm/plat-s3c24xx/pm.c |
2 | * | |
3 | * Copyright (c) 2004,2006 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * S3C24XX Power Manager (Suspend-To-RAM) support | |
7 | * | |
8 | * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | * Parts based on arch/arm/mach-pxa/pm.c | |
25 | * | |
26 | * Thanks to Dimitry Andric for debugging | |
27 | */ | |
28 | ||
29 | #include <linux/init.h> | |
30 | #include <linux/suspend.h> | |
31 | #include <linux/errno.h> | |
32 | #include <linux/time.h> | |
33 | #include <linux/interrupt.h> | |
34 | #include <linux/crc32.h> | |
35 | #include <linux/ioport.h> | |
a21765a7 | 36 | #include <linux/serial_core.h> |
fced80c7 | 37 | #include <linux/io.h> |
a21765a7 BD |
38 | |
39 | #include <asm/cacheflush.h> | |
a09e64fb | 40 | #include <mach/hardware.h> |
a21765a7 | 41 | |
a2b7ba9c | 42 | #include <plat/regs-serial.h> |
a09e64fb RK |
43 | #include <mach/regs-clock.h> |
44 | #include <mach/regs-gpio.h> | |
45 | #include <mach/regs-mem.h> | |
46 | #include <mach/regs-irq.h> | |
a21765a7 BD |
47 | |
48 | #include <asm/mach/time.h> | |
49 | ||
a2b7ba9c | 50 | #include <plat/pm.h> |
a21765a7 | 51 | |
a21765a7 BD |
52 | |
53 | #define PFX "s3c24xx-pm: " | |
54 | ||
55 | static struct sleep_save core_save[] = { | |
56 | SAVE_ITEM(S3C2410_LOCKTIME), | |
57 | SAVE_ITEM(S3C2410_CLKCON), | |
58 | ||
59 | /* we restore the timings here, with the proviso that the board | |
60 | * brings the system up in an slower, or equal frequency setting | |
61 | * to the original system. | |
62 | * | |
63 | * if we cannot guarantee this, then things are going to go very | |
64 | * wrong here, as we modify the refresh and both pll settings. | |
65 | */ | |
66 | ||
67 | SAVE_ITEM(S3C2410_BWSCON), | |
68 | SAVE_ITEM(S3C2410_BANKCON0), | |
69 | SAVE_ITEM(S3C2410_BANKCON1), | |
70 | SAVE_ITEM(S3C2410_BANKCON2), | |
71 | SAVE_ITEM(S3C2410_BANKCON3), | |
72 | SAVE_ITEM(S3C2410_BANKCON4), | |
73 | SAVE_ITEM(S3C2410_BANKCON5), | |
74 | ||
e425382e | 75 | #ifndef CONFIG_CPU_FREQ |
a21765a7 BD |
76 | SAVE_ITEM(S3C2410_CLKDIVN), |
77 | SAVE_ITEM(S3C2410_MPLLCON), | |
e425382e BD |
78 | SAVE_ITEM(S3C2410_REFRESH), |
79 | #endif | |
a21765a7 BD |
80 | SAVE_ITEM(S3C2410_UPLLCON), |
81 | SAVE_ITEM(S3C2410_CLKSLOW), | |
a21765a7 BD |
82 | }; |
83 | ||
62feee64 BD |
84 | static struct gpio_sleep { |
85 | void __iomem *base; | |
86 | unsigned int gpcon; | |
87 | unsigned int gpdat; | |
88 | unsigned int gpup; | |
89 | } gpio_save[] = { | |
90 | [0] = { | |
91 | .base = S3C2410_GPACON, | |
92 | }, | |
93 | [1] = { | |
94 | .base = S3C2410_GPBCON, | |
95 | }, | |
96 | [2] = { | |
97 | .base = S3C2410_GPCCON, | |
98 | }, | |
99 | [3] = { | |
100 | .base = S3C2410_GPDCON, | |
101 | }, | |
102 | [4] = { | |
103 | .base = S3C2410_GPECON, | |
104 | }, | |
105 | [5] = { | |
106 | .base = S3C2410_GPFCON, | |
107 | }, | |
108 | [6] = { | |
109 | .base = S3C2410_GPGCON, | |
110 | }, | |
111 | [7] = { | |
112 | .base = S3C2410_GPHCON, | |
113 | }, | |
114 | }; | |
a21765a7 | 115 | |
62feee64 | 116 | static struct sleep_save misc_save[] = { |
a21765a7 BD |
117 | SAVE_ITEM(S3C2410_DCLKCON), |
118 | }; | |
119 | ||
120 | #ifdef CONFIG_S3C2410_PM_DEBUG | |
121 | ||
122 | #define SAVE_UART(va) \ | |
123 | SAVE_ITEM((va) + S3C2410_ULCON), \ | |
124 | SAVE_ITEM((va) + S3C2410_UCON), \ | |
125 | SAVE_ITEM((va) + S3C2410_UFCON), \ | |
126 | SAVE_ITEM((va) + S3C2410_UMCON), \ | |
127 | SAVE_ITEM((va) + S3C2410_UBRDIV) | |
128 | ||
129 | static struct sleep_save uart_save[] = { | |
130 | SAVE_UART(S3C24XX_VA_UART0), | |
131 | SAVE_UART(S3C24XX_VA_UART1), | |
132 | #ifndef CONFIG_CPU_S3C2400 | |
133 | SAVE_UART(S3C24XX_VA_UART2), | |
134 | #endif | |
135 | }; | |
136 | ||
137 | /* debug | |
138 | * | |
139 | * we send the debug to printascii() to allow it to be seen if the | |
140 | * system never wakes up from the sleep | |
141 | */ | |
142 | ||
a21765a7 BD |
143 | static void s3c2410_pm_debug_init(void) |
144 | { | |
145 | unsigned long tmp = __raw_readl(S3C2410_CLKCON); | |
146 | ||
147 | /* re-start uart clocks */ | |
148 | tmp |= S3C2410_CLKCON_UART0; | |
149 | tmp |= S3C2410_CLKCON_UART1; | |
150 | tmp |= S3C2410_CLKCON_UART2; | |
151 | ||
152 | __raw_writel(tmp, S3C2410_CLKCON); | |
153 | udelay(10); | |
154 | } | |
155 | ||
a21765a7 | 156 | #else |
a21765a7 BD |
157 | #define s3c2410_pm_debug_init() do { } while(0) |
158 | ||
159 | static struct sleep_save uart_save[] = {}; | |
160 | #endif | |
161 | ||
162 | #if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0 | |
163 | ||
164 | /* suspend checking code... | |
165 | * | |
166 | * this next area does a set of crc checks over all the installed | |
167 | * memory, so the system can verify if the resume was ok. | |
168 | * | |
169 | * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC, | |
170 | * increasing it will mean that the area corrupted will be less easy to spot, | |
171 | * and reducing the size will cause the CRC save area to grow | |
172 | */ | |
173 | ||
174 | #define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024) | |
175 | ||
176 | static u32 crc_size; /* size needed for the crc block */ | |
177 | static u32 *crcs; /* allocated over suspend/resume */ | |
178 | ||
179 | typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg); | |
180 | ||
181 | /* s3c2410_pm_run_res | |
182 | * | |
183 | * go thorugh the given resource list, and look for system ram | |
184 | */ | |
185 | ||
186 | static void s3c2410_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg) | |
187 | { | |
188 | while (ptr != NULL) { | |
189 | if (ptr->child != NULL) | |
190 | s3c2410_pm_run_res(ptr->child, fn, arg); | |
191 | ||
192 | if ((ptr->flags & IORESOURCE_MEM) && | |
193 | strcmp(ptr->name, "System RAM") == 0) { | |
6419711a | 194 | S3C_PMDBG("Found system RAM at %08lx..%08lx\n", |
a21765a7 BD |
195 | ptr->start, ptr->end); |
196 | arg = (fn)(ptr, arg); | |
197 | } | |
198 | ||
199 | ptr = ptr->sibling; | |
200 | } | |
201 | } | |
202 | ||
203 | static void s3c2410_pm_run_sysram(run_fn_t fn, u32 *arg) | |
204 | { | |
205 | s3c2410_pm_run_res(&iomem_resource, fn, arg); | |
206 | } | |
207 | ||
208 | static u32 *s3c2410_pm_countram(struct resource *res, u32 *val) | |
209 | { | |
210 | u32 size = (u32)(res->end - res->start)+1; | |
211 | ||
212 | size += CHECK_CHUNKSIZE-1; | |
213 | size /= CHECK_CHUNKSIZE; | |
214 | ||
6419711a | 215 | S3C_PMDBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size); |
a21765a7 BD |
216 | |
217 | *val += size * sizeof(u32); | |
218 | return val; | |
219 | } | |
220 | ||
221 | /* s3c2410_pm_prepare_check | |
222 | * | |
223 | * prepare the necessary information for creating the CRCs. This | |
224 | * must be done before the final save, as it will require memory | |
225 | * allocating, and thus touching bits of the kernel we do not | |
226 | * know about. | |
227 | */ | |
228 | ||
229 | static void s3c2410_pm_check_prepare(void) | |
230 | { | |
231 | crc_size = 0; | |
232 | ||
233 | s3c2410_pm_run_sysram(s3c2410_pm_countram, &crc_size); | |
234 | ||
6419711a | 235 | S3C_PMDBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size); |
a21765a7 BD |
236 | |
237 | crcs = kmalloc(crc_size+4, GFP_KERNEL); | |
238 | if (crcs == NULL) | |
239 | printk(KERN_ERR "Cannot allocated CRC save area\n"); | |
240 | } | |
241 | ||
242 | static u32 *s3c2410_pm_makecheck(struct resource *res, u32 *val) | |
243 | { | |
244 | unsigned long addr, left; | |
245 | ||
246 | for (addr = res->start; addr < res->end; | |
247 | addr += CHECK_CHUNKSIZE) { | |
248 | left = res->end - addr; | |
249 | ||
250 | if (left > CHECK_CHUNKSIZE) | |
251 | left = CHECK_CHUNKSIZE; | |
252 | ||
253 | *val = crc32_le(~0, phys_to_virt(addr), left); | |
254 | val++; | |
255 | } | |
256 | ||
257 | return val; | |
258 | } | |
259 | ||
260 | /* s3c2410_pm_check_store | |
261 | * | |
262 | * compute the CRC values for the memory blocks before the final | |
263 | * sleep. | |
264 | */ | |
265 | ||
266 | static void s3c2410_pm_check_store(void) | |
267 | { | |
268 | if (crcs != NULL) | |
269 | s3c2410_pm_run_sysram(s3c2410_pm_makecheck, crcs); | |
270 | } | |
271 | ||
272 | /* in_region | |
273 | * | |
274 | * return TRUE if the area defined by ptr..ptr+size contatins the | |
275 | * what..what+whatsz | |
276 | */ | |
277 | ||
278 | static inline int in_region(void *ptr, int size, void *what, size_t whatsz) | |
279 | { | |
280 | if ((what+whatsz) < ptr) | |
281 | return 0; | |
282 | ||
283 | if (what > (ptr+size)) | |
284 | return 0; | |
285 | ||
286 | return 1; | |
287 | } | |
288 | ||
289 | static u32 *s3c2410_pm_runcheck(struct resource *res, u32 *val) | |
290 | { | |
6419711a | 291 | void *save_at = phys_to_virt(s3c_sleep_save_phys); |
a21765a7 BD |
292 | unsigned long addr; |
293 | unsigned long left; | |
294 | void *ptr; | |
295 | u32 calc; | |
296 | ||
297 | for (addr = res->start; addr < res->end; | |
298 | addr += CHECK_CHUNKSIZE) { | |
299 | left = res->end - addr; | |
300 | ||
301 | if (left > CHECK_CHUNKSIZE) | |
302 | left = CHECK_CHUNKSIZE; | |
303 | ||
304 | ptr = phys_to_virt(addr); | |
305 | ||
306 | if (in_region(ptr, left, crcs, crc_size)) { | |
6419711a | 307 | S3C_PMDBG("skipping %08lx, has crc block in\n", addr); |
a21765a7 BD |
308 | goto skip_check; |
309 | } | |
310 | ||
311 | if (in_region(ptr, left, save_at, 32*4 )) { | |
6419711a | 312 | S3C_PMDBG("skipping %08lx, has save block in\n", addr); |
a21765a7 BD |
313 | goto skip_check; |
314 | } | |
315 | ||
316 | /* calculate and check the checksum */ | |
317 | ||
318 | calc = crc32_le(~0, ptr, left); | |
319 | if (calc != *val) { | |
320 | printk(KERN_ERR PFX "Restore CRC error at " | |
321 | "%08lx (%08x vs %08x)\n", addr, calc, *val); | |
322 | ||
6419711a | 323 | S3C_PMDBG("Restore CRC error at %08lx (%08x vs %08x)\n", |
a21765a7 BD |
324 | addr, calc, *val); |
325 | } | |
326 | ||
327 | skip_check: | |
328 | val++; | |
329 | } | |
330 | ||
331 | return val; | |
332 | } | |
333 | ||
334 | /* s3c2410_pm_check_restore | |
335 | * | |
336 | * check the CRCs after the restore event and free the memory used | |
337 | * to hold them | |
338 | */ | |
339 | ||
340 | static void s3c2410_pm_check_restore(void) | |
341 | { | |
342 | if (crcs != NULL) { | |
343 | s3c2410_pm_run_sysram(s3c2410_pm_runcheck, crcs); | |
344 | kfree(crcs); | |
345 | crcs = NULL; | |
346 | } | |
347 | } | |
348 | ||
349 | #else | |
350 | ||
351 | #define s3c2410_pm_check_prepare() do { } while(0) | |
352 | #define s3c2410_pm_check_restore() do { } while(0) | |
353 | #define s3c2410_pm_check_store() do { } while(0) | |
354 | #endif | |
355 | ||
a21765a7 BD |
356 | /* s3c2410_pm_show_resume_irqs |
357 | * | |
358 | * print any IRQs asserted at resume time (ie, we woke from) | |
359 | */ | |
360 | ||
361 | static void s3c2410_pm_show_resume_irqs(int start, unsigned long which, | |
362 | unsigned long mask) | |
363 | { | |
364 | int i; | |
365 | ||
366 | which &= ~mask; | |
367 | ||
368 | for (i = 0; i <= 31; i++) { | |
369 | if ((which) & (1L<<i)) { | |
6419711a | 370 | S3C_PMDBG("IRQ %d asserted at resume\n", start+i); |
a21765a7 BD |
371 | } |
372 | } | |
373 | } | |
374 | ||
375 | /* s3c2410_pm_check_resume_pin | |
376 | * | |
377 | * check to see if the pin is configured correctly for sleep mode, and | |
378 | * make any necessary adjustments if it is not | |
379 | */ | |
380 | ||
381 | static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs) | |
382 | { | |
383 | unsigned long irqstate; | |
384 | unsigned long pinstate; | |
385 | int irq = s3c2410_gpio_getirq(pin); | |
386 | ||
387 | if (irqoffs < 4) | |
388 | irqstate = s3c_irqwake_intmask & (1L<<irqoffs); | |
389 | else | |
390 | irqstate = s3c_irqwake_eintmask & (1L<<irqoffs); | |
391 | ||
392 | pinstate = s3c2410_gpio_getcfg(pin); | |
393 | ||
394 | if (!irqstate) { | |
395 | if (pinstate == S3C2410_GPIO_IRQ) | |
6419711a | 396 | S3C_PMDBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin); |
a21765a7 BD |
397 | } else { |
398 | if (pinstate == S3C2410_GPIO_IRQ) { | |
6419711a | 399 | S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin); |
a21765a7 BD |
400 | s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT); |
401 | } | |
402 | } | |
403 | } | |
404 | ||
405 | /* s3c2410_pm_configure_extint | |
406 | * | |
407 | * configure all external interrupt pins | |
408 | */ | |
409 | ||
410 | static void s3c2410_pm_configure_extint(void) | |
411 | { | |
412 | int pin; | |
413 | ||
414 | /* for each of the external interrupts (EINT0..EINT15) we | |
415 | * need to check wether it is an external interrupt source, | |
416 | * and then configure it as an input if it is not | |
417 | */ | |
418 | ||
419 | for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) { | |
420 | s3c2410_pm_check_resume_pin(pin, pin - S3C2410_GPF0); | |
421 | } | |
422 | ||
423 | for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) { | |
424 | s3c2410_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8); | |
425 | } | |
426 | } | |
427 | ||
62feee64 BD |
428 | /* offsets for CON/DAT/UP registers */ |
429 | ||
430 | #define OFFS_CON (S3C2410_GPACON - S3C2410_GPACON) | |
431 | #define OFFS_DAT (S3C2410_GPADAT - S3C2410_GPACON) | |
432 | #define OFFS_UP (S3C2410_GPBUP - S3C2410_GPBCON) | |
433 | ||
434 | /* s3c2410_pm_save_gpios() | |
435 | * | |
436 | * Save the state of the GPIOs | |
437 | */ | |
438 | ||
439 | static void s3c2410_pm_save_gpios(void) | |
440 | { | |
441 | struct gpio_sleep *gps = gpio_save; | |
442 | unsigned int gpio; | |
443 | ||
444 | for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) { | |
445 | void __iomem *base = gps->base; | |
446 | ||
447 | gps->gpcon = __raw_readl(base + OFFS_CON); | |
448 | gps->gpdat = __raw_readl(base + OFFS_DAT); | |
449 | ||
450 | if (gpio > 0) | |
451 | gps->gpup = __raw_readl(base + OFFS_UP); | |
452 | ||
453 | } | |
454 | } | |
455 | ||
456 | /* Test whether the given masked+shifted bits of an GPIO configuration | |
457 | * are one of the SFN (special function) modes. */ | |
458 | ||
459 | static inline int is_sfn(unsigned long con) | |
460 | { | |
461 | return (con == 2 || con == 3); | |
462 | } | |
463 | ||
464 | /* Test if the given masked+shifted GPIO configuration is an input */ | |
465 | ||
466 | static inline int is_in(unsigned long con) | |
467 | { | |
468 | return con == 0; | |
469 | } | |
470 | ||
471 | /* Test if the given masked+shifted GPIO configuration is an output */ | |
472 | ||
473 | static inline int is_out(unsigned long con) | |
474 | { | |
475 | return con == 1; | |
476 | } | |
477 | ||
478 | /* s3c2410_pm_restore_gpio() | |
479 | * | |
480 | * Restore one of the GPIO banks that was saved during suspend. This is | |
481 | * not as simple as once thought, due to the possibility of glitches | |
482 | * from the order that the CON and DAT registers are set in. | |
483 | * | |
484 | * The three states the pin can be are {IN,OUT,SFN} which gives us 9 | |
485 | * combinations of changes to check. Three of these, if the pin stays | |
486 | * in the same configuration can be discounted. This leaves us with | |
487 | * the following: | |
488 | * | |
489 | * { IN => OUT } Change DAT first | |
490 | * { IN => SFN } Change CON first | |
491 | * { OUT => SFN } Change CON first, so new data will not glitch | |
492 | * { OUT => IN } Change CON first, so new data will not glitch | |
493 | * { SFN => IN } Change CON first | |
494 | * { SFN => OUT } Change DAT first, so new data will not glitch [1] | |
495 | * | |
496 | * We do not currently deal with the UP registers as these control | |
497 | * weak resistors, so a small delay in change should not need to bring | |
498 | * these into the calculations. | |
499 | * | |
500 | * [1] this assumes that writing to a pin DAT whilst in SFN will set the | |
501 | * state for when it is next output. | |
502 | */ | |
503 | ||
504 | static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps) | |
505 | { | |
506 | void __iomem *base = gps->base; | |
507 | unsigned long gps_gpcon = gps->gpcon; | |
508 | unsigned long gps_gpdat = gps->gpdat; | |
509 | unsigned long old_gpcon; | |
510 | unsigned long old_gpdat; | |
511 | unsigned long old_gpup = 0x0; | |
512 | unsigned long gpcon; | |
513 | int nr; | |
514 | ||
515 | old_gpcon = __raw_readl(base + OFFS_CON); | |
516 | old_gpdat = __raw_readl(base + OFFS_DAT); | |
517 | ||
518 | if (base == S3C2410_GPACON) { | |
519 | /* GPACON only has one bit per control / data and no PULLUPs. | |
520 | * GPACON[x] = 0 => Output, 1 => SFN */ | |
521 | ||
522 | /* first set all SFN bits to SFN */ | |
523 | ||
524 | gpcon = old_gpcon | gps->gpcon; | |
525 | __raw_writel(gpcon, base + OFFS_CON); | |
526 | ||
527 | /* now set all the other bits */ | |
528 | ||
529 | __raw_writel(gps_gpdat, base + OFFS_DAT); | |
530 | __raw_writel(gps_gpcon, base + OFFS_CON); | |
531 | } else { | |
532 | unsigned long old, new, mask; | |
533 | unsigned long change_mask = 0x0; | |
534 | ||
535 | old_gpup = __raw_readl(base + OFFS_UP); | |
536 | ||
537 | /* Create a change_mask of all the items that need to have | |
538 | * their CON value changed before their DAT value, so that | |
539 | * we minimise the work between the two settings. | |
540 | */ | |
541 | ||
542 | for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) { | |
543 | old = (old_gpcon & mask) >> nr; | |
544 | new = (gps_gpcon & mask) >> nr; | |
545 | ||
546 | /* If there is no change, then skip */ | |
547 | ||
548 | if (old == new) | |
549 | continue; | |
550 | ||
551 | /* If both are special function, then skip */ | |
552 | ||
553 | if (is_sfn(old) && is_sfn(new)) | |
554 | continue; | |
555 | ||
556 | /* Change is IN => OUT, do not change now */ | |
557 | ||
558 | if (is_in(old) && is_out(new)) | |
559 | continue; | |
560 | ||
561 | /* Change is SFN => OUT, do not change now */ | |
562 | ||
563 | if (is_sfn(old) && is_out(new)) | |
564 | continue; | |
565 | ||
566 | /* We should now be at the case of IN=>SFN, | |
567 | * OUT=>SFN, OUT=>IN, SFN=>IN. */ | |
568 | ||
569 | change_mask |= mask; | |
570 | } | |
571 | ||
572 | /* Write the new CON settings */ | |
573 | ||
574 | gpcon = old_gpcon & ~change_mask; | |
575 | gpcon |= gps_gpcon & change_mask; | |
576 | ||
577 | __raw_writel(gpcon, base + OFFS_CON); | |
578 | ||
579 | /* Now change any items that require DAT,CON */ | |
580 | ||
581 | __raw_writel(gps_gpdat, base + OFFS_DAT); | |
582 | __raw_writel(gps_gpcon, base + OFFS_CON); | |
583 | __raw_writel(gps->gpup, base + OFFS_UP); | |
584 | } | |
585 | ||
6419711a BD |
586 | S3C_PMDBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n", |
587 | index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat); | |
62feee64 BD |
588 | } |
589 | ||
590 | ||
591 | /** s3c2410_pm_restore_gpios() | |
592 | * | |
593 | * Restore the state of the GPIOs | |
594 | */ | |
595 | ||
596 | static void s3c2410_pm_restore_gpios(void) | |
597 | { | |
598 | struct gpio_sleep *gps = gpio_save; | |
599 | int gpio; | |
600 | ||
601 | for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) { | |
602 | s3c2410_pm_restore_gpio(gpio, gps); | |
603 | } | |
604 | } | |
605 | ||
a21765a7 BD |
606 | void (*pm_cpu_prep)(void); |
607 | void (*pm_cpu_sleep)(void); | |
608 | ||
609 | #define any_allowed(mask, allow) (((mask) & (allow)) != (allow)) | |
610 | ||
611 | /* s3c2410_pm_enter | |
612 | * | |
613 | * central control for sleep/resume process | |
614 | */ | |
615 | ||
616 | static int s3c2410_pm_enter(suspend_state_t state) | |
617 | { | |
618 | unsigned long regs_save[16]; | |
619 | ||
620 | /* ensure the debug is initialised (if enabled) */ | |
621 | ||
622 | s3c2410_pm_debug_init(); | |
623 | ||
6419711a | 624 | S3C_PMDBG("s3c2410_pm_enter(%d)\n", state); |
a21765a7 BD |
625 | |
626 | if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) { | |
627 | printk(KERN_ERR PFX "error: no cpu sleep functions set\n"); | |
628 | return -EINVAL; | |
629 | } | |
630 | ||
a21765a7 BD |
631 | /* check if we have anything to wake-up with... bad things seem |
632 | * to happen if you suspend with no wakeup (system will often | |
633 | * require a full power-cycle) | |
634 | */ | |
635 | ||
636 | if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) && | |
637 | !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) { | |
638 | printk(KERN_ERR PFX "No sources enabled for wake-up!\n"); | |
639 | printk(KERN_ERR PFX "Aborting sleep\n"); | |
640 | return -EINVAL; | |
641 | } | |
642 | ||
643 | /* prepare check area if configured */ | |
644 | ||
645 | s3c2410_pm_check_prepare(); | |
646 | ||
647 | /* store the physical address of the register recovery block */ | |
648 | ||
6419711a | 649 | s3c_sleep_save_phys = virt_to_phys(regs_save); |
a21765a7 | 650 | |
6419711a | 651 | S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys); |
a21765a7 BD |
652 | |
653 | /* save all necessary core registers not covered by the drivers */ | |
654 | ||
62feee64 | 655 | s3c2410_pm_save_gpios(); |
6419711a BD |
656 | s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save)); |
657 | s3c_pm_do_save(core_save, ARRAY_SIZE(core_save)); | |
658 | s3c_pm_do_save(uart_save, ARRAY_SIZE(uart_save)); | |
a21765a7 BD |
659 | |
660 | /* set the irq configuration for wake */ | |
661 | ||
662 | s3c2410_pm_configure_extint(); | |
663 | ||
6419711a | 664 | S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n", |
a21765a7 BD |
665 | s3c_irqwake_intmask, s3c_irqwake_eintmask); |
666 | ||
667 | __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK); | |
668 | __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK); | |
669 | ||
670 | /* ack any outstanding external interrupts before we go to sleep */ | |
671 | ||
672 | __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND); | |
673 | __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); | |
674 | __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); | |
675 | ||
6cbdc8c5 | 676 | /* call cpu specific preparation */ |
a21765a7 BD |
677 | |
678 | pm_cpu_prep(); | |
679 | ||
680 | /* flush cache back to ram */ | |
681 | ||
682 | flush_cache_all(); | |
683 | ||
684 | s3c2410_pm_check_store(); | |
685 | ||
686 | /* send the cpu to sleep... */ | |
687 | ||
688 | __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */ | |
689 | ||
690 | /* s3c2410_cpu_save will also act as our return point from when | |
691 | * we resume as it saves its own register state, so use the return | |
692 | * code to differentiate return from save and return from sleep */ | |
693 | ||
694 | if (s3c2410_cpu_save(regs_save) == 0) { | |
695 | flush_cache_all(); | |
696 | pm_cpu_sleep(); | |
697 | } | |
698 | ||
699 | /* restore the cpu state */ | |
700 | ||
701 | cpu_init(); | |
702 | ||
703 | /* restore the system state */ | |
704 | ||
6419711a BD |
705 | s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); |
706 | s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save)); | |
707 | s3c_pm_do_restore(uart_save, ARRAY_SIZE(uart_save)); | |
62feee64 | 708 | s3c2410_pm_restore_gpios(); |
a21765a7 BD |
709 | |
710 | s3c2410_pm_debug_init(); | |
711 | ||
712 | /* check what irq (if any) restored the system */ | |
713 | ||
6419711a | 714 | S3C_PMDBG("post sleep: IRQs 0x%08x, 0x%08x\n", |
a21765a7 BD |
715 | __raw_readl(S3C2410_SRCPND), |
716 | __raw_readl(S3C2410_EINTPEND)); | |
717 | ||
718 | s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND), | |
719 | s3c_irqwake_intmask); | |
720 | ||
721 | s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND), | |
722 | s3c_irqwake_eintmask); | |
723 | ||
6419711a | 724 | S3C_PMDBG("post sleep, preparing to return\n"); |
a21765a7 BD |
725 | |
726 | s3c2410_pm_check_restore(); | |
727 | ||
728 | /* ok, let's return from sleep */ | |
729 | ||
6419711a | 730 | S3C_PMDBG("S3C2410 PM Resume (post-restore)\n"); |
a21765a7 BD |
731 | return 0; |
732 | } | |
733 | ||
26398a70 | 734 | static struct platform_suspend_ops s3c2410_pm_ops = { |
a21765a7 | 735 | .enter = s3c2410_pm_enter, |
26398a70 | 736 | .valid = suspend_valid_only_mem, |
a21765a7 BD |
737 | }; |
738 | ||
739 | /* s3c2410_pm_init | |
740 | * | |
741 | * Attach the power management functions. This should be called | |
742 | * from the board specific initialisation if the board supports | |
743 | * it. | |
744 | */ | |
745 | ||
746 | int __init s3c2410_pm_init(void) | |
747 | { | |
748 | printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n"); | |
749 | ||
26398a70 | 750 | suspend_set_ops(&s3c2410_pm_ops); |
a21765a7 BD |
751 | return 0; |
752 | } |