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1da177e4 LT |
1 | /* linux/arch/arm/mach-s3c2410/clock.c |
2 | * | |
a21765a7 | 3 | * Copyright (c) 2006 Simtec Electronics |
1da177e4 LT |
4 | * Ben Dooks <ben@simtec.co.uk> |
5 | * | |
a21765a7 | 6 | * S3C2410,S3C2440,S3C2442 Clock control support |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #include <linux/init.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/list.h> | |
27 | #include <linux/errno.h> | |
28 | #include <linux/err.h> | |
edbaa603 | 29 | #include <linux/device.h> |
f8ce2547 | 30 | #include <linux/clk.h> |
00431707 | 31 | #include <linux/mutex.h> |
8e40a2f9 | 32 | #include <linux/delay.h> |
a21765a7 | 33 | #include <linux/serial_core.h> |
fced80c7 | 34 | #include <linux/io.h> |
a21765a7 BD |
35 | |
36 | #include <asm/mach/map.h> | |
1da177e4 | 37 | |
a09e64fb | 38 | #include <mach/hardware.h> |
1da177e4 | 39 | |
a2b7ba9c | 40 | #include <plat/regs-serial.h> |
a09e64fb RK |
41 | #include <mach/regs-clock.h> |
42 | #include <mach/regs-gpio.h> | |
1da177e4 | 43 | |
a2b7ba9c | 44 | #include <plat/s3c2410.h> |
d5120ae7 | 45 | #include <plat/clock.h> |
a2b7ba9c | 46 | #include <plat/cpu.h> |
1da177e4 | 47 | |
a21765a7 | 48 | int s3c2410_clkcon_enable(struct clk *clk, int enable) |
1da177e4 | 49 | { |
a21765a7 BD |
50 | unsigned int clocks = clk->ctrlbit; |
51 | unsigned long clkcon; | |
1da177e4 | 52 | |
a21765a7 | 53 | clkcon = __raw_readl(S3C2410_CLKCON); |
1da177e4 | 54 | |
a21765a7 BD |
55 | if (enable) |
56 | clkcon |= clocks; | |
c086f282 | 57 | else |
a21765a7 | 58 | clkcon &= ~clocks; |
1da177e4 | 59 | |
a21765a7 BD |
60 | /* ensure none of the special function bits set */ |
61 | clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER); | |
1da177e4 | 62 | |
a21765a7 | 63 | __raw_writel(clkcon, S3C2410_CLKCON); |
1da177e4 | 64 | |
2a513ce7 | 65 | return 0; |
1da177e4 LT |
66 | } |
67 | ||
a21765a7 | 68 | static int s3c2410_upll_enable(struct clk *clk, int enable) |
1da177e4 | 69 | { |
a21765a7 BD |
70 | unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW); |
71 | unsigned long orig = clkslow; | |
3fc3e1c0 BD |
72 | |
73 | if (enable) | |
a21765a7 | 74 | clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF; |
3fc3e1c0 | 75 | else |
a21765a7 | 76 | clkslow |= S3C2410_CLKSLOW_UCLK_OFF; |
3fc3e1c0 | 77 | |
a21765a7 | 78 | __raw_writel(clkslow, S3C2410_CLKSLOW); |
3fc3e1c0 | 79 | |
a21765a7 | 80 | /* if we started the UPLL, then allow to settle */ |
3fc3e1c0 | 81 | |
a21765a7 BD |
82 | if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF)) |
83 | udelay(200); | |
3fc3e1c0 BD |
84 | |
85 | return 0; | |
86 | } | |
87 | ||
a21765a7 BD |
88 | /* standard clock definitions */ |
89 | ||
4e04691b | 90 | static struct clk init_clocks_off[] = { |
a21765a7 BD |
91 | { |
92 | .name = "nand", | |
a21765a7 BD |
93 | .parent = &clk_h, |
94 | .enable = s3c2410_clkcon_enable, | |
95 | .ctrlbit = S3C2410_CLKCON_NAND, | |
96 | }, { | |
97 | .name = "sdi", | |
a21765a7 BD |
98 | .parent = &clk_p, |
99 | .enable = s3c2410_clkcon_enable, | |
100 | .ctrlbit = S3C2410_CLKCON_SDI, | |
101 | }, { | |
102 | .name = "adc", | |
a21765a7 BD |
103 | .parent = &clk_p, |
104 | .enable = s3c2410_clkcon_enable, | |
105 | .ctrlbit = S3C2410_CLKCON_ADC, | |
106 | }, { | |
107 | .name = "i2c", | |
a21765a7 BD |
108 | .parent = &clk_p, |
109 | .enable = s3c2410_clkcon_enable, | |
110 | .ctrlbit = S3C2410_CLKCON_IIC, | |
111 | }, { | |
112 | .name = "iis", | |
a21765a7 BD |
113 | .parent = &clk_p, |
114 | .enable = s3c2410_clkcon_enable, | |
115 | .ctrlbit = S3C2410_CLKCON_IIS, | |
116 | }, { | |
117 | .name = "spi", | |
a21765a7 BD |
118 | .parent = &clk_p, |
119 | .enable = s3c2410_clkcon_enable, | |
120 | .ctrlbit = S3C2410_CLKCON_SPI, | |
3fc3e1c0 | 121 | } |
1da177e4 LT |
122 | }; |
123 | ||
a21765a7 BD |
124 | static struct clk init_clocks[] = { |
125 | { | |
126 | .name = "lcd", | |
a21765a7 BD |
127 | .parent = &clk_h, |
128 | .enable = s3c2410_clkcon_enable, | |
129 | .ctrlbit = S3C2410_CLKCON_LCDC, | |
130 | }, { | |
131 | .name = "gpio", | |
a21765a7 BD |
132 | .parent = &clk_p, |
133 | .enable = s3c2410_clkcon_enable, | |
134 | .ctrlbit = S3C2410_CLKCON_GPIO, | |
135 | }, { | |
136 | .name = "usb-host", | |
a21765a7 BD |
137 | .parent = &clk_h, |
138 | .enable = s3c2410_clkcon_enable, | |
139 | .ctrlbit = S3C2410_CLKCON_USBH, | |
140 | }, { | |
141 | .name = "usb-device", | |
a21765a7 BD |
142 | .parent = &clk_h, |
143 | .enable = s3c2410_clkcon_enable, | |
144 | .ctrlbit = S3C2410_CLKCON_USBD, | |
145 | }, { | |
146 | .name = "timers", | |
a21765a7 BD |
147 | .parent = &clk_p, |
148 | .enable = s3c2410_clkcon_enable, | |
149 | .ctrlbit = S3C2410_CLKCON_PWMT, | |
150 | }, { | |
151 | .name = "uart", | |
e83626f2 | 152 | .devname = "s3c2410-uart.0", |
a21765a7 BD |
153 | .parent = &clk_p, |
154 | .enable = s3c2410_clkcon_enable, | |
155 | .ctrlbit = S3C2410_CLKCON_UART0, | |
156 | }, { | |
157 | .name = "uart", | |
e83626f2 | 158 | .devname = "s3c2410-uart.1", |
a21765a7 BD |
159 | .parent = &clk_p, |
160 | .enable = s3c2410_clkcon_enable, | |
161 | .ctrlbit = S3C2410_CLKCON_UART1, | |
162 | }, { | |
163 | .name = "uart", | |
e83626f2 | 164 | .devname = "s3c2410-uart.2", |
a21765a7 BD |
165 | .parent = &clk_p, |
166 | .enable = s3c2410_clkcon_enable, | |
167 | .ctrlbit = S3C2410_CLKCON_UART2, | |
168 | }, { | |
169 | .name = "rtc", | |
a21765a7 BD |
170 | .parent = &clk_p, |
171 | .enable = s3c2410_clkcon_enable, | |
172 | .ctrlbit = S3C2410_CLKCON_RTC, | |
173 | }, { | |
174 | .name = "watchdog", | |
a21765a7 BD |
175 | .parent = &clk_p, |
176 | .ctrlbit = 0, | |
177 | }, { | |
178 | .name = "usb-bus-host", | |
a21765a7 BD |
179 | .parent = &clk_usb_bus, |
180 | }, { | |
181 | .name = "usb-bus-gadget", | |
a21765a7 BD |
182 | .parent = &clk_usb_bus, |
183 | }, | |
1da177e4 LT |
184 | }; |
185 | ||
a21765a7 BD |
186 | /* s3c2410_baseclk_add() |
187 | * | |
188 | * Add all the clocks used by the s3c2410 or compatible CPUs | |
189 | * such as the S3C2440 and S3C2442. | |
190 | * | |
191 | * We cannot use a system device as we are needed before any | |
192 | * of the init-calls that initialise the devices are actually | |
193 | * done. | |
194 | */ | |
1da177e4 | 195 | |
a21765a7 | 196 | int __init s3c2410_baseclk_add(void) |
1da177e4 | 197 | { |
a21765a7 BD |
198 | unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW); |
199 | unsigned long clkcon = __raw_readl(S3C2410_CLKCON); | |
200 | struct clk *clkp; | |
201 | struct clk *xtal; | |
202 | int ret; | |
203 | int ptr; | |
1da177e4 | 204 | |
a21765a7 | 205 | clk_upll.enable = s3c2410_upll_enable; |
1da177e4 | 206 | |
a21765a7 BD |
207 | if (s3c24xx_register_clock(&clk_usb_bus) < 0) |
208 | printk(KERN_ERR "failed to register usb bus clock\n"); | |
1da177e4 | 209 | |
a21765a7 | 210 | /* register clocks from clock array */ |
1da177e4 | 211 | |
a21765a7 BD |
212 | clkp = init_clocks; |
213 | for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { | |
214 | /* ensure that we note the clock state */ | |
1da177e4 | 215 | |
a21765a7 | 216 | clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0; |
1da177e4 | 217 | |
a21765a7 BD |
218 | ret = s3c24xx_register_clock(clkp); |
219 | if (ret < 0) { | |
220 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | |
221 | clkp->name, ret); | |
222 | } | |
223 | } | |
1da177e4 | 224 | |
a21765a7 | 225 | /* We must be careful disabling the clocks we are not intending to |
3a4fa0a2 | 226 | * be using at boot time, as subsystems such as the LCD which do |
a21765a7 BD |
227 | * their own DMA requests to the bus can cause the system to lockup |
228 | * if they where in the middle of requesting bus access. | |
229 | * | |
230 | * Disabling the LCD clock if the LCD is active is very dangerous, | |
231 | * and therefore the bootloader should be careful to not enable | |
232 | * the LCD clock if it is not needed. | |
233 | */ | |
234 | ||
235 | /* install (and disable) the clocks we do not need immediately */ | |
236 | ||
4e04691b BD |
237 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
238 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | |
8e40a2f9 | 239 | |
a21765a7 | 240 | /* show the clock-slow value */ |
1da177e4 | 241 | |
a21765a7 | 242 | xtal = clk_get(NULL, "xtal"); |
1da177e4 | 243 | |
a21765a7 BD |
244 | printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n", |
245 | print_mhz(clk_get_rate(xtal) / | |
246 | ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))), | |
247 | (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast", | |
248 | (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on", | |
249 | (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on"); | |
1da177e4 | 250 | |
9d325f23 | 251 | s3c_pwmclk_init(); |
1da177e4 LT |
252 | return 0; |
253 | } |